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From: Christoph Muellner <christoph.muellner@vrull.eu>
To: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@sifive.com>,
	Jim Wilson <jim.wilson.gcc@gmail.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Waterman <andrew@sifive.com>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>,
	Cooper Qu <cooper.qu@linux.alibaba.com>,
	Lifang Xia <lifang_xia@linux.alibaba.com>,
	Yunhai Shang <yunhai@linux.alibaba.com>,
	Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH 7/7] riscv: Add basic extension support for XTheadFmv and XTheadInt
Date: Sun, 13 Nov 2022 22:46:36 +0100	[thread overview]
Message-ID: <20221113214636.2747737-8-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20221113214636.2747737-1-christoph.muellner@vrull.eu>

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch add basic support for the XTheadFmv and XTheadInt
ISA extension. As both extensions only contain instruction,
which are not supposed to be emitted by the compiler, the support
only covers awareness of the extension name in the march string
and the definition of a feature test macro.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: Add xtheadfmv and
	  xtheadint.
	* config/riscv/riscv-opts.h (MASK_XTHEADMAC): New.
	(MASK_XTHEADFMV): New.
	(TARGET_XTHEADFMV): New.
	(MASK_XTHEADINT): New.
	(TARGET_XTHEADINT): New.
	(MASK_XTHEADMEMIDX): New.
	(MASK_XTHEADSYNC): New.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadfmv.c: New test.
	* gcc.target/riscv/xtheadint.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/common/config/riscv/riscv-common.cc    |  4 ++++
 gcc/config/riscv/riscv-opts.h              | 10 +++++++---
 gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 14 ++++++++++++++
 gcc/testsuite/gcc.target/riscv/xtheadint.c | 14 ++++++++++++++
 4 files changed, 39 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 8e1449d3543..b3e6732dddd 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -228,6 +228,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"xtheadcmo", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadcondmov", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadfmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadfmv", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadint", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1263,6 +1265,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"xtheadcmo",     &gcc_options::x_riscv_xthead_subext, MASK_XTHEADCMO},
   {"xtheadcondmov", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADCONDMOV},
   {"xtheadfmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADFMEMIDX},
+  {"xtheadfmv",     &gcc_options::x_riscv_xthead_subext, MASK_XTHEADFMV},
+  {"xtheadint",     &gcc_options::x_riscv_xthead_subext, MASK_XTHEADINT},
   {"xtheadmac",     &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMAC},
   {"xtheadmemidx",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
   {"xtheadsync",    &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 18daac40dbd..c1868dcf284 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -201,11 +201,15 @@ enum stack_protector_guard {
 #define TARGET_XTHEADCONDMOV	((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0)
 #define MASK_XTHEADFMEMIDX	(1 << 5)
 #define TARGET_XTHEADFMEMIDX	((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0)
-#define MASK_XTHEADMAC		(1 << 6)
+#define MASK_XTHEADFMV		(1 << 6)
+#define TARGET_XTHEADFMV	((riscv_xthead_subext & MASK_XTHEADFMV) != 0)
+#define MASK_XTHEADINT		(1 << 7)
+#define TARGET_XTHEADINT	((riscv_xthead_subext & MASK_XTHEADINT) != 0)
+#define MASK_XTHEADMAC		(1 << 8)
 #define TARGET_XTHEADMAC	((riscv_xthead_subext & MASK_XTHEADMAC) != 0)
-#define MASK_XTHEADMEMIDX	(1 << 7)
+#define MASK_XTHEADMEMIDX	(1 << 9)
 #define TARGET_XTHEADMEMIDX	((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0)
-#define MASK_XTHEADSYNC		(1 << 8)
+#define MASK_XTHEADSYNC		(1 << 10)
 #define TARGET_XTHEADSYNC	((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
 
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv.c b/gcc/testsuite/gcc.target/riscv/xtheadfmv.c
new file mode 100644
index 00000000000..e97e8f461f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadfmv" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadfmv" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadfmv
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
+
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadint.c b/gcc/testsuite/gcc.target/riscv/xtheadint.c
new file mode 100644
index 00000000000..ee6989a380e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadint.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadint" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadint" { target { rv64 } } } */
+
+#ifndef __riscv_xtheadint
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
+
-- 
2.38.1


  parent reply	other threads:[~2022-11-13 21:46 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-13 21:46 [PATCH 0/7] Add XThead* support Christoph Muellner
2022-11-13 21:46 ` [PATCH 1/7] riscv: Add basic XThead* vendor extension support Christoph Muellner
2022-11-13 21:46 ` [PATCH 2/7] riscv: riscv-cores.def: Add T-Head XuanTie C906 Christoph Muellner
2022-11-18  4:50   ` cooper.qu
2022-11-18  4:58     ` Palmer Dabbelt
2022-11-13 21:46 ` [PATCH 3/7] riscv: thead: Add support for XTheadBa and XTheadBs ISA extensions Christoph Muellner
2022-11-13 21:46 ` [PATCH 4/7] riscv: thead: Add support for XTheadCondMov " Christoph Muellner
2022-11-13 21:46 ` [PATCH 5/7] riscv: thead: Add support for XTheadBb ISA extension Christoph Muellner
2022-11-18  4:21   ` cooper.qu
2022-11-13 21:46 ` [PATCH 6/7] riscv: thead: Add support for XTheadMac " Christoph Muellner
2022-11-13 21:46 ` Christoph Muellner [this message]
2022-11-18  4:43   ` [PATCH 7/7] riscv: Add basic extension support for XTheadFmv and XTheadInt cooper.qu
2023-11-02  7:26   ` [RE] [7/7] " Jin Ma
2023-11-02  7:42     ` Christoph Müllner
2023-11-07  3:04   ` [PATCH] riscv: thead: Add support for the XTheadInt ISA extension Jin Ma
2023-11-10 15:05     ` Christoph Müllner
2023-11-17  7:33     ` [PATCH v2] RISC-V: T-HEAD: " Jin Ma
2024-01-09  9:35       ` Jin Ma
2024-01-09 17:59       ` [PATCH " Jeff Law
2024-01-10 17:56         ` Christoph Müllner

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