Re: [PATCH v2] RISC-V: T-HEAD: Add support for the XTheadInt ISA extension

["Christoph Müllner" <christoph.muellner@vrull.eu>]

On Tue, Jan 9, 2024 at 6:59 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
> On 11/17/23 00:33, Jin Ma wrote:
> > The XTheadInt ISA extension provides acceleration interruption
> > instructions as defined in T-Head-specific:
> > * th.ipush
> > * th.ipop
> >
> > Ref:
> > https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
> >
> > gcc/ChangeLog:
> >
> >       * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
> >       (th_int_get_save_adjustment): Likewise.
> >       (th_int_adjust_cfi_prologue): Likewise.
> >       * config/riscv/riscv.cc (TH_INT_INTERRUPT): New macro.
> >       (riscv_expand_prologue): Add the processing of XTheadInt.
> >       (riscv_expand_epilogue): Likewise.
> >       * config/riscv/riscv.md: New unspec.
> >       * config/riscv/thead.cc (BITSET_P): New macro.
> >       * config/riscv/thead.md (th_int_push): New pattern.
> >       (th_int_pop): New pattern.
> >
> > gcc/testsuite/ChangeLog:
> >
> >       * gcc.target/riscv/xtheadint-push-pop.c: New test.
> Thanks for the ping earlier today.  I've looked at this patch repeatedly
> over the last few weeks, but never enough to give it a full review.
>
>
> > diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> > index 2babfafb23c..4d6e16c0edc 100644
> > --- a/gcc/config/riscv/thead.md
> > +++ b/gcc/config/riscv/thead.md
>
> > +(define_insn "th_int_pop"
> > +  [(unspec_volatile [(const_int 0)] UNSPECV_XTHEADINT_POP)
> > +   (clobber (reg:SI RETURN_ADDR_REGNUM))
> > +   (clobber (reg:SI T0_REGNUM))
> > +   (clobber (reg:SI T1_REGNUM))
> > +   (clobber (reg:SI T2_REGNUM))
> > +   (clobber (reg:SI A0_REGNUM))
> > +   (clobber (reg:SI A1_REGNUM))
> > +   (clobber (reg:SI A2_REGNUM))
> > +   (clobber (reg:SI A3_REGNUM))
> > +   (clobber (reg:SI A4_REGNUM))
> > +   (clobber (reg:SI A5_REGNUM))
> > +   (clobber (reg:SI A6_REGNUM))
> > +   (clobber (reg:SI A7_REGNUM))
> > +   (clobber (reg:SI T3_REGNUM))
> > +   (clobber (reg:SI T4_REGNUM))
> > +   (clobber (reg:SI T5_REGNUM))
> > +   (clobber (reg:SI T6_REGNUM))
> > +   (return)]
> > +  "TARGET_XTHEADINT && !TARGET_64BIT"
> > +  "th.ipop"
> > +  [(set_attr "type"  "ret")
> > +   (set_attr "mode"  "SI")])
> I probably would have gone with a load type since its the loads that are
> most likely to interact existing code in the pipeline.  But I doubt it
> really matters in practice.
>
>
> OK for the trunk.  Thanks for your patience.

I've retested this locally (no regressions), completed the ChangeLog
in the commit message and committed.

Thanks,
Christoph