From: Yixuan Chen <chenyixuan@iscas.ac.cn>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, andrew@sifive.com, oriachiuan@gmail.com,
Yixuan Chen <chenyixuan@iscas.ac.cn>
Subject: [PATCH] Ver.2: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv.
Date: Thu, 17 Nov 2022 17:53:55 +0800 [thread overview]
Message-ID: <20221117095355.1928564-1-chenyixuan@iscas.ac.cn> (raw)
2022-11-17 Yixuan Chen <chenyixuan@iscas.ac.cn>
* gcc/testsuite/gcc.dg/pr25521.c: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv.
---
gcc/testsuite/gcc.dg/pr25521.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/pr25521.c b/gcc/testsuite/gcc.dg/pr25521.c
index 74fe2ae6626..628ddf1a761 100644
--- a/gcc/testsuite/gcc.dg/pr25521.c
+++ b/gcc/testsuite/gcc.dg/pr25521.c
@@ -2,7 +2,8 @@
sections.
{ dg-require-effective-target elf }
- { dg-do compile } */
+ { dg-do compile }
+ { dg-options "-msmall-data-limit=0" { target { riscv*-*-* } } } */
const volatile int foo = 30;
--
2.37.2
next reply other threads:[~2022-11-17 9:54 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-17 9:53 Yixuan Chen [this message]
2022-11-17 21:50 ` Jeff Law
2022-11-17 23:59 ` Palmer Dabbelt
2022-11-18 3:30 ` Oria Chiuan
2022-11-18 5:02 ` Palmer Dabbelt
2022-11-18 5:21 ` Oria Chiuan
2022-11-18 5:52 ` 陈逸轩
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