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From: Fei Gao <gaofei@eswincomputing.com>
To: gcc-patches@gcc.gnu.org
Cc: jeffreyalaw@gmail.com, kito.cheng@gmail.com, palmer@dabbelt.com,
	Fei Gao <gaofei@eswincomputing.com>
Subject: [PATCH 1/3] RISC-V: add a new parameter in riscv_first_stack_step.
Date: Thu,  1 Dec 2022 10:03:30 +0000	[thread overview]
Message-ID: <20221201100332.22226-2-gaofei@eswincomputing.com> (raw)
In-Reply-To: <20221201100332.22226-1-gaofei@eswincomputing.com>

frame->total_size to remaining_size conversion is done as an independent patch without
functionality change as per review comment.

gcc/ChangeLog:

        * config/riscv/riscv.cc (riscv_first_stack_step): add a new function parameter remaining_size.
        (riscv_compute_frame_info): adapt new riscv_first_stack_step interface.
        (riscv_expand_prologue): likewise.
        (riscv_expand_epilogue): likewise.
---
 gcc/config/riscv/riscv.cc | 48 +++++++++++++++++++--------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 05bdba5ab4d..f0bbcd6d6be 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4634,7 +4634,7 @@ riscv_save_libcall_count (unsigned mask)
    They decrease stack_pointer_rtx but leave frame_pointer_rtx and
    hard_frame_pointer_rtx unchanged.  */
 
-static HOST_WIDE_INT riscv_first_stack_step (struct riscv_frame_info *frame);
+static HOST_WIDE_INT riscv_first_stack_step (struct riscv_frame_info *frame, poly_int64 remaining_size);
 
 /* Handle stack align for poly_int.  */
 static poly_int64
@@ -4663,7 +4663,7 @@ riscv_compute_frame_info (void)
      save/restore t0.  We check for this before clearing the frame struct.  */
   if (cfun->machine->interrupt_handler_p)
     {
-      HOST_WIDE_INT step1 = riscv_first_stack_step (frame);
+      HOST_WIDE_INT step1 = riscv_first_stack_step (frame, frame->total_size);
       if (! POLY_SMALL_OPERAND_P ((frame->total_size - step1)))
 	interrupt_save_prologue_temp = true;
     }
@@ -4913,45 +4913,45 @@ riscv_restore_reg (rtx reg, rtx mem)
    without adding extra instructions.  */
 
 static HOST_WIDE_INT
-riscv_first_stack_step (struct riscv_frame_info *frame)
+riscv_first_stack_step (struct riscv_frame_info *frame, poly_int64 remaining_size)
 {
-  HOST_WIDE_INT frame_total_constant_size;
-  if (!frame->total_size.is_constant ())
-    frame_total_constant_size
-      = riscv_stack_align (frame->total_size.coeffs[0])
-	- riscv_stack_align (frame->total_size.coeffs[1]);
+  HOST_WIDE_INT remaining_const_size;
+  if (!remaining_size.is_constant ())
+    remaining_const_size
+      = riscv_stack_align (remaining_size.coeffs[0])
+        - riscv_stack_align (remaining_size.coeffs[1]);
   else
-    frame_total_constant_size = frame->total_size.to_constant ();
+    remaining_const_size = remaining_size.to_constant ();
 
-  if (SMALL_OPERAND (frame_total_constant_size))
-    return frame_total_constant_size;
+  if (SMALL_OPERAND (remaining_const_size))
+    return remaining_const_size;
 
   HOST_WIDE_INT min_first_step =
-    RISCV_STACK_ALIGN ((frame->total_size - frame->frame_pointer_offset).to_constant());
+    riscv_stack_align ((remaining_size - frame->frame_pointer_offset).to_constant());
   HOST_WIDE_INT max_first_step = IMM_REACH / 2 - PREFERRED_STACK_BOUNDARY / 8;
-  HOST_WIDE_INT min_second_step = frame_total_constant_size - max_first_step;
+  HOST_WIDE_INT min_second_step = remaining_const_size - max_first_step;
   gcc_assert (min_first_step <= max_first_step);
 
   /* As an optimization, use the least-significant bits of the total frame
      size, so that the second adjustment step is just LUI + ADD.  */
   if (!SMALL_OPERAND (min_second_step)
-      && frame_total_constant_size % IMM_REACH < IMM_REACH / 2
-      && frame_total_constant_size % IMM_REACH >= min_first_step)
-    return frame_total_constant_size % IMM_REACH;
+      && remaining_const_size % IMM_REACH < IMM_REACH / 2
+      && remaining_const_size % IMM_REACH >= min_first_step)
+    return remaining_const_size % IMM_REACH;
 
   if (TARGET_RVC)
     {
       /* If we need two subtracts, and one is small enough to allow compressed
-	 loads and stores, then put that one first.  */
+         loads and stores, then put that one first.  */
       if (IN_RANGE (min_second_step, 0,
-		    (TARGET_64BIT ? SDSP_REACH : SWSP_REACH)))
-	return MAX (min_second_step, min_first_step);
+                    (TARGET_64BIT ? SDSP_REACH : SWSP_REACH)))
+       return MAX (min_second_step, min_first_step);
 
       /* If we need LUI + ADDI + ADD for the second adjustment step, then start
-	 with the minimum first step, so that we can get compressed loads and
-	 stores.  */
+         with the minimum first step, so that we can get compressed loads and
+         stores.  */
       else if (!SMALL_OPERAND (min_second_step))
-	return min_first_step;
+       return min_first_step;
     }
 
   return max_first_step;
@@ -5037,7 +5037,7 @@ riscv_expand_prologue (void)
   /* Save the registers.  */
   if ((frame->mask | frame->fmask) != 0)
     {
-      HOST_WIDE_INT step1 = riscv_first_stack_step (frame);
+      HOST_WIDE_INT step1 = riscv_first_stack_step (frame, frame->total_size);
       if (size.is_constant ())
 	step1 = MIN (size.to_constant(), step1);
 
@@ -5216,7 +5216,7 @@ riscv_expand_epilogue (int style)
      possible in the second step without going out of range.  */
   if ((frame->mask | frame->fmask) != 0)
     {
-      step2 = riscv_first_stack_step (frame);
+      step2 = riscv_first_stack_step (frame, frame->total_size);
       step1 -= step2;
     }
 
-- 
2.17.1


  reply	other threads:[~2022-12-01 10:03 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-01 10:03 [PATCH 0/3] RISC-V: optimize stack manipulation in save-restore Fei Gao
2022-12-01 10:03 ` Fei Gao [this message]
2023-02-03  8:52   ` [PING][PATCH 1/3] RISC-V: add a new parameter in riscv_first_stack_step Fei Gao
2023-04-16 16:40   ` [PATCH " Jeff Law
2023-04-17 18:09   ` Jeff Law
2022-12-01 10:03 ` [PATCH 2/3] RISC-V: optimize stack manipulation in save-restore Fei Gao
2023-02-03  8:52   ` [PING] " Fei Gao
2023-04-16 16:45   ` Jeff Law
2023-04-17 22:51   ` Jeff Law
2022-12-01 10:03 ` [PATCH 3/3] RISC-V: make the stack manipulation codes more readable Fei Gao
2023-02-03  8:52   ` [PING] " Fei Gao
2023-04-18  0:14   ` Jeff Law
2023-02-03  8:52 ` [PING] [PATCH 0/3] RISC-V: optimize stack manipulation in save-restore Fei Gao
2023-02-09  2:21   ` [PING 2] " Fei Gao
2023-02-16  7:17   ` Fei Gao
2023-02-16 14:39     ` Jeff Law

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