[PATCH] RISC-V: Add Full 'v' extension predicate to vsmul intrinsic

[PATCH] RISC-V: Add Full 'v' extension predicate to vsmul intrinsic

[juzhe.zhong]

From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

According to RVV ISA, vsmul are not supported for EEW=64 in Zve64*,
so add Full 'V' extension required into predicate of vsmul intrinsics.

gcc/ChangeLog:

        * config/riscv/riscv-vector-builtins-functions.def (vsmul): Change iterators.

---
 gcc/config/riscv/riscv-vector-builtins-functions.def | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index cea44c8fb20..66fa63530f3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -170,14 +170,14 @@ DEF_RVV_FUNCTION (vaadd, alu, full_preds, i_vvv_ops)
 DEF_RVV_FUNCTION (vasub, alu, full_preds, i_vvv_ops)
 DEF_RVV_FUNCTION (vaaddu, alu, full_preds, u_vvv_ops)
 DEF_RVV_FUNCTION (vasubu, alu, full_preds, u_vvv_ops)
-DEF_RVV_FUNCTION (vsmul, alu, full_preds, i_vvv_ops)
+DEF_RVV_FUNCTION (vsmul, alu, full_preds, full_v_i_vvv_ops)
 DEF_RVV_FUNCTION (vssra, alu, full_preds, i_shift_vvv_ops)
 DEF_RVV_FUNCTION (vssrl, alu, full_preds, u_shift_vvv_ops)
 DEF_RVV_FUNCTION (vaadd, alu, full_preds, i_vvx_ops)
 DEF_RVV_FUNCTION (vasub, alu, full_preds, i_vvx_ops)
 DEF_RVV_FUNCTION (vaaddu, alu, full_preds, u_vvx_ops)
 DEF_RVV_FUNCTION (vasubu, alu, full_preds, u_vvx_ops)
-DEF_RVV_FUNCTION (vsmul, alu, full_preds, i_vvx_ops)
+DEF_RVV_FUNCTION (vsmul, alu, full_preds, full_v_i_vvx_ops)
 DEF_RVV_FUNCTION (vssra, alu, full_preds, i_shift_vvx_ops)
 DEF_RVV_FUNCTION (vssrl, alu, full_preds, u_shift_vvx_ops)
 DEF_RVV_FUNCTION (vnclipu, narrow_alu, full_preds, u_narrow_shift_vwv_ops)
-- 
2.36.3