[PATCH] RISC-V: Add vwmacc vv C api tests

[PATCH] RISC-V: Add vwmacc vv C api tests

[juzhe.zhong]

From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vwmacc_vv-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vwmacc_vv-1.c   | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmacc_vv-2.c   | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmacc_vv-3.c   | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmacc_vv_mu-1.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmacc_vv_mu-2.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmacc_vv_mu-3.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmacc_vv_tu-1.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmacc_vv_tu-2.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmacc_vv_tu-3.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmacc_vv_tum-1.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmacc_vv_tum-2.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmacc_vv_tum-3.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmacc_vv_tumu-1.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmacc_vv_tumu-2.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmacc_vv_tumu-3.c         | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_m-1.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_m-2.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_m-3.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_mu-1.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_mu-2.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_mu-3.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tu-1.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tu-2.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tu-3.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tum-1.c        | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tum-2.c        | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tum-3.c        | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tumu-1.c       | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tumu-2.c       | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tumu-3.c       | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmaccu_vv-1.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmaccu_vv-2.c  | 111 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vwmaccu_vv-3.c  | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_m-1.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_m-2.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_m-3.c           | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_mu-1.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_mu-2.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_mu-3.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_tu-1.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_tu-2.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_tu-3.c          | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_tum-1.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_tum-2.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_tum-3.c         | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_tumu-1.c        | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_tumu-2.c        | 111 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_tumu-3.c        | 111 ++++++++++++++++++
 54 files changed, 5994 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-1.c
new file mode 100644
index 00000000000..803dfa9fbe8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8(vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-2.c
new file mode 100644
index 00000000000..88a0a12f7a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8(vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-3.c
new file mode 100644
index 00000000000..33f733cc0bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8(vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c
new file mode 100644
index 00000000000..0d6390ceedf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_m(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_m(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_m(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_m(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_m(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_m(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_m(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_m(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_m(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_m(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_m(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_m(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_m(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_m(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_m(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_m(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c
new file mode 100644
index 00000000000..df359bdb79b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_m(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_m(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_m(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_m(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_m(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_m(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_m(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_m(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_m(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_m(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_m(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_m(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_m(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_m(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_m(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_m(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c
new file mode 100644
index 00000000000..c1408b51458
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_m(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_m(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_m(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_m(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_m(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_m(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_m(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_m(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_m(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_m(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_m(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_m(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_m(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_m(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_m(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_m(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c
new file mode 100644
index 00000000000..5032a0849a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c
new file mode 100644
index 00000000000..731e2676bbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_mu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c
new file mode 100644
index 00000000000..c4643acee18
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_mu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c
new file mode 100644
index 00000000000..114758232ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_tu(vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c
new file mode 100644
index 00000000000..3d21a06ee32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_tu(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_tu(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_tu(vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c
new file mode 100644
index 00000000000..4c258c970f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_tu(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_tu(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_tu(vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c
new file mode 100644
index 00000000000..c65c026ba02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c
new file mode 100644
index 00000000000..513b6c33118
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_tum(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c
new file mode 100644
index 00000000000..a1ce9b2e351
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_tum(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c
new file mode 100644
index 00000000000..751da6ccd7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c
new file mode 100644
index 00000000000..e78de68fb93
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c
new file mode 100644
index 00000000000..51c6d321fc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf4_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16mf2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_vv_i16m1_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m1_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_vv_i16m2_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_vv_i16m4_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m4_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_vv_i16m8_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i16m8_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32mf2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_vv_i32m1_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m1_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_vv_i32m2_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_vv_i32m4_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m4_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_vv_i32m8_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i32m8_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_vv_i64m1_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m1_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_vv_i64m2_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_vv_i64m4_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m4_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_vv_i64m8_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_vv_i64m8_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c
new file mode 100644
index 00000000000..b69b9d5fd11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8(vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c
new file mode 100644
index 00000000000..65e728fe55c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8(vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c
new file mode 100644
index 00000000000..918c5fa857d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8(vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c
new file mode 100644
index 00000000000..56c482ee6db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_m(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_m(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_m(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_m(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_m(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_m(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_m(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_m(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_m(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_m(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_m(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_m(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_m(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_m(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_m(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_m(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c
new file mode 100644
index 00000000000..a8c4250211e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_m(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_m(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_m(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_m(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_m(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_m(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_m(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_m(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_m(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_m(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_m(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_m(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_m(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_m(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_m(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_m(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_m(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c
new file mode 100644
index 00000000000..a2284ffeccc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_m(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_m(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_m(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_m(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_m(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_m(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_m(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_m(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_m(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_m(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_m(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_m(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_m(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_m(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_m(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_m(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_m(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c
new file mode 100644
index 00000000000..a2e7cd7a58d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c
new file mode 100644
index 00000000000..fe32bfb6409
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_mu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c
new file mode 100644
index 00000000000..3e33291ec1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_mu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c
new file mode 100644
index 00000000000..a32ffc269fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_tu(vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c
new file mode 100644
index 00000000000..82c390ad470
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_tu(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_tu(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_tu(vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c
new file mode 100644
index 00000000000..5fe023663c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_tu(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_tu(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_tu(vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c
new file mode 100644
index 00000000000..a75b8e0d00f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c
new file mode 100644
index 00000000000..4c4cd28b1ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_tum(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c
new file mode 100644
index 00000000000..f2554817b8e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_tum(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c
new file mode 100644
index 00000000000..58f492be265
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c
new file mode 100644
index 00000000000..df7b038f8c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c
new file mode 100644
index 00000000000..31bba289459
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf4_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16mf2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_vv_i16m1_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m1_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_vv_i16m2_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_vv_i16m4_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m4_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_vv_i16m8_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i16m8_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32mf2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_vv_i32m1_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m1_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_vv_i32m2_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_vv_i32m4_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m4_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_vv_i32m8_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i32m8_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_vv_i64m1_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m1_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_vv_i64m2_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_vv_i64m4_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m4_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_vv_i64m8_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_vv_i64m8_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-1.c
new file mode 100644
index 00000000000..35662bc9ec0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2(vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1(vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2(vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4(vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8(vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2(vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1(vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2(vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4(vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8(vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1(vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2(vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4(vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8(vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-2.c
new file mode 100644
index 00000000000..5b00b6875bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4(vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2(vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1(vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2(vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4(vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8(vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2(vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1(vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2(vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4(vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8(vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1(vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2(vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4(vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8(vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-3.c
new file mode 100644
index 00000000000..c0f57af2419
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4(vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2(vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1(vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2(vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4(vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8(vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2(vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1(vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2(vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4(vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8(vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1(vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2(vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4(vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8(vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c
new file mode 100644
index 00000000000..596aa21d79e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_m(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_m(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_m(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_m(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_m(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_m(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_m(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_m(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_m(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_m(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_m(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_m(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_m(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_m(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c
new file mode 100644
index 00000000000..d855092f9e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_m(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_m(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_m(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_m(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_m(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_m(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_m(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_m(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_m(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_m(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_m(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_m(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_m(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_m(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_m(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_m(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_m(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_m(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_m(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_m(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_m(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_m(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_m(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c
new file mode 100644
index 00000000000..a942bc29ced
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_m(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_m(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_m(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_m(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_m(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_m(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_m(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_m(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_m(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_m(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_m(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_m(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_m(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_m(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_m(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_m(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_m(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_m(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_m(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_m(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_m(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_m(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_m(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c
new file mode 100644
index 00000000000..4626f95c1a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c
new file mode 100644
index 00000000000..6ee2a1f4a95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_mu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c
new file mode 100644
index 00000000000..2496bb70365
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_mu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c
new file mode 100644
index 00000000000..db9ab3581ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_tu(vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c
new file mode 100644
index 00000000000..6604dc654e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_tu(vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c
new file mode 100644
index 00000000000..6dcccbc16f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_tu(vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c
new file mode 100644
index 00000000000..1683f8b4ebc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c
new file mode 100644
index 00000000000..4d2fd2e1ea7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_tum(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c
new file mode 100644
index 00000000000..36972c53bb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_tum(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c
new file mode 100644
index 00000000000..4d74c751727
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c
new file mode 100644
index 00000000000..42a56c20537
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c
new file mode 100644
index 00000000000..88c48aea096
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf4_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16mf2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m1_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m4_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u16m8_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32mf2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m1_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m4_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u32m8_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m1_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m2_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m4_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_vv_u64m8_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
-- 
2.36.3

[PATCH] RISC-V: Add vwmacc vv C++ api tests

[juzhe.zhong]

From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vwmacc_vv-1.C: New test.
        * g++.target/riscv/rvv/base/vwmacc_vv-2.C: New test.
        * g++.target/riscv/rvv/base/vwmacc_vv-3.C: New test.
        * g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv-1.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv-2.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv-3.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv-1.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv-2.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv-3.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vwmacc_vv-1.C   | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwmacc_vv-2.C   | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwmacc_vv-3.C   | 216 ++++++++++++++++++
 .../riscv/rvv/base/vwmacc_vv_mu-1.C           | 111 +++++++++
 .../riscv/rvv/base/vwmacc_vv_mu-2.C           | 111 +++++++++
 .../riscv/rvv/base/vwmacc_vv_mu-3.C           | 111 +++++++++
 .../riscv/rvv/base/vwmacc_vv_tu-1.C           | 111 +++++++++
 .../riscv/rvv/base/vwmacc_vv_tu-2.C           | 111 +++++++++
 .../riscv/rvv/base/vwmacc_vv_tu-3.C           | 111 +++++++++
 .../riscv/rvv/base/vwmacc_vv_tum-1.C          | 111 +++++++++
 .../riscv/rvv/base/vwmacc_vv_tum-2.C          | 111 +++++++++
 .../riscv/rvv/base/vwmacc_vv_tum-3.C          | 111 +++++++++
 .../riscv/rvv/base/vwmacc_vv_tumu-1.C         | 111 +++++++++
 .../riscv/rvv/base/vwmacc_vv_tumu-2.C         | 111 +++++++++
 .../riscv/rvv/base/vwmacc_vv_tumu-3.C         | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwmaccsu_vv-1.C | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwmaccsu_vv-2.C | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwmaccsu_vv-3.C | 216 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccsu_vv_mu-1.C         | 111 +++++++++
 .../riscv/rvv/base/vwmaccsu_vv_mu-2.C         | 111 +++++++++
 .../riscv/rvv/base/vwmaccsu_vv_mu-3.C         | 111 +++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tu-1.C         | 111 +++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tu-2.C         | 111 +++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tu-3.C         | 111 +++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tum-1.C        | 111 +++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tum-2.C        | 111 +++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tum-3.C        | 111 +++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tumu-1.C       | 111 +++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tumu-2.C       | 111 +++++++++
 .../riscv/rvv/base/vwmaccsu_vv_tumu-3.C       | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwmaccu_vv-1.C  | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwmaccu_vv-2.C  | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwmaccu_vv-3.C  | 216 ++++++++++++++++++
 .../riscv/rvv/base/vwmaccu_vv_mu-1.C          | 111 +++++++++
 .../riscv/rvv/base/vwmaccu_vv_mu-2.C          | 111 +++++++++
 .../riscv/rvv/base/vwmaccu_vv_mu-3.C          | 111 +++++++++
 .../riscv/rvv/base/vwmaccu_vv_tu-1.C          | 111 +++++++++
 .../riscv/rvv/base/vwmaccu_vv_tu-2.C          | 111 +++++++++
 .../riscv/rvv/base/vwmaccu_vv_tu-3.C          | 111 +++++++++
 .../riscv/rvv/base/vwmaccu_vv_tum-1.C         | 111 +++++++++
 .../riscv/rvv/base/vwmaccu_vv_tum-2.C         | 111 +++++++++
 .../riscv/rvv/base/vwmaccu_vv_tum-3.C         | 111 +++++++++
 .../riscv/rvv/base/vwmaccu_vv_tumu-1.C        | 111 +++++++++
 .../riscv/rvv/base/vwmaccu_vv_tumu-2.C        | 111 +++++++++
 .../riscv/rvv/base/vwmaccu_vv_tumu-3.C        | 111 +++++++++
 45 files changed, 5940 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-1.C
new file mode 100644
index 00000000000..481fe63f074
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-1.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vwmacc(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-2.C
new file mode 100644
index 00000000000..08c16d3955d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-2.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vwmacc(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-3.C
new file mode 100644
index 00000000000..870b62cf392
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-3.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vwmacc(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C
new file mode 100644
index 00000000000..4d8564beaeb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C
new file mode 100644
index 00000000000..23ec15b7568
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C
new file mode 100644
index 00000000000..3e16e035563
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C
new file mode 100644
index 00000000000..397d3f01198
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C
new file mode 100644
index 00000000000..08276ad193c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C
new file mode 100644
index 00000000000..f7df4b17e66
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tu(vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C
new file mode 100644
index 00000000000..afed070daf9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C
new file mode 100644
index 00000000000..657b4d9cf23
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C
new file mode 100644
index 00000000000..9d28777964d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C
new file mode 100644
index 00000000000..e45bcf5695a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C
new file mode 100644
index 00000000000..d5a01238cc6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C
new file mode 100644
index 00000000000..773f7095c9c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmacc_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmacc_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmacc_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmacc_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmacc_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmacc_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmacc_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmacc_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmacc_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmacc_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmacc_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmacc_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmacc_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-1.C
new file mode 100644
index 00000000000..28f5a3831c9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-1.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vwmaccsu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-2.C
new file mode 100644
index 00000000000..4ccbc3a703a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-2.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vwmaccsu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-3.C
new file mode 100644
index 00000000000..b60666b0319
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-3.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vwmaccsu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C
new file mode 100644
index 00000000000..65815081b04
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C
new file mode 100644
index 00000000000..1704a0c9611
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C
new file mode 100644
index 00000000000..4107fd73e8d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C
new file mode 100644
index 00000000000..5570d279db7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C
new file mode 100644
index 00000000000..5034aa4a753
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C
new file mode 100644
index 00000000000..6e0b65b0c22
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tu(vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C
new file mode 100644
index 00000000000..5c2a3a5bca6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C
new file mode 100644
index 00000000000..6aaf403fca8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C
new file mode 100644
index 00000000000..fd6fc26515b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C
new file mode 100644
index 00000000000..1aa27dbe36d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C
new file mode 100644
index 00000000000..94d4b3d8776
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C
new file mode 100644
index 00000000000..2f694edeb42
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vwmaccsu_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-1.C
new file mode 100644
index 00000000000..b2c49896513
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-1.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vwmaccu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-2.C
new file mode 100644
index 00000000000..c9f3e7ed08b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-2.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vwmaccu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-3.C
new file mode 100644
index 00000000000..210311dca50
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-3.C
@@ -0,0 +1,216 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(vd,vs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vwmaccu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C
new file mode 100644
index 00000000000..a77d935e1fc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C
new file mode 100644
index 00000000000..b2c4a795688
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C
new file mode 100644
index 00000000000..47bf138422f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C
new file mode 100644
index 00000000000..9470b52fd8a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C
new file mode 100644
index 00000000000..dacab0af322
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C
new file mode 100644
index 00000000000..d31989fe726
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tu(vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C
new file mode 100644
index 00000000000..515c6d8e31f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C
new file mode 100644
index 00000000000..1aa0b331367
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C
new file mode 100644
index 00000000000..6e2bbdab7df
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C
new file mode 100644
index 00000000000..39aff25d25d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C
new file mode 100644
index 00000000000..2f4176a78f9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C
new file mode 100644
index 00000000000..0fe3dffe1b3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vwmaccu_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
-- 
2.36.3