* [PATCH] RISC-V: Refine reduction RA constraint according to RVV ISA
@ 2023-03-13 9:05 juzhe.zhong
2023-03-14 18:05 ` Jeff Law
2023-04-21 20:32 ` Jeff Law
0 siblings, 2 replies; 4+ messages in thread
From: juzhe.zhong @ 2023-03-13 9:05 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
According to RVV ISA:
14. Vector Reduction Operations
"The destination vector register can overlap the source operands, including the mask register."
gcc/ChangeLog:
* config/riscv/vector.md: Refine RA constraint.
---
gcc/config/riscv/vector.md | 96 +++++++++++++++++++-------------------
1 file changed, 48 insertions(+), 48 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 4ea74372de5..75336b1a515 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6259,44 +6259,44 @@
;; For example, The LMUL = 1 corresponding mode of VNx16QImode is VNx4QImode
;; for -march=rv*zve32* wheras VNx8QImode for -march=rv*zve64*
(define_insn "@pred_reduc_<reduc><mode><vlmul1>"
- [(set (match_operand:<VLMUL1> 0 "register_operand" "=vd, vd, vr, vr")
+ [(set (match_operand:<VLMUL1> 0 "register_operand" "=vr, vr")
(unspec:<VLMUL1>
[(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 6 "const_int_operand" " i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_reduc:VI
(vec_duplicate:VI
(vec_select:<VEL>
- (match_operand:<VLMUL1> 4 "register_operand" " vr, vr, vr, vr")
+ (match_operand:<VLMUL1> 4 "register_operand" " vr, vr")
(parallel [(const_int 0)])))
- (match_operand:VI 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
+ (match_operand:VI 3 "register_operand" " vr, vr"))
+ (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR && TARGET_MIN_VLEN > 32"
"vred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vired")
(set_attr "mode" "<MODE>")])
(define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
- [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand" "=vd, vd, vr, vr")
+ [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand" "=vr, vr")
(unspec:<VLMUL1_ZVE32>
[(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 6 "const_int_operand" " i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_reduc:VI_ZVE32
(vec_duplicate:VI_ZVE32
(vec_select:<VEL>
- (match_operand:<VLMUL1_ZVE32> 4 "register_operand" " vr, vr, vr, vr")
+ (match_operand:<VLMUL1_ZVE32> 4 "register_operand" " vr, vr")
(parallel [(const_int 0)])))
- (match_operand:VI_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
+ (match_operand:VI_ZVE32 3 "register_operand" " vr, vr"))
+ (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR && TARGET_MIN_VLEN == 32"
"vred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vired")
@@ -6339,90 +6339,90 @@
(set_attr "mode" "<MODE>")])
(define_insn "@pred_reduc_<reduc><mode><vlmul1>"
- [(set (match_operand:<VLMUL1> 0 "register_operand" "=vd, vd, vr, vr")
+ [(set (match_operand:<VLMUL1> 0 "register_operand" "=vr, vr")
(unspec:<VLMUL1>
[(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 6 "const_int_operand" " i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_freduc:VF
(vec_duplicate:VF
(vec_select:<VEL>
- (match_operand:<VLMUL1> 4 "register_operand" " vr, vr, vr, vr")
+ (match_operand:<VLMUL1> 4 "register_operand" " vr, vr")
(parallel [(const_int 0)])))
- (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
+ (match_operand:VF 3 "register_operand" " vr, vr"))
+ (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR && TARGET_MIN_VLEN > 32"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
(define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
- [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand" "=vd, vd, vr, vr")
+ [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand" "=vr, vr")
(unspec:<VLMUL1_ZVE32>
[(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 6 "const_int_operand" " i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_freduc:VF_ZVE32
(vec_duplicate:VF_ZVE32
(vec_select:<VEL>
- (match_operand:<VLMUL1_ZVE32> 4 "register_operand" " vr, vr, vr, vr")
+ (match_operand:<VLMUL1_ZVE32> 4 "register_operand" " vr, vr")
(parallel [(const_int 0)])))
- (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))]
+ (match_operand:VF_ZVE32 3 "register_operand" " vr, vr"))
+ (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR && TARGET_MIN_VLEN == 32"
"vfred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfredu")
(set_attr "mode" "<MODE>")])
(define_insn "@pred_reduc_plus<order><mode><vlmul1>"
- [(set (match_operand:<VLMUL1> 0 "register_operand" "=vd, vd, vr, vr")
+ [(set (match_operand:<VLMUL1> 0 "register_operand" "=vr, vr")
(unspec:<VLMUL1>
[(unspec:<VLMUL1>
[(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 6 "const_int_operand" " i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus:VF
(vec_duplicate:VF
(vec_select:<VEL>
- (match_operand:<VLMUL1> 4 "register_operand" " vr, vr, vr, vr")
+ (match_operand:<VLMUL1> 4 "register_operand" " vr, vr")
(parallel [(const_int 0)])))
- (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))]
+ (match_operand:VF 3 "register_operand" " vr, vr"))
+ (match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
"TARGET_VECTOR && TARGET_MIN_VLEN > 32"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<MODE>")])
(define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
- [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand" "=vd, vd, vr, vr")
+ [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand" "=vr, vr")
(unspec:<VLMUL1_ZVE32>
[(unspec:<VLMUL1_ZVE32>
[(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
- (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 6 "const_int_operand" " i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK")
+ (match_operand 6 "const_int_operand" " i, i")
+ (match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus:VF_ZVE32
(vec_duplicate:VF_ZVE32
(vec_select:<VEL>
- (match_operand:<VLMUL1_ZVE32> 4 "register_operand" " vr, vr, vr, vr")
+ (match_operand:<VLMUL1_ZVE32> 4 "register_operand" " vr, vr")
(parallel [(const_int 0)])))
- (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))]
+ (match_operand:VF_ZVE32 3 "register_operand" " vr, vr"))
+ (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))]
"TARGET_VECTOR && TARGET_MIN_VLEN == 32"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
--
2.36.3
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] RISC-V: Refine reduction RA constraint according to RVV ISA
2023-03-13 9:05 [PATCH] RISC-V: Refine reduction RA constraint according to RVV ISA juzhe.zhong
@ 2023-03-14 18:05 ` Jeff Law
2023-03-14 23:10 ` juzhe.zhong
2023-04-21 20:32 ` Jeff Law
1 sibling, 1 reply; 4+ messages in thread
From: Jeff Law @ 2023-03-14 18:05 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: kito.cheng
On 3/13/23 03:05, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> According to RVV ISA:
> 14. Vector Reduction Operations
>
> "The destination vector register can overlap the source operands, including the mask register."
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md: Refine RA constraint.
This feels like it ought to wait for gcc-14 as well.
One question though, why even bother with the matching constraint at all
in these patterns? ISTM it doesn't really accomplish anything.
Removing it allows a single alternative to handle all the possibilities.
Jeff
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Re: [PATCH] RISC-V: Refine reduction RA constraint according to RVV ISA
2023-03-14 18:05 ` Jeff Law
@ 2023-03-14 23:10 ` juzhe.zhong
0 siblings, 0 replies; 4+ messages in thread
From: juzhe.zhong @ 2023-03-14 23:10 UTC (permalink / raw)
To: Jeff Law, gcc-patches; +Cc: kito.cheng
[-- Attachment #1: Type: text/plain, Size: 1308 bytes --]
Since according to RVV ISA, "The destination vector register can overlap the source operands, including the mask register."
That means we can have vredsum.vs v0,v8,v9,v0.t. This patch is to refine the constraint to allow this happen that the current RA constraint doesn't allow.
Since you can see "vd" to match "vm", vd doesn't include mask register (v0). This trivial optimization can allow our RA have 1 more register to allocate.
It's overall beneficial to the RA.
juzhe.zhong@rivai.ai
From: Jeff Law
Date: 2023-03-15 02:05
To: juzhe.zhong; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH] RISC-V: Refine reduction RA constraint according to RVV ISA
On 3/13/23 03:05, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> According to RVV ISA:
> 14. Vector Reduction Operations
>
> "The destination vector register can overlap the source operands, including the mask register."
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md: Refine RA constraint.
This feels like it ought to wait for gcc-14 as well.
One question though, why even bother with the matching constraint at all
in these patterns? ISTM it doesn't really accomplish anything.
Removing it allows a single alternative to handle all the possibilities.
Jeff
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] RISC-V: Refine reduction RA constraint according to RVV ISA
2023-03-13 9:05 [PATCH] RISC-V: Refine reduction RA constraint according to RVV ISA juzhe.zhong
2023-03-14 18:05 ` Jeff Law
@ 2023-04-21 20:32 ` Jeff Law
1 sibling, 0 replies; 4+ messages in thread
From: Jeff Law @ 2023-04-21 20:32 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: kito.cheng
On 3/13/23 03:05, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> According to RVV ISA:
> 14. Vector Reduction Operations
>
> "The destination vector register can overlap the source operands, including the mask register."
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md: Refine RA constraint.
OK. Go ahead and install this on the trunk.
jeff
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-03-13 9:05 [PATCH] RISC-V: Refine reduction RA constraint according to RVV ISA juzhe.zhong
2023-03-14 18:05 ` Jeff Law
2023-03-14 23:10 ` juzhe.zhong
2023-04-21 20:32 ` Jeff Law
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