From: Li Xu <xuli1@eswincomputing.com>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com,
Li Xu <xuli1@eswincomputing.com>
Subject: [PATCH] RISC-V: Fix typo
Date: Mon, 3 Apr 2023 09:19:39 +0800 [thread overview]
Message-ID: <20230403011939.10677-1-xuli1@eswincomputing.com> (raw)
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.def (vuint32m8_t): Fix typo
(vfloat32m8_t): Likewise
---
gcc/config/riscv/riscv-vector-builtins.def | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
index d4a74befd8a..2d527f76f0a 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -234,7 +234,7 @@ DEF_RVV_TYPE (vuint32m8_t, 16, __rvv_uint32m8_t, uint32, VNx16SI, VNx8SI,
_u32m8, _u32, _e32m8)
/* SEW = 64:
- Disable when TARGET_MIN_VLEN > 32. */
+ Enable when TARGET_MIN_VLEN > 32. */
DEF_RVV_TYPE (vint64m1_t, 15, __rvv_int64m1_t, int64, VNx1DI, VOID, _i64m1,
_i64, _e64m1)
DEF_RVV_TYPE (vuint64m1_t, 16, __rvv_uint64m1_t, uint64, VNx1DI, VOID, _u64m1,
@@ -278,7 +278,7 @@ DEF_RVV_TYPE (vfloat32m8_t, 17, __rvv_float32m8_t, float, VNx16SF, VNx8SF,
_f32m8, _f32, _e32m8)
/* SEW = 64:
- Disable when TARGET_VECTOR_FP64. */
+ Enable when TARGET_VECTOR_FP64. */
DEF_RVV_TYPE (vfloat64m1_t, 17, __rvv_float64m1_t, double, VNx1DF, VOID, _f64m1,
_f64, _e64m1)
DEF_RVV_TYPE (vfloat64m2_t, 17, __rvv_float64m2_t, double, VNx2DF, VOID, _f64m2,
--
2.17.1
next reply other threads:[~2023-04-03 1:19 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-03 1:19 Li Xu [this message]
2023-04-03 4:00 ` Jeff Law
-- strict thread matches above, loose matches on Subject: below --
2023-04-04 7:49 Li Xu
2023-04-05 1:14 ` Jeff Law
2022-10-24 14:24 juzhe.zhong
2022-10-26 8:34 ` Kito Cheng
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