From: Li Xu <xuli1@eswincomputing.com>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com,
Li Xu <xuli1@eswincomputing.com>
Subject: [PATCH] RISC-V: Fix typo
Date: Tue, 4 Apr 2023 15:49:03 +0800 [thread overview]
Message-ID: <20230404074903.4275-1-xuli1@eswincomputing.com> (raw)
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.def: Fix typo.
* config/riscv/riscv.cc (riscv_dwarf_poly_indeterminate_value): Ditto.
* config/riscv/vector-iterators.md: Ditto.
---
gcc/config/riscv/riscv-vector-builtins.def | 3 +--
gcc/config/riscv/riscv.cc | 4 ++--
gcc/config/riscv/vector-iterators.md | 4 ++--
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
index 2d527f76f0a..563ad355342 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -65,8 +65,7 @@ along with GCC; see the file COPYING3. If not see
#define DEF_RVV_BASE_TYPE(NAME, TYPE)
#endif
-/* Use "DEF_RVV_TYPE_INDEX" macro to define RVV function types.
- The 'NAME' will be concatenated into intrinsic function name. */
+/* Use "DEF_RVV_TYPE_INDEX" macro to define RVV function types. */
#ifndef DEF_RVV_TYPE_INDEX
#define DEF_RVV_TYPE_INDEX(VECTOR, MASK, SIGNED, UNSIGNED, EEW8_INDEX, EEW16_INDEX, \
EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC, \
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 76eee4a55e9..5f542932d13 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7048,8 +7048,8 @@ riscv_dwarf_poly_indeterminate_value (unsigned int i, unsigned int *factor,
int *offset)
{
/* Polynomial invariant 1 == (VLENB / riscv_bytes_per_vector_chunk) - 1.
- 1. TARGET_MIN_VLEN == 32, olynomial invariant 1 == (VLENB / 4) - 1.
- 2. TARGET_MIN_VLEN > 32, olynomial invariant 1 == (VLENB / 8) - 1.
+ 1. TARGET_MIN_VLEN == 32, polynomial invariant 1 == (VLENB / 4) - 1.
+ 2. TARGET_MIN_VLEN > 32, polynomial invariant 1 == (VLENB / 8) - 1.
*/
gcc_assert (i == 1);
*factor = riscv_bytes_per_vector_chunk;
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 34e486e48ca..194e9b8f57f 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -727,7 +727,7 @@
(VNx1QI "vnx4hi") (VNx2QI "vnx4hi") (VNx4QI "vnx4hi")
(VNx8QI "vnx4hi") (VNx16QI "vnx4hi") (VNx32QI "vnx4hi") (VNx64QI "vnx4hi")
(VNx1HI "vnx2si") (VNx2HI "vnx2si") (VNx4HI "vnx2si")
- (VNx8HI "vnx2si") (VNx16HI "vnx2si") (VNx32HI "vnx2SI")
+ (VNx8HI "vnx2si") (VNx16HI "vnx2si") (VNx32HI "vnx2si")
(VNx1SI "vnx2di") (VNx2SI "vnx2di") (VNx4SI "vnx2di")
(VNx8SI "vnx2di") (VNx16SI "vnx2di")
(VNx1SF "vnx1df") (VNx2SF "vnx1df")
@@ -738,7 +738,7 @@
(VNx1QI "vnx2hi") (VNx2QI "vnx2hi") (VNx4QI "vnx2hi")
(VNx8QI "vnx2hi") (VNx16QI "vnx2hi") (VNx32QI "vnx2hi")
(VNx1HI "vnx1si") (VNx2HI "vnx1si") (VNx4HI "vnx1si")
- (VNx8HI "vnx1si") (VNx16HI "vnx1SI")
+ (VNx8HI "vnx1si") (VNx16HI "vnx1si")
])
(define_mode_attr VDEMOTE [
--
2.17.1
next reply other threads:[~2023-04-04 7:49 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-04 7:49 Li Xu [this message]
2023-04-05 1:14 ` Jeff Law
-- strict thread matches above, loose matches on Subject: below --
2023-04-03 1:19 Li Xu
2023-04-03 4:00 ` Jeff Law
2022-10-24 14:24 juzhe.zhong
2022-10-26 8:34 ` Kito Cheng
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