From: Michael Collison <collison@rivosinc.com>
To: gcc-patches@gcc.gnu.org
Subject: [PATCH v5 10/10] RISC-V: autovec: This patch supports 8 bit auto-vectorization in riscv.
Date: Wed, 26 Apr 2023 17:45:14 -0400 [thread overview]
Message-ID: <20230426214514.3355280-11-collison@rivosinc.com> (raw)
In-Reply-To: <20230426214514.3355280-1-collison@rivosinc.com>
From: Kevin Lee <kevinl@rivosinc.com>
2023-04-14 Kevin Lee <kevinl@rivosinc.com>
gcc/testsuite/ChangeLog:
* config/riscv/riscv.cc (riscv_autovectorize_vector_modes): Add
new vector mode
* gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit
type
* gcc.target/riscv/rvv/autovec/loop-add.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-and-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-and.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-div-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-div.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-max-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-max.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-min-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-min.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-mod-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-mod.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-mul-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-mul.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-or-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-or.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-sub.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-xor-rv32.c: Ditto
* gcc.target/riscv/rvv/autovec/loop-xor.c: Ditto
---
gcc/config/riscv/riscv.cc | 1 +
.../gcc.target/riscv/rvv/autovec/loop-add-rv32.c | 5 +++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c | 5 +++--
.../gcc.target/riscv/rvv/autovec/loop-and-rv32.c | 5 +++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c | 5 +++--
.../gcc.target/riscv/rvv/autovec/loop-div-rv32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c | 8 +++++---
.../gcc.target/riscv/rvv/autovec/loop-max-rv32.c | 7 ++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c | 7 ++++---
.../gcc.target/riscv/rvv/autovec/loop-min-rv32.c | 7 ++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c | 7 ++++---
.../gcc.target/riscv/rvv/autovec/loop-mod-rv32.c | 8 +++++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c | 8 +++++---
.../gcc.target/riscv/rvv/autovec/loop-mul-rv32.c | 5 +++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c | 5 +++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c | 5 +++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c | 5 +++--
.../gcc.target/riscv/rvv/autovec/loop-sub-rv32.c | 5 +++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c | 5 +++--
.../gcc.target/riscv/rvv/autovec/loop-xor-rv32.c | 5 +++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c | 5 +++--
21 files changed, 73 insertions(+), 48 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 77209b161f6..f293414acd1 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7143,6 +7143,7 @@ riscv_autovectorize_vector_modes (vector_modes *modes, bool)
modes->safe_push (VNx8QImode);
modes->safe_push (VNx4QImode);
modes->safe_push (VNx2QImode);
+ modes->safe_push (VNx1QImode);
}
return 0;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
index bdc3b6892e9..76f5a3a3ff5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] + b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
index d7f992c7d27..3d1e10bf4e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
@@ -10,8 +10,9 @@
dst[i] = a[i] + b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
index eb1ac5b44fd..a4c7abfb0ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] & b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
index ff0cc2a5df7..a795e0968a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
@@ -10,8 +10,9 @@
dst[i] = a[i] & b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
index 21960f265b7..c734bb9c5f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] / b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,6 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
index bd675b4f6f0..9f57cd91054 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
@@ -10,8 +10,9 @@
dst[i] = a[i] / b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,6 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
index 751ee9ecaa3..bd825c3dfaa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] >= b[i] ? a[i] : b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,5 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
index f4dbf3f04fc..729fbe0bc76 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
@@ -10,8 +10,9 @@
dst[i] = a[i] >= b[i] ? a[i] : b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,5 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
index e51cf590577..808c2879d86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] <= b[i] ? a[i] : b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,5 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
index 304f939f6f9..c81ba64223f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
@@ -10,8 +10,9 @@
dst[i] = a[i] <= b[i] ? a[i] : b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,5 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
index 7c497f6e4cc..9ce4f82b3a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] % b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,6 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
index 7508f4a50d1..46fbff22266 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
@@ -10,8 +10,9 @@
dst[i] = a[i] % b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,5 +22,6 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */
+/* int8_t and int16_t not autovec currently */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
index fd6dcbf9c53..336af62359e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] * b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
index 9fce40890ef..12a17d0da00 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
@@ -10,8 +10,9 @@
dst[i] = a[i] * b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
index 305d106abd9..b272d893114 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] | b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
index 501017bc790..52243be3712 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
@@ -10,8 +10,9 @@
dst[i] = a[i] | b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
index 7d0a40ec539..6fdce0f7881 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] - b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
index c8900884f83..73369745afc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
@@ -10,8 +10,9 @@
dst[i] = a[i] - b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
index 6a9ffdb11d5..bd43e60cceb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
@@ -10,8 +10,9 @@
dst[i] = a[i] ^ b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
index c9d7d7f8a75..cb3adde80c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
@@ -10,8 +10,9 @@
dst[i] = a[i] ^ b[i]; \
}
-/* *int8_t not autovec currently. */
#define TEST_ALL() \
+ TEST_TYPE(int8_t) \
+ TEST_TYPE(uint8_t) \
TEST_TYPE(int16_t) \
TEST_TYPE(uint16_t) \
TEST_TYPE(int32_t) \
@@ -21,4 +22,4 @@
TEST_ALL()
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */
--
2.34.1
prev parent reply other threads:[~2023-04-26 21:45 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-26 21:45 [PATCH v5 00/10] RISC-V: autovec: Add autovec support Michael Collison
2023-04-26 21:45 ` [PATCH v5 01/10] RISC-V: autovec: Add new predicates and function prototypes Michael Collison
2023-04-28 22:28 ` Jeff Law
2023-04-26 21:45 ` [PATCH v5 02/10] RISC-V: autovec: Export policy functions to global scope Michael Collison
2023-04-28 22:15 ` Jeff Law
2023-04-26 21:45 ` [PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions Michael Collison
2023-04-28 22:19 ` Jeff Law
2023-05-03 10:53 ` Kito Cheng
2023-05-03 17:31 ` Michael Collison
2023-05-06 20:13 ` Jeff Law
2023-04-26 21:45 ` [PATCH v5 04/10] RISC-V:autovec: Add target vectorization hooks Michael Collison
2023-05-03 10:59 ` Kito Cheng
2023-04-26 21:45 ` [PATCH v5 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store Michael Collison
2023-04-26 21:45 ` [PATCH v5 06/10] RISC-V:autovec: Add autovectorization tests for add & sub Michael Collison
2023-04-26 21:45 ` [PATCH v5 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2 Michael Collison
2023-05-02 10:11 ` Richard Sandiford
2023-04-26 21:45 ` [PATCH v5 08/10] RISC-V:autovec: Add autovectorization tests for binary integer Michael Collison
2023-04-26 21:45 ` [PATCH v5 09/10] RISC-V: autovec: This patch adds a guard for VNx1 vectors that are present in ports like riscv Michael Collison
2023-04-26 21:45 ` Michael Collison [this message]
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