[PATCH 01/16] arm: [MVE intrinsics] add binary_maxvminv shape

[PATCH 01/16] arm: [MVE intrinsics] add binary_maxvminv shape

[Christophe Lyon]

This patch adds the binary_maxvminv shape description.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/arm-mve-builtins-shapes.cc (binary_maxvminv): New.
	* config/arm/arm-mve-builtins-shapes.h (binary_maxvminv): New.
---
 gcc/config/arm/arm-mve-builtins-shapes.cc | 30 +++++++++++++++++++++++
 gcc/config/arm/arm-mve-builtins-shapes.h  |  1 +
 2 files changed, 31 insertions(+)

diff --git a/gcc/config/arm/arm-mve-builtins-shapes.cc b/gcc/config/arm/arm-mve-builtins-shapes.cc
index 1d43b8871bf..19c3c47a20e 100644
--- a/gcc/config/arm/arm-mve-builtins-shapes.cc
+++ b/gcc/config/arm/arm-mve-builtins-shapes.cc
@@ -401,6 +401,36 @@ struct binary_rshift_def : public overloaded_base<0>
 };
 SHAPE (binary_rshift)
 
+/* <S0>_t vfoo[_<t0>](<S0>_t, <T0>_t)
+
+   Example: vmaxvq.
+   int8_t [__arm_]vmaxvq[_s8](int8_t a, int8x16_t b)
+   int8_t [__arm_]vmaxvq_p[_s8](int8_t a, int8x16_t b, mve_pred16_t p)  */
+struct binary_maxvminv_def : public overloaded_base<0>
+{
+  void
+  build (function_builder &b, const function_group_info &group,
+	 bool preserve_user_namespace) const override
+  {
+    b.add_overloaded_functions (group, MODE_none, preserve_user_namespace);
+    build_all (b, "s0,s0,v0", group, MODE_none, preserve_user_namespace);
+  }
+
+  tree
+  resolve (function_resolver &r) const override
+  {
+    unsigned int i, nargs;
+    type_suffix_index type;
+    if (!r.check_gp_argument (2, i, nargs)
+	|| !r.require_derived_scalar_type (0, r.SAME_TYPE_CLASS)
+	|| (type = r.infer_vector_type (1)) == NUM_TYPE_SUFFIXES)
+      return error_mark_node;
+
+    return r.resolve_to (r.mode_suffix_id, type);
+  }
+};
+SHAPE (binary_maxvminv)
+
 /* <T0:half>_t vfoo[_t0](<T0:half>_t, <T0>_t)
 
    Example: vmovnbq.
diff --git a/gcc/config/arm/arm-mve-builtins-shapes.h b/gcc/config/arm/arm-mve-builtins-shapes.h
index dd2597dc6f5..9debf1d8733 100644
--- a/gcc/config/arm/arm-mve-builtins-shapes.h
+++ b/gcc/config/arm/arm-mve-builtins-shapes.h
@@ -37,6 +37,7 @@ namespace arm_mve
     extern const function_shape *const binary;
     extern const function_shape *const binary_lshift;
     extern const function_shape *const binary_lshift_r;
+    extern const function_shape *const binary_maxvminv;
     extern const function_shape *const binary_move_narrow;
     extern const function_shape *const binary_move_narrow_unsigned;
     extern const function_shape *const binary_opt_n;
-- 
2.34.1

[PATCH 02/16] arm: [MVE intrinsics] add binary_maxavminav shape

[Christophe Lyon]

This patch adds the binary_maxavminav shape description.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/arm-mve-builtins-shapes.cc (binary_maxavminav): New.
	* config/arm/arm-mve-builtins-shapes.h (binary_maxavminav): New.
---
 gcc/config/arm/arm-mve-builtins-shapes.cc | 30 +++++++++++++++++++++++
 gcc/config/arm/arm-mve-builtins-shapes.h  |  1 +
 2 files changed, 31 insertions(+)

diff --git a/gcc/config/arm/arm-mve-builtins-shapes.cc b/gcc/config/arm/arm-mve-builtins-shapes.cc
index 19c3c47a20e..1324abd1c12 100644
--- a/gcc/config/arm/arm-mve-builtins-shapes.cc
+++ b/gcc/config/arm/arm-mve-builtins-shapes.cc
@@ -401,6 +401,36 @@ struct binary_rshift_def : public overloaded_base<0>
 };
 SHAPE (binary_rshift)
 
+/* <uS0>_t vfoo[_<t0>](<uS0>_t, <T0>_t)
+
+   Example: vmaxavq.
+   uint8_t [__arm_]vmaxavq[_s8](uint8_t a, int8x16_t b)
+   uint8_t [__arm_]vmaxavq_p[_s8](uint8_t a, int8x16_t b, mve_pred16_t p)  */
+struct binary_maxavminav_def : public overloaded_base<0>
+{
+  void
+  build (function_builder &b, const function_group_info &group,
+	 bool preserve_user_namespace) const override
+  {
+    b.add_overloaded_functions (group, MODE_none, preserve_user_namespace);
+    build_all (b, "su0,su0,v0", group, MODE_none, preserve_user_namespace);
+  }
+
+  tree
+  resolve (function_resolver &r) const override
+  {
+    unsigned int i, nargs;
+    type_suffix_index type;
+    if (!r.check_gp_argument (2, i, nargs)
+	|| !r.require_derived_scalar_type (0, TYPE_unsigned)
+	|| (type = r.infer_vector_type (1)) == NUM_TYPE_SUFFIXES)
+      return error_mark_node;
+
+    return r.resolve_to (r.mode_suffix_id, type);
+  }
+};
+SHAPE (binary_maxavminav)
+
 /* <S0>_t vfoo[_<t0>](<S0>_t, <T0>_t)
 
    Example: vmaxvq.
diff --git a/gcc/config/arm/arm-mve-builtins-shapes.h b/gcc/config/arm/arm-mve-builtins-shapes.h
index 9debf1d8733..cf4c523ab1a 100644
--- a/gcc/config/arm/arm-mve-builtins-shapes.h
+++ b/gcc/config/arm/arm-mve-builtins-shapes.h
@@ -37,6 +37,7 @@ namespace arm_mve
     extern const function_shape *const binary;
     extern const function_shape *const binary_lshift;
     extern const function_shape *const binary_lshift_r;
+    extern const function_shape *const binary_maxavminav;
     extern const function_shape *const binary_maxvminv;
     extern const function_shape *const binary_move_narrow;
     extern const function_shape *const binary_move_narrow_unsigned;
-- 
2.34.1

[PATCH 03/16] arm: [MVE intrinsics add unspec_mve_function_exact_insn_pred_p

[Christophe Lyon]

Introduce a function that will be used to build intrinsics that use p
predication.

2022-09-08  Christophe Lyon <christophe.lyon@arm.com>

	gcc/
	* config/arm/arm-mve-builtins-functions.h (class
	unspec_mve_function_exact_insn_pred_p): New.
---
 gcc/config/arm/arm-mve-builtins-functions.h | 64 +++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/gcc/config/arm/arm-mve-builtins-functions.h b/gcc/config/arm/arm-mve-builtins-functions.h
index 533fd1159c6..bf4e209a720 100644
--- a/gcc/config/arm/arm-mve-builtins-functions.h
+++ b/gcc/config/arm/arm-mve-builtins-functions.h
@@ -376,6 +376,70 @@ public:
   }
 };
 
+/* Map the function directly to CODE (UNSPEC), when there is a
+   non-predicated version and one with the "_p" predicate.  */
+class unspec_mve_function_exact_insn_pred_p : public function_base
+{
+public:
+  CONSTEXPR unspec_mve_function_exact_insn_pred_p (int unspec_for_sint,
+						   int unspec_for_uint,
+						   int unspec_for_fp,
+						   int unspec_for_p_sint,
+						   int unspec_for_p_uint,
+						   int unspec_for_p_fp)
+    : m_unspec_for_sint (unspec_for_sint),
+      m_unspec_for_uint (unspec_for_uint),
+      m_unspec_for_fp (unspec_for_fp),
+      m_unspec_for_p_sint (unspec_for_p_sint),
+      m_unspec_for_p_uint (unspec_for_p_uint),
+      m_unspec_for_p_fp (unspec_for_p_fp)
+  {}
+
+  /* The unspec code associated with signed-integer and unsigned-integer
+     operations, with no predicate, or with "_p" predicate.  */
+  int m_unspec_for_sint;
+  int m_unspec_for_uint;
+  int m_unspec_for_fp;
+  int m_unspec_for_p_sint;
+  int m_unspec_for_p_uint;
+  int m_unspec_for_p_fp;
+
+  rtx
+  expand (function_expander &e) const override
+  {
+    insn_code code;
+    switch (e.pred)
+      {
+      case PRED_none:
+	if (e.type_suffix (0).integer_p)
+	  if (e.type_suffix (0).unsigned_p)
+	    code = code_for_mve_q (m_unspec_for_uint, m_unspec_for_uint, e.vector_mode (0));
+	  else
+	    code = code_for_mve_q (m_unspec_for_sint, m_unspec_for_sint, e.vector_mode (0));
+	else
+	  code = code_for_mve_q_f (m_unspec_for_fp, e.vector_mode (0));
+
+	return e.use_exact_insn (code);
+
+      case PRED_p:
+	if (e.type_suffix (0).integer_p)
+	  if (e.type_suffix (0).unsigned_p)
+	    code = code_for_mve_q_p (m_unspec_for_p_uint, m_unspec_for_p_uint, e.vector_mode (0));
+	  else
+	    code = code_for_mve_q_p (m_unspec_for_p_sint, m_unspec_for_p_sint, e.vector_mode (0));
+	else
+	  gcc_unreachable ();  /* Will be fixed later in the series.  */
+
+	return e.use_exact_insn (code);
+
+      default:
+	gcc_unreachable ();
+      }
+
+    gcc_unreachable ();
+  }
+};
+
 /* Map the function directly to CODE (UNSPEC, M) for vshl-like
    builtins. The difference with unspec_mve_function_exact_insn is
    that this function handles MODE_r and the related unspecs..  */
-- 
2.34.1

[PATCH 04/16] arm: [MVE intrinsics] factorize vmaxvq vminvq vmaxavq vminavq

[Christophe Lyon]

Factorize vmaxvq vminvq vmaxavq vminavq so that they use the same
pattern.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (MVE_VMAXVQ_VMINVQ, MVE_VMAXVQ_VMINVQ_P): New.
	(mve_insn): Add vmaxav, vmaxv, vminav, vminv.
	(supf): Add VMAXAVQ_S, VMAXAVQ_P_S, VMINAVQ_S, VMINAVQ_P_S.
	* config/arm/mve.md (mve_vmaxavq_s<mode>, mve_vmaxvq_<supf><mode>)
	(mve_vminavq_s<mode>, mve_vminvq_<supf><mode>): Merge into ...
	(@mve_<mve_insn>q_<supf><mode>): ... this.
	(mve_vmaxavq_p_s<mode>, mve_vmaxvq_p_<supf><mode>)
	(mve_vminavq_p_s<mode>, mve_vminvq_p_<supf><mode>): Merge into ...
	(@mve_<mve_insn>q_p_<supf><mode>): ... this.
---
 gcc/config/arm/iterators.md |  26 ++++++++
 gcc/config/arm/mve.md       | 115 +++++-------------------------------
 2 files changed, 40 insertions(+), 101 deletions(-)

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index e82ff0d5d9b..5bb7e2be7c8 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -578,6 +578,20 @@ (define_int_iterator MVE_FP_CREATE_ONLY [
 		     VCREATEQ_F
 		     ])
 
+(define_int_iterator MVE_VMAXVQ_VMINVQ [
+		     VMAXAVQ_S
+		     VMAXVQ_S VMAXVQ_U
+		     VMINAVQ_S
+		     VMINVQ_S VMINVQ_U
+		     ])
+
+(define_int_iterator MVE_VMAXVQ_VMINVQ_P [
+		     VMAXAVQ_P_S
+		     VMAXVQ_P_S VMAXVQ_P_U
+		     VMINAVQ_P_S
+		     VMINVQ_P_S VMINVQ_P_U
+		     ])
+
 (define_int_iterator MVE_MOVN [
 		     VMOVNBQ_S VMOVNBQ_U
 		     VMOVNTQ_S VMOVNTQ_U
@@ -627,8 +641,16 @@ (define_int_attr mve_insn [
 		 (VHSUBQ_M_S "vhsub") (VHSUBQ_M_U "vhsub")
 		 (VHSUBQ_N_S "vhsub") (VHSUBQ_N_U "vhsub")
 		 (VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub")
+		 (VMAXAVQ_P_S "vmaxav")
+		 (VMAXAVQ_S "vmaxav")
 		 (VMAXQ_M_S "vmax") (VMAXQ_M_U "vmax")
+		 (VMAXVQ_P_S "vmaxv") (VMAXVQ_P_U "vmaxv")
+		 (VMAXVQ_S "vmaxv") (VMAXVQ_U "vmaxv")
+		 (VMINAVQ_P_S "vminav")
+		 (VMINAVQ_S "vminav")
 		 (VMINQ_M_S "vmin") (VMINQ_M_U "vmin")
+		 (VMINVQ_P_S "vminv") (VMINVQ_P_U "vminv")
+		 (VMINVQ_S "vminv") (VMINVQ_U "vminv")
 		 (VMLAQ_M_N_S "vmla") (VMLAQ_M_N_U "vmla")
 		 (VMLASQ_M_N_S "vmlas") (VMLASQ_M_N_U "vmlas")
 		 (VMOVNBQ_M_S "vmovnb") (VMOVNBQ_M_U "vmovnb")
@@ -1992,6 +2014,10 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
 		       (VQMOVUNBQ_S "s")
 		       (VQMOVUNTQ_M_S "s")
 		       (VQMOVUNTQ_S "s")
+		       (VMAXAVQ_S "s")
+		       (VMAXAVQ_P_S "s")
+		       (VMINAVQ_S "s")
+		       (VMINAVQ_P_S "s")
 		       ])
 
 ;; Both kinds of return insn.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 98728e6f3ef..715e85c9998 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -962,21 +962,6 @@ (define_insn "mve_vmaxaq_s<mode>"
   [(set_attr "type" "mve_move")
 ])
 
-;;
-;; [vmaxavq_s])
-;;
-(define_insn "mve_vmaxavq_s<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-			  (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VMAXAVQ_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vmaxav.s%#<V_sz_elem>\t%0, %q2"
-  [(set_attr "type" "mve_move")
-])
-
 ;;
 ;; [vmaxq_u, vmaxq_s]
 ;; [vminq_s, vminq_u]
@@ -994,17 +979,20 @@ (define_insn "mve_<max_min_su_str>q_<max_min_supf><mode>"
 
 
 ;;
-;; [vmaxvq_u, vmaxvq_s])
+;; [vmaxavq_s]
+;; [vmaxvq_u, vmaxvq_s]
+;; [vminavq_s]
+;; [vminvq_u, vminvq_s]
 ;;
-(define_insn "mve_vmaxvq_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
   [
    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
 	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
 			  (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VMAXVQ))
+	 MVE_VMAXVQ_VMINVQ))
   ]
   "TARGET_HAVE_MVE"
-  "vmaxv.<supf>%#<V_sz_elem>\t%0, %q2"
+  "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1023,36 +1011,6 @@ (define_insn "mve_vminaq_s<mode>"
   [(set_attr "type" "mve_move")
 ])
 
-;;
-;; [vminavq_s])
-;;
-(define_insn "mve_vminavq_s<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-			  (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VMINAVQ_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vminav.s%#<V_sz_elem>\t%0, %q2"
-  [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vminvq_u, vminvq_s])
-;;
-(define_insn "mve_vminvq_<supf><mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-			  (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VMINVQ))
-  ]
-  "TARGET_HAVE_MVE"
-  "vminv.<supf>%#<V_sz_elem>\t%0, %q2"
-  [(set_attr "type" "mve_move")
-])
-
 ;;
 ;; [vmladavq_u, vmladavq_s])
 ;;
@@ -2366,34 +2324,21 @@ (define_insn "mve_vmaxaq_m_s<mode>"
    (set_attr "length""8")])
 
 ;;
-;; [vmaxavq_p_s])
-;;
-(define_insn "mve_vmaxavq_p_s<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")
-		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VMAXAVQ_P_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vmaxavt.s%#<V_sz_elem>	%0, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
-;;
-;; [vmaxvq_p_u, vmaxvq_p_s])
+;; [vmaxavq_p_s]
+;; [vmaxvq_p_u, vmaxvq_p_s]
+;; [vminavq_p_s]
+;; [vminvq_p_s, vminvq_p_u]
 ;;
-(define_insn "mve_vmaxvq_p_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_p_<supf><mode>"
   [
    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
 	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
 		       (match_operand:MVE_2 2 "s_register_operand" "w")
 		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VMAXVQ_P))
+	 MVE_VMAXVQ_VMINVQ_P))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmaxvt.<supf>%#<V_sz_elem>	%0, %q2"
+  "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -2413,38 +2358,6 @@ (define_insn "mve_vminaq_m_s<mode>"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
-;;
-;; [vminavq_p_s])
-;;
-(define_insn "mve_vminavq_p_s<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")
-		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VMINAVQ_P_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vminavt.s%#<V_sz_elem>	%0, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
-;;
-;; [vminvq_p_s, vminvq_p_u])
-;;
-(define_insn "mve_vminvq_p_<supf><mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")
-		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VMINVQ_P))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vminvt.<supf>%#<V_sz_elem>\t%0, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
 ;;
 ;; [vmladavaq_u, vmladavaq_s])
 ;;
-- 
2.34.1

[PATCH 05/16] arm: [MVE intrinsics] rework vmaxvq vminvq vmaxavq vminavq

[Christophe Lyon]

Implement vmaxvq, vminvq, vmaxavq, vminavq using the new MVE builtins
framework.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/arm-mve-builtins-base.cc (FUNCTION_PRED_P_S_U)
	(FUNCTION_PRED_P_S): New.
	(vmaxavq, vminavq, vmaxvq, vminvq): New.
	* config/arm/arm-mve-builtins-base.def (vmaxavq, vminavq, vmaxvq)
	(vminvq): New.
	* config/arm/arm-mve-builtins-base.h (vmaxavq, vminavq, vmaxvq)
	(vminvq): New.
	* config/arm/arm_mve.h (vminvq): Remove.
	(vmaxvq): Remove.
	(vminvq_p): Remove.
	(vmaxvq_p): Remove.
	(vminvq_u8): Remove.
	(vmaxvq_u8): Remove.
	(vminvq_s8): Remove.
	(vmaxvq_s8): Remove.
	(vminvq_u16): Remove.
	(vmaxvq_u16): Remove.
	(vminvq_s16): Remove.
	(vmaxvq_s16): Remove.
	(vminvq_u32): Remove.
	(vmaxvq_u32): Remove.
	(vminvq_s32): Remove.
	(vmaxvq_s32): Remove.
	(vminvq_p_u8): Remove.
	(vmaxvq_p_u8): Remove.
	(vminvq_p_s8): Remove.
	(vmaxvq_p_s8): Remove.
	(vminvq_p_u16): Remove.
	(vmaxvq_p_u16): Remove.
	(vminvq_p_s16): Remove.
	(vmaxvq_p_s16): Remove.
	(vminvq_p_u32): Remove.
	(vmaxvq_p_u32): Remove.
	(vminvq_p_s32): Remove.
	(vmaxvq_p_s32): Remove.
	(__arm_vminvq_u8): Remove.
	(__arm_vmaxvq_u8): Remove.
	(__arm_vminvq_s8): Remove.
	(__arm_vmaxvq_s8): Remove.
	(__arm_vminvq_u16): Remove.
	(__arm_vmaxvq_u16): Remove.
	(__arm_vminvq_s16): Remove.
	(__arm_vmaxvq_s16): Remove.
	(__arm_vminvq_u32): Remove.
	(__arm_vmaxvq_u32): Remove.
	(__arm_vminvq_s32): Remove.
	(__arm_vmaxvq_s32): Remove.
	(__arm_vminvq_p_u8): Remove.
	(__arm_vmaxvq_p_u8): Remove.
	(__arm_vminvq_p_s8): Remove.
	(__arm_vmaxvq_p_s8): Remove.
	(__arm_vminvq_p_u16): Remove.
	(__arm_vmaxvq_p_u16): Remove.
	(__arm_vminvq_p_s16): Remove.
	(__arm_vmaxvq_p_s16): Remove.
	(__arm_vminvq_p_u32): Remove.
	(__arm_vmaxvq_p_u32): Remove.
	(__arm_vminvq_p_s32): Remove.
	(__arm_vmaxvq_p_s32): Remove.
	(__arm_vminvq): Remove.
	(__arm_vmaxvq): Remove.
	(__arm_vminvq_p): Remove.
	(__arm_vmaxvq_p): Remove.
	(vminavq): Remove.
	(vmaxavq): Remove.
	(vminavq_p): Remove.
	(vmaxavq_p): Remove.
	(vminavq_s8): Remove.
	(vmaxavq_s8): Remove.
	(vminavq_s16): Remove.
	(vmaxavq_s16): Remove.
	(vminavq_s32): Remove.
	(vmaxavq_s32): Remove.
	(vminavq_p_s8): Remove.
	(vmaxavq_p_s8): Remove.
	(vminavq_p_s16): Remove.
	(vmaxavq_p_s16): Remove.
	(vminavq_p_s32): Remove.
	(vmaxavq_p_s32): Remove.
	(__arm_vminavq_s8): Remove.
	(__arm_vmaxavq_s8): Remove.
	(__arm_vminavq_s16): Remove.
	(__arm_vmaxavq_s16): Remove.
	(__arm_vminavq_s32): Remove.
	(__arm_vmaxavq_s32): Remove.
	(__arm_vminavq_p_s8): Remove.
	(__arm_vmaxavq_p_s8): Remove.
	(__arm_vminavq_p_s16): Remove.
	(__arm_vmaxavq_p_s16): Remove.
	(__arm_vminavq_p_s32): Remove.
	(__arm_vmaxavq_p_s32): Remove.
	(__arm_vminavq): Remove.
	(__arm_vmaxavq): Remove.
	(__arm_vminavq_p): Remove.
	(__arm_vmaxavq_p): Remove.
---
 gcc/config/arm/arm-mve-builtins-base.cc  |  17 +
 gcc/config/arm/arm-mve-builtins-base.def |   4 +
 gcc/config/arm/arm-mve-builtins-base.h   |   4 +
 gcc/config/arm/arm_mve.h                 | 616 -----------------------
 4 files changed, 25 insertions(+), 616 deletions(-)

diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc
index aafd85b293d..cfab3f222ed 100644
--- a/gcc/config/arm/arm-mve-builtins-base.cc
+++ b/gcc/config/arm/arm-mve-builtins-base.cc
@@ -212,6 +212,19 @@ namespace arm_mve {
     -1, -1, UNSPEC##_M_F,						\
     -1, -1, -1))
 
+  /* Helper for builtins without RTX codes, _S mode, _p predicated.  */
+#define FUNCTION_PRED_P_S(NAME, UNSPEC) FUNCTION			\
+  (NAME, unspec_mve_function_exact_insn_pred_p,				\
+   (UNSPEC##_S, -1, -1,							\
+    UNSPEC##_P_S, -1, -1))
+
+  /* Helper for builtins without RTX codes, _S and _U modes, _p
+     predicated.  */
+#define FUNCTION_PRED_P_S_U(NAME, UNSPEC) FUNCTION			\
+  (NAME, unspec_mve_function_exact_insn_pred_p,				\
+   (UNSPEC##_S, UNSPEC##_U, -1,						\
+    UNSPEC##_P_S, UNSPEC##_P_U, -1))
+
 FUNCTION_WITHOUT_N (vabdq, VABDQ)
 FUNCTION (vabsq, unspec_based_mve_function_exact_insn, (ABS, ABS, ABS, -1, -1, -1, VABSQ_M_S, -1, VABSQ_M_F, -1, -1, -1))
 FUNCTION_WITH_RTX_M_N (vaddq, PLUS, VADDQ)
@@ -222,8 +235,12 @@ FUNCTION_WITHOUT_M_N (vcreateq, VCREATEQ)
 FUNCTION_WITH_RTX_M (veorq, XOR, VEORQ)
 FUNCTION_WITH_M_N_NO_F (vhaddq, VHADDQ)
 FUNCTION_WITH_M_N_NO_F (vhsubq, VHSUBQ)
+FUNCTION_PRED_P_S (vmaxavq, VMAXAVQ)
 FUNCTION_WITH_RTX_M_NO_F (vmaxq, SMAX, UMAX, VMAXQ)
+FUNCTION_PRED_P_S_U (vmaxvq, VMAXVQ)
+FUNCTION_PRED_P_S (vminavq, VMINAVQ)
 FUNCTION_WITH_RTX_M_NO_F (vminq, SMIN, UMIN, VMINQ)
+FUNCTION_PRED_P_S_U (vminvq, VMINVQ)
 FUNCTION_WITHOUT_N_NO_F (vmovnbq, VMOVNBQ)
 FUNCTION_WITHOUT_N_NO_F (vmovntq, VMOVNTQ)
 FUNCTION_WITHOUT_N_NO_F (vmulhq, VMULHQ)
diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def
index 78c7515b972..d06e134719e 100644
--- a/gcc/config/arm/arm-mve-builtins-base.def
+++ b/gcc/config/arm/arm-mve-builtins-base.def
@@ -28,8 +28,12 @@ DEF_MVE_FUNCTION (vcreateq, create, all_integer_with_64, none)
 DEF_MVE_FUNCTION (veorq, binary, all_integer, mx_or_none)
 DEF_MVE_FUNCTION (vhaddq, binary_opt_n, all_integer, mx_or_none)
 DEF_MVE_FUNCTION (vhsubq, binary_opt_n, all_integer, mx_or_none)
+DEF_MVE_FUNCTION (vmaxavq, binary_maxavminav, all_signed, p_or_none)
 DEF_MVE_FUNCTION (vmaxq, binary, all_integer, mx_or_none)
+DEF_MVE_FUNCTION (vmaxvq, binary_maxvminv, all_integer, p_or_none)
+DEF_MVE_FUNCTION (vminavq, binary_maxavminav, all_signed, p_or_none)
 DEF_MVE_FUNCTION (vminq, binary, all_integer, mx_or_none)
+DEF_MVE_FUNCTION (vminvq, binary_maxvminv, all_integer, p_or_none)
 DEF_MVE_FUNCTION (vmovnbq, binary_move_narrow, integer_16_32, m_or_none)
 DEF_MVE_FUNCTION (vmovntq, binary_move_narrow, integer_16_32, m_or_none)
 DEF_MVE_FUNCTION (vmulhq, binary, all_integer, mx_or_none)
diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h
index e5a83466512..30e0f42a352 100644
--- a/gcc/config/arm/arm-mve-builtins-base.h
+++ b/gcc/config/arm/arm-mve-builtins-base.h
@@ -33,8 +33,12 @@ extern const function_base *const vcreateq;
 extern const function_base *const veorq;
 extern const function_base *const vhaddq;
 extern const function_base *const vhsubq;
+extern const function_base *const vmaxavq;
 extern const function_base *const vmaxq;
+extern const function_base *const vmaxvq;
+extern const function_base *const vminavq;
 extern const function_base *const vminq;
+extern const function_base *const vminvq;
 extern const function_base *const vmovnbq;
 extern const function_base *const vmovntq;
 extern const function_base *const vmulhq;
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 8258ee0b802..dddaab74bc0 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -57,8 +57,6 @@
 #define vmulltq_int(__a, __b) __arm_vmulltq_int(__a, __b)
 #define vmullbq_int(__a, __b) __arm_vmullbq_int(__a, __b)
 #define vmladavq(__a, __b) __arm_vmladavq(__a, __b)
-#define vminvq(__a, __b) __arm_vminvq(__a, __b)
-#define vmaxvq(__a, __b) __arm_vmaxvq(__a, __b)
 #define vcmphiq(__a, __b) __arm_vcmphiq(__a, __b)
 #define vcmpeqq(__a, __b) __arm_vcmpeqq(__a, __b)
 #define vcmpcsq(__a, __b) __arm_vcmpcsq(__a, __b)
@@ -67,9 +65,7 @@
 #define vbicq(__a, __b) __arm_vbicq(__a, __b)
 #define vaddvq_p(__a, __p) __arm_vaddvq_p(__a, __p)
 #define vaddvaq(__a, __b) __arm_vaddvaq(__a, __b)
-#define vminavq(__a, __b) __arm_vminavq(__a, __b)
 #define vminaq(__a, __b) __arm_vminaq(__a, __b)
-#define vmaxavq(__a, __b) __arm_vmaxavq(__a, __b)
 #define vmaxaq(__a, __b) __arm_vmaxaq(__a, __b)
 #define vbrsrq(__a, __b) __arm_vbrsrq(__a, __b)
 #define vcmpltq(__a, __b) __arm_vcmpltq(__a, __b)
@@ -110,8 +106,6 @@
 #define vmlaq(__a, __b, __c) __arm_vmlaq(__a, __b, __c)
 #define vmladavq_p(__a, __b, __p) __arm_vmladavq_p(__a, __b, __p)
 #define vmladavaq(__a, __b, __c) __arm_vmladavaq(__a, __b, __c)
-#define vminvq_p(__a, __b, __p) __arm_vminvq_p(__a, __b, __p)
-#define vmaxvq_p(__a, __b, __p) __arm_vmaxvq_p(__a, __b, __p)
 #define vdupq_m(__inactive, __a, __p) __arm_vdupq_m(__inactive, __a, __p)
 #define vcmpneq_m(__a, __b, __p) __arm_vcmpneq_m(__a, __b, __p)
 #define vcmphiq_m(__a, __b, __p) __arm_vcmphiq_m(__a, __b, __p)
@@ -121,9 +115,7 @@
 #define vaddvaq_p(__a, __b, __p) __arm_vaddvaq_p(__a, __b, __p)
 #define vsriq(__a, __b, __imm) __arm_vsriq(__a, __b, __imm)
 #define vsliq(__a, __b, __imm) __arm_vsliq(__a, __b, __imm)
-#define vminavq_p(__a, __b, __p) __arm_vminavq_p(__a, __b, __p)
 #define vminaq_m(__a, __b, __p) __arm_vminaq_m(__a, __b, __p)
-#define vmaxavq_p(__a, __b, __p) __arm_vmaxavq_p(__a, __b, __p)
 #define vmaxaq_m(__a, __b, __p) __arm_vmaxaq_m(__a, __b, __p)
 #define vcmpltq_m(__a, __b, __p) __arm_vcmpltq_m(__a, __b, __p)
 #define vcmpleq_m(__a, __b, __p) __arm_vcmpleq_m(__a, __b, __p)
@@ -482,8 +474,6 @@
 #define vmulltq_int_u8(__a, __b) __arm_vmulltq_int_u8(__a, __b)
 #define vmullbq_int_u8(__a, __b) __arm_vmullbq_int_u8(__a, __b)
 #define vmladavq_u8(__a, __b) __arm_vmladavq_u8(__a, __b)
-#define vminvq_u8(__a, __b) __arm_vminvq_u8(__a, __b)
-#define vmaxvq_u8(__a, __b) __arm_vmaxvq_u8(__a, __b)
 #define vcmpneq_n_u8(__a, __b) __arm_vcmpneq_n_u8(__a, __b)
 #define vcmphiq_u8(__a, __b) __arm_vcmphiq_u8(__a, __b)
 #define vcmphiq_n_u8(__a, __b) __arm_vcmphiq_n_u8(__a, __b)
@@ -496,9 +486,7 @@
 #define vbicq_u8(__a, __b) __arm_vbicq_u8(__a, __b)
 #define vaddvq_p_u8(__a, __p) __arm_vaddvq_p_u8(__a, __p)
 #define vaddvaq_u8(__a, __b) __arm_vaddvaq_u8(__a, __b)
-#define vminavq_s8(__a, __b) __arm_vminavq_s8(__a, __b)
 #define vminaq_s8(__a, __b) __arm_vminaq_s8(__a, __b)
-#define vmaxavq_s8(__a, __b) __arm_vmaxavq_s8(__a, __b)
 #define vmaxaq_s8(__a, __b) __arm_vmaxaq_s8(__a, __b)
 #define vbrsrq_n_u8(__a, __b) __arm_vbrsrq_n_u8(__a, __b)
 #define vcmpneq_n_s8(__a, __b) __arm_vcmpneq_n_s8(__a, __b)
@@ -521,8 +509,6 @@
 #define vmlsdavq_s8(__a, __b) __arm_vmlsdavq_s8(__a, __b)
 #define vmladavxq_s8(__a, __b) __arm_vmladavxq_s8(__a, __b)
 #define vmladavq_s8(__a, __b) __arm_vmladavq_s8(__a, __b)
-#define vminvq_s8(__a, __b) __arm_vminvq_s8(__a, __b)
-#define vmaxvq_s8(__a, __b) __arm_vmaxvq_s8(__a, __b)
 #define vhcaddq_rot90_s8(__a, __b) __arm_vhcaddq_rot90_s8(__a, __b)
 #define vhcaddq_rot270_s8(__a, __b) __arm_vhcaddq_rot270_s8(__a, __b)
 #define vcaddq_rot90_s8(__a, __b) __arm_vcaddq_rot90_s8(__a, __b)
@@ -534,8 +520,6 @@
 #define vmulltq_int_u16(__a, __b) __arm_vmulltq_int_u16(__a, __b)
 #define vmullbq_int_u16(__a, __b) __arm_vmullbq_int_u16(__a, __b)
 #define vmladavq_u16(__a, __b) __arm_vmladavq_u16(__a, __b)
-#define vminvq_u16(__a, __b) __arm_vminvq_u16(__a, __b)
-#define vmaxvq_u16(__a, __b) __arm_vmaxvq_u16(__a, __b)
 #define vcmpneq_n_u16(__a, __b) __arm_vcmpneq_n_u16(__a, __b)
 #define vcmphiq_u16(__a, __b) __arm_vcmphiq_u16(__a, __b)
 #define vcmphiq_n_u16(__a, __b) __arm_vcmphiq_n_u16(__a, __b)
@@ -548,9 +532,7 @@
 #define vbicq_u16(__a, __b) __arm_vbicq_u16(__a, __b)
 #define vaddvq_p_u16(__a, __p) __arm_vaddvq_p_u16(__a, __p)
 #define vaddvaq_u16(__a, __b) __arm_vaddvaq_u16(__a, __b)
-#define vminavq_s16(__a, __b) __arm_vminavq_s16(__a, __b)
 #define vminaq_s16(__a, __b) __arm_vminaq_s16(__a, __b)
-#define vmaxavq_s16(__a, __b) __arm_vmaxavq_s16(__a, __b)
 #define vmaxaq_s16(__a, __b) __arm_vmaxaq_s16(__a, __b)
 #define vbrsrq_n_u16(__a, __b) __arm_vbrsrq_n_u16(__a, __b)
 #define vcmpneq_n_s16(__a, __b) __arm_vcmpneq_n_s16(__a, __b)
@@ -573,8 +555,6 @@
 #define vmlsdavq_s16(__a, __b) __arm_vmlsdavq_s16(__a, __b)
 #define vmladavxq_s16(__a, __b) __arm_vmladavxq_s16(__a, __b)
 #define vmladavq_s16(__a, __b) __arm_vmladavq_s16(__a, __b)
-#define vminvq_s16(__a, __b) __arm_vminvq_s16(__a, __b)
-#define vmaxvq_s16(__a, __b) __arm_vmaxvq_s16(__a, __b)
 #define vhcaddq_rot90_s16(__a, __b) __arm_vhcaddq_rot90_s16(__a, __b)
 #define vhcaddq_rot270_s16(__a, __b) __arm_vhcaddq_rot270_s16(__a, __b)
 #define vcaddq_rot90_s16(__a, __b) __arm_vcaddq_rot90_s16(__a, __b)
@@ -586,8 +566,6 @@
 #define vmulltq_int_u32(__a, __b) __arm_vmulltq_int_u32(__a, __b)
 #define vmullbq_int_u32(__a, __b) __arm_vmullbq_int_u32(__a, __b)
 #define vmladavq_u32(__a, __b) __arm_vmladavq_u32(__a, __b)
-#define vminvq_u32(__a, __b) __arm_vminvq_u32(__a, __b)
-#define vmaxvq_u32(__a, __b) __arm_vmaxvq_u32(__a, __b)
 #define vcmpneq_n_u32(__a, __b) __arm_vcmpneq_n_u32(__a, __b)
 #define vcmphiq_u32(__a, __b) __arm_vcmphiq_u32(__a, __b)
 #define vcmphiq_n_u32(__a, __b) __arm_vcmphiq_n_u32(__a, __b)
@@ -600,9 +578,7 @@
 #define vbicq_u32(__a, __b) __arm_vbicq_u32(__a, __b)
 #define vaddvq_p_u32(__a, __p) __arm_vaddvq_p_u32(__a, __p)
 #define vaddvaq_u32(__a, __b) __arm_vaddvaq_u32(__a, __b)
-#define vminavq_s32(__a, __b) __arm_vminavq_s32(__a, __b)
 #define vminaq_s32(__a, __b) __arm_vminaq_s32(__a, __b)
-#define vmaxavq_s32(__a, __b) __arm_vmaxavq_s32(__a, __b)
 #define vmaxaq_s32(__a, __b) __arm_vmaxaq_s32(__a, __b)
 #define vbrsrq_n_u32(__a, __b) __arm_vbrsrq_n_u32(__a, __b)
 #define vcmpneq_n_s32(__a, __b) __arm_vcmpneq_n_s32(__a, __b)
@@ -625,8 +601,6 @@
 #define vmlsdavq_s32(__a, __b) __arm_vmlsdavq_s32(__a, __b)
 #define vmladavxq_s32(__a, __b) __arm_vmladavxq_s32(__a, __b)
 #define vmladavq_s32(__a, __b) __arm_vmladavq_s32(__a, __b)
-#define vminvq_s32(__a, __b) __arm_vminvq_s32(__a, __b)
-#define vmaxvq_s32(__a, __b) __arm_vmaxvq_s32(__a, __b)
 #define vhcaddq_rot90_s32(__a, __b) __arm_vhcaddq_rot90_s32(__a, __b)
 #define vhcaddq_rot270_s32(__a, __b) __arm_vhcaddq_rot270_s32(__a, __b)
 #define vcaddq_rot90_s32(__a, __b) __arm_vcaddq_rot90_s32(__a, __b)
@@ -765,8 +739,6 @@
 #define vmlaq_n_u8(__a, __b, __c) __arm_vmlaq_n_u8(__a, __b, __c)
 #define vmladavq_p_u8(__a, __b, __p) __arm_vmladavq_p_u8(__a, __b, __p)
 #define vmladavaq_u8(__a, __b, __c) __arm_vmladavaq_u8(__a, __b, __c)
-#define vminvq_p_u8(__a, __b, __p) __arm_vminvq_p_u8(__a, __b, __p)
-#define vmaxvq_p_u8(__a, __b, __p) __arm_vmaxvq_p_u8(__a, __b, __p)
 #define vdupq_m_n_u8(__inactive, __a, __p) __arm_vdupq_m_n_u8(__inactive, __a, __p)
 #define vcmpneq_m_u8(__a, __b, __p) __arm_vcmpneq_m_u8(__a, __b, __p)
 #define vcmpneq_m_n_u8(__a, __b, __p) __arm_vcmpneq_m_n_u8(__a, __b, __p)
@@ -779,9 +751,7 @@
 #define vaddvaq_p_u8(__a, __b, __p) __arm_vaddvaq_p_u8(__a, __b, __p)
 #define vsriq_n_u8(__a, __b,  __imm) __arm_vsriq_n_u8(__a, __b,  __imm)
 #define vsliq_n_u8(__a, __b,  __imm) __arm_vsliq_n_u8(__a, __b,  __imm)
-#define vminavq_p_s8(__a, __b, __p) __arm_vminavq_p_s8(__a, __b, __p)
 #define vminaq_m_s8(__a, __b, __p) __arm_vminaq_m_s8(__a, __b, __p)
-#define vmaxavq_p_s8(__a, __b, __p) __arm_vmaxavq_p_s8(__a, __b, __p)
 #define vmaxaq_m_s8(__a, __b, __p) __arm_vmaxaq_m_s8(__a, __b, __p)
 #define vcmpneq_m_s8(__a, __b, __p) __arm_vcmpneq_m_s8(__a, __b, __p)
 #define vcmpneq_m_n_s8(__a, __b, __p) __arm_vcmpneq_m_n_s8(__a, __b, __p)
@@ -801,8 +771,6 @@
 #define vmlsdavq_p_s8(__a, __b, __p) __arm_vmlsdavq_p_s8(__a, __b, __p)
 #define vmladavxq_p_s8(__a, __b, __p) __arm_vmladavxq_p_s8(__a, __b, __p)
 #define vmladavq_p_s8(__a, __b, __p) __arm_vmladavq_p_s8(__a, __b, __p)
-#define vminvq_p_s8(__a, __b, __p) __arm_vminvq_p_s8(__a, __b, __p)
-#define vmaxvq_p_s8(__a, __b, __p) __arm_vmaxvq_p_s8(__a, __b, __p)
 #define vdupq_m_n_s8(__inactive, __a, __p) __arm_vdupq_m_n_s8(__inactive, __a, __p)
 #define vaddvaq_p_s8(__a, __b, __p) __arm_vaddvaq_p_s8(__a, __b, __p)
 #define vqrdmlsdhxq_s8(__inactive, __a, __b) __arm_vqrdmlsdhxq_s8(__inactive, __a, __b)
@@ -833,8 +801,6 @@
 #define vmlaq_n_u16(__a, __b, __c) __arm_vmlaq_n_u16(__a, __b, __c)
 #define vmladavq_p_u16(__a, __b, __p) __arm_vmladavq_p_u16(__a, __b, __p)
 #define vmladavaq_u16(__a, __b, __c) __arm_vmladavaq_u16(__a, __b, __c)
-#define vminvq_p_u16(__a, __b, __p) __arm_vminvq_p_u16(__a, __b, __p)
-#define vmaxvq_p_u16(__a, __b, __p) __arm_vmaxvq_p_u16(__a, __b, __p)
 #define vdupq_m_n_u16(__inactive, __a, __p) __arm_vdupq_m_n_u16(__inactive, __a, __p)
 #define vcmpneq_m_u16(__a, __b, __p) __arm_vcmpneq_m_u16(__a, __b, __p)
 #define vcmpneq_m_n_u16(__a, __b, __p) __arm_vcmpneq_m_n_u16(__a, __b, __p)
@@ -847,9 +813,7 @@
 #define vaddvaq_p_u16(__a, __b, __p) __arm_vaddvaq_p_u16(__a, __b, __p)
 #define vsriq_n_u16(__a, __b,  __imm) __arm_vsriq_n_u16(__a, __b,  __imm)
 #define vsliq_n_u16(__a, __b,  __imm) __arm_vsliq_n_u16(__a, __b,  __imm)
-#define vminavq_p_s16(__a, __b, __p) __arm_vminavq_p_s16(__a, __b, __p)
 #define vminaq_m_s16(__a, __b, __p) __arm_vminaq_m_s16(__a, __b, __p)
-#define vmaxavq_p_s16(__a, __b, __p) __arm_vmaxavq_p_s16(__a, __b, __p)
 #define vmaxaq_m_s16(__a, __b, __p) __arm_vmaxaq_m_s16(__a, __b, __p)
 #define vcmpneq_m_s16(__a, __b, __p) __arm_vcmpneq_m_s16(__a, __b, __p)
 #define vcmpneq_m_n_s16(__a, __b, __p) __arm_vcmpneq_m_n_s16(__a, __b, __p)
@@ -869,8 +833,6 @@
 #define vmlsdavq_p_s16(__a, __b, __p) __arm_vmlsdavq_p_s16(__a, __b, __p)
 #define vmladavxq_p_s16(__a, __b, __p) __arm_vmladavxq_p_s16(__a, __b, __p)
 #define vmladavq_p_s16(__a, __b, __p) __arm_vmladavq_p_s16(__a, __b, __p)
-#define vminvq_p_s16(__a, __b, __p) __arm_vminvq_p_s16(__a, __b, __p)
-#define vmaxvq_p_s16(__a, __b, __p) __arm_vmaxvq_p_s16(__a, __b, __p)
 #define vdupq_m_n_s16(__inactive, __a, __p) __arm_vdupq_m_n_s16(__inactive, __a, __p)
 #define vaddvaq_p_s16(__a, __b, __p) __arm_vaddvaq_p_s16(__a, __b, __p)
 #define vqrdmlsdhxq_s16(__inactive, __a, __b) __arm_vqrdmlsdhxq_s16(__inactive, __a, __b)
@@ -901,8 +863,6 @@
 #define vmlaq_n_u32(__a, __b, __c) __arm_vmlaq_n_u32(__a, __b, __c)
 #define vmladavq_p_u32(__a, __b, __p) __arm_vmladavq_p_u32(__a, __b, __p)
 #define vmladavaq_u32(__a, __b, __c) __arm_vmladavaq_u32(__a, __b, __c)
-#define vminvq_p_u32(__a, __b, __p) __arm_vminvq_p_u32(__a, __b, __p)
-#define vmaxvq_p_u32(__a, __b, __p) __arm_vmaxvq_p_u32(__a, __b, __p)
 #define vdupq_m_n_u32(__inactive, __a, __p) __arm_vdupq_m_n_u32(__inactive, __a, __p)
 #define vcmpneq_m_u32(__a, __b, __p) __arm_vcmpneq_m_u32(__a, __b, __p)
 #define vcmpneq_m_n_u32(__a, __b, __p) __arm_vcmpneq_m_n_u32(__a, __b, __p)
@@ -915,9 +875,7 @@
 #define vaddvaq_p_u32(__a, __b, __p) __arm_vaddvaq_p_u32(__a, __b, __p)
 #define vsriq_n_u32(__a, __b,  __imm) __arm_vsriq_n_u32(__a, __b,  __imm)
 #define vsliq_n_u32(__a, __b,  __imm) __arm_vsliq_n_u32(__a, __b,  __imm)
-#define vminavq_p_s32(__a, __b, __p) __arm_vminavq_p_s32(__a, __b, __p)
 #define vminaq_m_s32(__a, __b, __p) __arm_vminaq_m_s32(__a, __b, __p)
-#define vmaxavq_p_s32(__a, __b, __p) __arm_vmaxavq_p_s32(__a, __b, __p)
 #define vmaxaq_m_s32(__a, __b, __p) __arm_vmaxaq_m_s32(__a, __b, __p)
 #define vcmpneq_m_s32(__a, __b, __p) __arm_vcmpneq_m_s32(__a, __b, __p)
 #define vcmpneq_m_n_s32(__a, __b, __p) __arm_vcmpneq_m_n_s32(__a, __b, __p)
@@ -937,8 +895,6 @@
 #define vmlsdavq_p_s32(__a, __b, __p) __arm_vmlsdavq_p_s32(__a, __b, __p)
 #define vmladavxq_p_s32(__a, __b, __p) __arm_vmladavxq_p_s32(__a, __b, __p)
 #define vmladavq_p_s32(__a, __b, __p) __arm_vmladavq_p_s32(__a, __b, __p)
-#define vminvq_p_s32(__a, __b, __p) __arm_vminvq_p_s32(__a, __b, __p)
-#define vmaxvq_p_s32(__a, __b, __p) __arm_vmaxvq_p_s32(__a, __b, __p)
 #define vdupq_m_n_s32(__inactive, __a, __p) __arm_vdupq_m_n_s32(__inactive, __a, __p)
 #define vaddvaq_p_s32(__a, __b, __p) __arm_vaddvaq_p_s32(__a, __b, __p)
 #define vqrdmlsdhxq_s32(__inactive, __a, __b) __arm_vqrdmlsdhxq_s32(__inactive, __a, __b)
@@ -2333,20 +2289,6 @@ __arm_vmladavq_u8 (uint8x16_t __a, uint8x16_t __b)
   return __builtin_mve_vmladavq_uv16qi (__a, __b);
 }
 
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_u8 (uint8_t __a, uint8x16_t __b)
-{
-  return __builtin_mve_vminvq_uv16qi (__a, __b);
-}
-
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_u8 (uint8_t __a, uint8x16_t __b)
-{
-  return __builtin_mve_vmaxvq_uv16qi (__a, __b);
-}
-
 __extension__ extern __inline mve_pred16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmpneq_n_u8 (uint8x16_t __a, uint8_t __b)
@@ -2433,13 +2375,6 @@ __arm_vaddvaq_u8 (uint32_t __a, uint8x16_t __b)
   return __builtin_mve_vaddvaq_uv16qi (__a, __b);
 }
 
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminavq_s8 (uint8_t __a, int8x16_t __b)
-{
-  return __builtin_mve_vminavq_sv16qi (__a, __b);
-}
-
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminaq_s8 (uint8x16_t __a, int8x16_t __b)
@@ -2447,13 +2382,6 @@ __arm_vminaq_s8 (uint8x16_t __a, int8x16_t __b)
   return __builtin_mve_vminaq_sv16qi (__a, __b);
 }
 
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxavq_s8 (uint8_t __a, int8x16_t __b)
-{
-  return __builtin_mve_vmaxavq_sv16qi (__a, __b);
-}
-
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxaq_s8 (uint8x16_t __a, int8x16_t __b)
@@ -2608,20 +2536,6 @@ __arm_vmladavq_s8 (int8x16_t __a, int8x16_t __b)
   return __builtin_mve_vmladavq_sv16qi (__a, __b);
 }
 
-__extension__ extern __inline int8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_s8 (int8_t __a, int8x16_t __b)
-{
-  return __builtin_mve_vminvq_sv16qi (__a, __b);
-}
-
-__extension__ extern __inline int8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_s8 (int8_t __a, int8x16_t __b)
-{
-  return __builtin_mve_vmaxvq_sv16qi (__a, __b);
-}
-
 __extension__ extern __inline int8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vhcaddq_rot90_s8 (int8x16_t __a, int8x16_t __b)
@@ -2699,20 +2613,6 @@ __arm_vmladavq_u16 (uint16x8_t __a, uint16x8_t __b)
   return __builtin_mve_vmladavq_uv8hi (__a, __b);
 }
 
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_u16 (uint16_t __a, uint16x8_t __b)
-{
-  return __builtin_mve_vminvq_uv8hi (__a, __b);
-}
-
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_u16 (uint16_t __a, uint16x8_t __b)
-{
-  return __builtin_mve_vmaxvq_uv8hi (__a, __b);
-}
-
 __extension__ extern __inline mve_pred16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmpneq_n_u16 (uint16x8_t __a, uint16_t __b)
@@ -2799,13 +2699,6 @@ __arm_vaddvaq_u16 (uint32_t __a, uint16x8_t __b)
   return __builtin_mve_vaddvaq_uv8hi (__a, __b);
 }
 
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminavq_s16 (uint16_t __a, int16x8_t __b)
-{
-  return __builtin_mve_vminavq_sv8hi (__a, __b);
-}
-
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminaq_s16 (uint16x8_t __a, int16x8_t __b)
@@ -2813,13 +2706,6 @@ __arm_vminaq_s16 (uint16x8_t __a, int16x8_t __b)
   return __builtin_mve_vminaq_sv8hi (__a, __b);
 }
 
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxavq_s16 (uint16_t __a, int16x8_t __b)
-{
-  return __builtin_mve_vmaxavq_sv8hi (__a, __b);
-}
-
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxaq_s16 (uint16x8_t __a, int16x8_t __b)
@@ -2974,20 +2860,6 @@ __arm_vmladavq_s16 (int16x8_t __a, int16x8_t __b)
   return __builtin_mve_vmladavq_sv8hi (__a, __b);
 }
 
-__extension__ extern __inline int16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_s16 (int16_t __a, int16x8_t __b)
-{
-  return __builtin_mve_vminvq_sv8hi (__a, __b);
-}
-
-__extension__ extern __inline int16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_s16 (int16_t __a, int16x8_t __b)
-{
-  return __builtin_mve_vmaxvq_sv8hi (__a, __b);
-}
-
 __extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vhcaddq_rot90_s16 (int16x8_t __a, int16x8_t __b)
@@ -3065,20 +2937,6 @@ __arm_vmladavq_u32 (uint32x4_t __a, uint32x4_t __b)
   return __builtin_mve_vmladavq_uv4si (__a, __b);
 }
 
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_u32 (uint32_t __a, uint32x4_t __b)
-{
-  return __builtin_mve_vminvq_uv4si (__a, __b);
-}
-
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_u32 (uint32_t __a, uint32x4_t __b)
-{
-  return __builtin_mve_vmaxvq_uv4si (__a, __b);
-}
-
 __extension__ extern __inline mve_pred16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmpneq_n_u32 (uint32x4_t __a, uint32_t __b)
@@ -3165,13 +3023,6 @@ __arm_vaddvaq_u32 (uint32_t __a, uint32x4_t __b)
   return __builtin_mve_vaddvaq_uv4si (__a, __b);
 }
 
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminavq_s32 (uint32_t __a, int32x4_t __b)
-{
-  return __builtin_mve_vminavq_sv4si (__a, __b);
-}
-
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminaq_s32 (uint32x4_t __a, int32x4_t __b)
@@ -3179,13 +3030,6 @@ __arm_vminaq_s32 (uint32x4_t __a, int32x4_t __b)
   return __builtin_mve_vminaq_sv4si (__a, __b);
 }
 
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxavq_s32 (uint32_t __a, int32x4_t __b)
-{
-  return __builtin_mve_vmaxavq_sv4si (__a, __b);
-}
-
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxaq_s32 (uint32x4_t __a, int32x4_t __b)
@@ -3340,20 +3184,6 @@ __arm_vmladavq_s32 (int32x4_t __a, int32x4_t __b)
   return __builtin_mve_vmladavq_sv4si (__a, __b);
 }
 
-__extension__ extern __inline int32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_s32 (int32_t __a, int32x4_t __b)
-{
-  return __builtin_mve_vminvq_sv4si (__a, __b);
-}
-
-__extension__ extern __inline int32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_s32 (int32_t __a, int32x4_t __b)
-{
-  return __builtin_mve_vmaxvq_sv4si (__a, __b);
-}
-
 __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vhcaddq_rot90_s32 (int32x4_t __a, int32x4_t __b)
@@ -3856,20 +3686,6 @@ __arm_vmladavaq_u8 (uint32_t __a, uint8x16_t __b, uint8x16_t __c)
   return __builtin_mve_vmladavaq_uv16qi (__a, __b, __c);
 }
 
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_p_u8 (uint8_t __a, uint8x16_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminvq_p_uv16qi (__a, __b, __p);
-}
-
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_p_u8 (uint8_t __a, uint8x16_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxvq_p_uv16qi (__a, __b, __p);
-}
-
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vdupq_m_n_u8 (uint8x16_t __inactive, uint8_t __a, mve_pred16_t __p)
@@ -3954,13 +3770,6 @@ __arm_vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm)
   return __builtin_mve_vsliq_n_uv16qi (__a, __b, __imm);
 }
 
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminavq_p_s8 (uint8_t __a, int8x16_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminavq_p_sv16qi (__a, __b, __p);
-}
-
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminaq_m_s8 (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
@@ -3968,13 +3777,6 @@ __arm_vminaq_m_s8 (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
   return __builtin_mve_vminaq_m_sv16qi (__a, __b, __p);
 }
 
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxavq_p_s8 (uint8_t __a, int8x16_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxavq_p_sv16qi (__a, __b, __p);
-}
-
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxaq_m_s8 (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
@@ -4108,20 +3910,6 @@ __arm_vmladavq_p_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
   return __builtin_mve_vmladavq_p_sv16qi (__a, __b, __p);
 }
 
-__extension__ extern __inline int8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_p_s8 (int8_t __a, int8x16_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminvq_p_sv16qi (__a, __b, __p);
-}
-
-__extension__ extern __inline int8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_p_s8 (int8_t __a, int8x16_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxvq_p_sv16qi (__a, __b, __p);
-}
-
 __extension__ extern __inline int8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vdupq_m_n_s8 (int8x16_t __inactive, int8_t __a, mve_pred16_t __p)
@@ -4332,20 +4120,6 @@ __arm_vmladavaq_u16 (uint32_t __a, uint16x8_t __b, uint16x8_t __c)
   return __builtin_mve_vmladavaq_uv8hi (__a, __b, __c);
 }
 
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_p_u16 (uint16_t __a, uint16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminvq_p_uv8hi (__a, __b, __p);
-}
-
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_p_u16 (uint16_t __a, uint16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxvq_p_uv8hi (__a, __b, __p);
-}
-
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vdupq_m_n_u16 (uint16x8_t __inactive, uint16_t __a, mve_pred16_t __p)
@@ -4430,13 +4204,6 @@ __arm_vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm)
   return __builtin_mve_vsliq_n_uv8hi (__a, __b, __imm);
 }
 
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminavq_p_s16 (uint16_t __a, int16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminavq_p_sv8hi (__a, __b, __p);
-}
-
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminaq_m_s16 (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
@@ -4444,13 +4211,6 @@ __arm_vminaq_m_s16 (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
   return __builtin_mve_vminaq_m_sv8hi (__a, __b, __p);
 }
 
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxavq_p_s16 (uint16_t __a, int16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxavq_p_sv8hi (__a, __b, __p);
-}
-
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxaq_m_s16 (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
@@ -4584,20 +4344,6 @@ __arm_vmladavq_p_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
   return __builtin_mve_vmladavq_p_sv8hi (__a, __b, __p);
 }
 
-__extension__ extern __inline int16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_p_s16 (int16_t __a, int16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminvq_p_sv8hi (__a, __b, __p);
-}
-
-__extension__ extern __inline int16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_p_s16 (int16_t __a, int16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxvq_p_sv8hi (__a, __b, __p);
-}
-
 __extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vdupq_m_n_s16 (int16x8_t __inactive, int16_t __a, mve_pred16_t __p)
@@ -4808,20 +4554,6 @@ __arm_vmladavaq_u32 (uint32_t __a, uint32x4_t __b, uint32x4_t __c)
   return __builtin_mve_vmladavaq_uv4si (__a, __b, __c);
 }
 
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_p_u32 (uint32_t __a, uint32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminvq_p_uv4si (__a, __b, __p);
-}
-
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_p_u32 (uint32_t __a, uint32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxvq_p_uv4si (__a, __b, __p);
-}
-
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vdupq_m_n_u32 (uint32x4_t __inactive, uint32_t __a, mve_pred16_t __p)
@@ -4906,13 +4638,6 @@ __arm_vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm)
   return __builtin_mve_vsliq_n_uv4si (__a, __b, __imm);
 }
 
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminavq_p_s32 (uint32_t __a, int32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminavq_p_sv4si (__a, __b, __p);
-}
-
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminaq_m_s32 (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
@@ -4920,13 +4645,6 @@ __arm_vminaq_m_s32 (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
   return __builtin_mve_vminaq_m_sv4si (__a, __b, __p);
 }
 
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxavq_p_s32 (uint32_t __a, int32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxavq_p_sv4si (__a, __b, __p);
-}
-
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxaq_m_s32 (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
@@ -5060,20 +4778,6 @@ __arm_vmladavq_p_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
   return __builtin_mve_vmladavq_p_sv4si (__a, __b, __p);
 }
 
-__extension__ extern __inline int32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_p_s32 (int32_t __a, int32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminvq_p_sv4si (__a, __b, __p);
-}
-
-__extension__ extern __inline int32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_p_s32 (int32_t __a, int32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxvq_p_sv4si (__a, __b, __p);
-}
-
 __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vdupq_m_n_s32 (int32x4_t __inactive, int32_t __a, mve_pred16_t __p)
@@ -12772,20 +12476,6 @@ __arm_vmladavq (uint8x16_t __a, uint8x16_t __b)
  return __arm_vmladavq_u8 (__a, __b);
 }
 
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq (uint8_t __a, uint8x16_t __b)
-{
- return __arm_vminvq_u8 (__a, __b);
-}
-
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq (uint8_t __a, uint8x16_t __b)
-{
- return __arm_vmaxvq_u8 (__a, __b);
-}
-
 __extension__ extern __inline mve_pred16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmpneq (uint8x16_t __a, uint8_t __b)
@@ -12870,13 +12560,6 @@ __arm_vaddvaq (uint32_t __a, uint8x16_t __b)
  return __arm_vaddvaq_u8 (__a, __b);
 }
 
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminavq (uint8_t __a, int8x16_t __b)
-{
- return __arm_vminavq_s8 (__a, __b);
-}
-
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminaq (uint8x16_t __a, int8x16_t __b)
@@ -12884,13 +12567,6 @@ __arm_vminaq (uint8x16_t __a, int8x16_t __b)
  return __arm_vminaq_s8 (__a, __b);
 }
 
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxavq (uint8_t __a, int8x16_t __b)
-{
- return __arm_vmaxavq_s8 (__a, __b);
-}
-
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxaq (uint8x16_t __a, int8x16_t __b)
@@ -13045,20 +12721,6 @@ __arm_vmladavq (int8x16_t __a, int8x16_t __b)
  return __arm_vmladavq_s8 (__a, __b);
 }
 
-__extension__ extern __inline int8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq (int8_t __a, int8x16_t __b)
-{
- return __arm_vminvq_s8 (__a, __b);
-}
-
-__extension__ extern __inline int8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq (int8_t __a, int8x16_t __b)
-{
- return __arm_vmaxvq_s8 (__a, __b);
-}
-
 __extension__ extern __inline int8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vhcaddq_rot90 (int8x16_t __a, int8x16_t __b)
@@ -13136,20 +12798,6 @@ __arm_vmladavq (uint16x8_t __a, uint16x8_t __b)
  return __arm_vmladavq_u16 (__a, __b);
 }
 
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq (uint16_t __a, uint16x8_t __b)
-{
- return __arm_vminvq_u16 (__a, __b);
-}
-
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq (uint16_t __a, uint16x8_t __b)
-{
- return __arm_vmaxvq_u16 (__a, __b);
-}
-
 __extension__ extern __inline mve_pred16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmpneq (uint16x8_t __a, uint16_t __b)
@@ -13234,13 +12882,6 @@ __arm_vaddvaq (uint32_t __a, uint16x8_t __b)
  return __arm_vaddvaq_u16 (__a, __b);
 }
 
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminavq (uint16_t __a, int16x8_t __b)
-{
- return __arm_vminavq_s16 (__a, __b);
-}
-
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminaq (uint16x8_t __a, int16x8_t __b)
@@ -13248,13 +12889,6 @@ __arm_vminaq (uint16x8_t __a, int16x8_t __b)
  return __arm_vminaq_s16 (__a, __b);
 }
 
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxavq (uint16_t __a, int16x8_t __b)
-{
- return __arm_vmaxavq_s16 (__a, __b);
-}
-
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxaq (uint16x8_t __a, int16x8_t __b)
@@ -13409,20 +13043,6 @@ __arm_vmladavq (int16x8_t __a, int16x8_t __b)
  return __arm_vmladavq_s16 (__a, __b);
 }
 
-__extension__ extern __inline int16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq (int16_t __a, int16x8_t __b)
-{
- return __arm_vminvq_s16 (__a, __b);
-}
-
-__extension__ extern __inline int16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq (int16_t __a, int16x8_t __b)
-{
- return __arm_vmaxvq_s16 (__a, __b);
-}
-
 __extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vhcaddq_rot90 (int16x8_t __a, int16x8_t __b)
@@ -13500,20 +13120,6 @@ __arm_vmladavq (uint32x4_t __a, uint32x4_t __b)
  return __arm_vmladavq_u32 (__a, __b);
 }
 
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq (uint32_t __a, uint32x4_t __b)
-{
- return __arm_vminvq_u32 (__a, __b);
-}
-
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq (uint32_t __a, uint32x4_t __b)
-{
- return __arm_vmaxvq_u32 (__a, __b);
-}
-
 __extension__ extern __inline mve_pred16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmpneq (uint32x4_t __a, uint32_t __b)
@@ -13598,13 +13204,6 @@ __arm_vaddvaq (uint32_t __a, uint32x4_t __b)
  return __arm_vaddvaq_u32 (__a, __b);
 }
 
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminavq (uint32_t __a, int32x4_t __b)
-{
- return __arm_vminavq_s32 (__a, __b);
-}
-
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminaq (uint32x4_t __a, int32x4_t __b)
@@ -13612,13 +13211,6 @@ __arm_vminaq (uint32x4_t __a, int32x4_t __b)
  return __arm_vminaq_s32 (__a, __b);
 }
 
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxavq (uint32_t __a, int32x4_t __b)
-{
- return __arm_vmaxavq_s32 (__a, __b);
-}
-
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxaq (uint32x4_t __a, int32x4_t __b)
@@ -13773,20 +13365,6 @@ __arm_vmladavq (int32x4_t __a, int32x4_t __b)
  return __arm_vmladavq_s32 (__a, __b);
 }
 
-__extension__ extern __inline int32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq (int32_t __a, int32x4_t __b)
-{
- return __arm_vminvq_s32 (__a, __b);
-}
-
-__extension__ extern __inline int32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq (int32_t __a, int32x4_t __b)
-{
- return __arm_vmaxvq_s32 (__a, __b);
-}
-
 __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vhcaddq_rot90 (int32x4_t __a, int32x4_t __b)
@@ -14249,20 +13827,6 @@ __arm_vmladavaq (uint32_t __a, uint8x16_t __b, uint8x16_t __c)
  return __arm_vmladavaq_u8 (__a, __b, __c);
 }
 
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_p (uint8_t __a, uint8x16_t __b, mve_pred16_t __p)
-{
- return __arm_vminvq_p_u8 (__a, __b, __p);
-}
-
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_p (uint8_t __a, uint8x16_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxvq_p_u8 (__a, __b, __p);
-}
-
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vdupq_m (uint8x16_t __inactive, uint8_t __a, mve_pred16_t __p)
@@ -14347,13 +13911,6 @@ __arm_vsliq (uint8x16_t __a, uint8x16_t __b, const int __imm)
  return __arm_vsliq_n_u8 (__a, __b, __imm);
 }
 
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminavq_p (uint8_t __a, int8x16_t __b, mve_pred16_t __p)
-{
- return __arm_vminavq_p_s8 (__a, __b, __p);
-}
-
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminaq_m (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
@@ -14361,13 +13918,6 @@ __arm_vminaq_m (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
  return __arm_vminaq_m_s8 (__a, __b, __p);
 }
 
-__extension__ extern __inline uint8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxavq_p (uint8_t __a, int8x16_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxavq_p_s8 (__a, __b, __p);
-}
-
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxaq_m (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
@@ -14501,20 +14051,6 @@ __arm_vmladavq_p (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
  return __arm_vmladavq_p_s8 (__a, __b, __p);
 }
 
-__extension__ extern __inline int8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_p (int8_t __a, int8x16_t __b, mve_pred16_t __p)
-{
- return __arm_vminvq_p_s8 (__a, __b, __p);
-}
-
-__extension__ extern __inline int8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_p (int8_t __a, int8x16_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxvq_p_s8 (__a, __b, __p);
-}
-
 __extension__ extern __inline int8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vdupq_m (int8x16_t __inactive, int8_t __a, mve_pred16_t __p)
@@ -14725,20 +14261,6 @@ __arm_vmladavaq (uint32_t __a, uint16x8_t __b, uint16x8_t __c)
  return __arm_vmladavaq_u16 (__a, __b, __c);
 }
 
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_p (uint16_t __a, uint16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vminvq_p_u16 (__a, __b, __p);
-}
-
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_p (uint16_t __a, uint16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxvq_p_u16 (__a, __b, __p);
-}
-
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vdupq_m (uint16x8_t __inactive, uint16_t __a, mve_pred16_t __p)
@@ -14823,13 +14345,6 @@ __arm_vsliq (uint16x8_t __a, uint16x8_t __b, const int __imm)
  return __arm_vsliq_n_u16 (__a, __b, __imm);
 }
 
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminavq_p (uint16_t __a, int16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vminavq_p_s16 (__a, __b, __p);
-}
-
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminaq_m (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
@@ -14837,13 +14352,6 @@ __arm_vminaq_m (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
  return __arm_vminaq_m_s16 (__a, __b, __p);
 }
 
-__extension__ extern __inline uint16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxavq_p (uint16_t __a, int16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxavq_p_s16 (__a, __b, __p);
-}
-
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxaq_m (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
@@ -14977,20 +14485,6 @@ __arm_vmladavq_p (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
  return __arm_vmladavq_p_s16 (__a, __b, __p);
 }
 
-__extension__ extern __inline int16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_p (int16_t __a, int16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vminvq_p_s16 (__a, __b, __p);
-}
-
-__extension__ extern __inline int16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_p (int16_t __a, int16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxvq_p_s16 (__a, __b, __p);
-}
-
 __extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vdupq_m (int16x8_t __inactive, int16_t __a, mve_pred16_t __p)
@@ -15201,20 +14695,6 @@ __arm_vmladavaq (uint32_t __a, uint32x4_t __b, uint32x4_t __c)
  return __arm_vmladavaq_u32 (__a, __b, __c);
 }
 
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_p (uint32_t __a, uint32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vminvq_p_u32 (__a, __b, __p);
-}
-
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_p (uint32_t __a, uint32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxvq_p_u32 (__a, __b, __p);
-}
-
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vdupq_m (uint32x4_t __inactive, uint32_t __a, mve_pred16_t __p)
@@ -15299,13 +14779,6 @@ __arm_vsliq (uint32x4_t __a, uint32x4_t __b, const int __imm)
  return __arm_vsliq_n_u32 (__a, __b, __imm);
 }
 
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminavq_p (uint32_t __a, int32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vminavq_p_s32 (__a, __b, __p);
-}
-
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminaq_m (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
@@ -15313,13 +14786,6 @@ __arm_vminaq_m (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
  return __arm_vminaq_m_s32 (__a, __b, __p);
 }
 
-__extension__ extern __inline uint32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxavq_p (uint32_t __a, int32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxavq_p_s32 (__a, __b, __p);
-}
-
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxaq_m (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
@@ -15453,20 +14919,6 @@ __arm_vmladavq_p (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
  return __arm_vmladavq_p_s32 (__a, __b, __p);
 }
 
-__extension__ extern __inline int32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminvq_p (int32_t __a, int32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vminvq_p_s32 (__a, __b, __p);
-}
-
-__extension__ extern __inline int32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxvq_p (int32_t __a, int32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxvq_p_s32 (__a, __b, __p);
-}
-
 __extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vdupq_m (int32x4_t __inactive, int32_t __a, mve_pred16_t __p)
@@ -25181,74 +24633,6 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmphiq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmphiq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
 
-#define __arm_vmaxavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vmaxavq_s8 (__p0, __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vmaxavq_s16 (__p0, __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vmaxavq_s32 (__p0, __ARM_mve_coerce(__p1, int32x4_t)));})
-
-#define __arm_vmaxavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vmaxavq_p_s8 (__p0, __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vmaxavq_p_s16 (__p0, __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vmaxavq_p_s32 (__p0, __ARM_mve_coerce(__p1, int32x4_t), p2));})
-
-#define __arm_vmaxvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vmaxvq_s8 (__p0, __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vmaxvq_s16 (__p0, __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vmaxvq_s32 (__p0, __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vmaxvq_u8 (__p0, __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vmaxvq_u16 (__p0, __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vmaxvq_u32 (__p0,__ARM_mve_coerce(__p1, uint32x4_t)));})
-
-#define __arm_vmaxvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vmaxvq_p_s8 (__p0, __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vmaxvq_p_s16 (__p0, __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vmaxvq_p_s32 (__p0, __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vmaxvq_p_u8 (__p0, __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vmaxvq_p_u16 (__p0, __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vmaxvq_p_u32 (__p0, __ARM_mve_coerce(__p1, uint32x4_t), p2));})
-
-#define __arm_vminavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vminavq_s8 (__p0, __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vminavq_s16 (__p0, __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vminavq_s32 (__p0, __ARM_mve_coerce(__p1, int32x4_t)));})
-
-#define __arm_vminavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vminavq_p_s8 (__p0, __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vminavq_p_s16 (__p0, __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vminavq_p_s32 (__p0, __ARM_mve_coerce(__p1, int32x4_t), p2));})
-
-#define __arm_vminvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vminvq_s8 (__p0, __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vminvq_s16 (__p0, __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vminvq_s32 (__p0, __ARM_mve_coerce(__p1, int32x4_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vminvq_u8 (__p0, __ARM_mve_coerce(__p1, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vminvq_u16 (__p0, __ARM_mve_coerce(__p1, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vminvq_u32 (__p0, __ARM_mve_coerce(__p1, uint32x4_t)));})
-
-#define __arm_vminvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vminvq_p_s8 (__p0, __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vminvq_p_s16 (__p0, __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vminvq_p_s32 (__p0, __ARM_mve_coerce(__p1, int32x4_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vminvq_p_u8 (__p0, __ARM_mve_coerce(__p1, uint8x16_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vminvq_p_u16 (__p0, __ARM_mve_coerce(__p1, uint16x8_t), p2), \
-  int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vminvq_p_u32 (__p0, __ARM_mve_coerce(__p1, uint32x4_t), p2));})
-
 #define __arm_vmladavaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
-- 
2.34.1

[PATCH 06/16] arm: add smax/smin expanders for v*hf

[Christophe Lyon]

This patch adds the missing expanders for smax/smin for v*hf modes.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/vec-common.md (smin<mode>3): New.
	(smax<mode>3): New.
---
 gcc/config/arm/vec-common.md | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index b5fc86fdf28..1f9b7992da4 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -116,6 +116,13 @@ (define_expand "smin<mode>3"
    "ARM_HAVE_<MODE>_ARITH"
 )
 
+(define_expand "smin<mode>3"
+  [(set (match_operand:VH 0 "s_register_operand")
+	(smin:VH (match_operand:VH 1 "s_register_operand")
+		 (match_operand:VH 2 "s_register_operand")))]
+   "ARM_HAVE_<MODE>_ARITH"
+)
+
 (define_expand "umin<mode>3"
   [(set (match_operand:VINTW 0 "s_register_operand")
 	(umin:VINTW (match_operand:VINTW 1 "s_register_operand")
@@ -130,6 +137,13 @@ (define_expand "smax<mode>3"
    "ARM_HAVE_<MODE>_ARITH"
 )
 
+(define_expand "smax<mode>3"
+  [(set (match_operand:VH 0 "s_register_operand")
+	(smax:VH (match_operand:VH 1 "s_register_operand")
+		 (match_operand:VH 2 "s_register_operand")))]
+   "ARM_HAVE_<MODE>_ARITH"
+)
+
 (define_expand "umax<mode>3"
   [(set (match_operand:VINTW 0 "s_register_operand")
 	(umax:VINTW (match_operand:VINTW 1 "s_register_operand")
-- 
2.34.1

[PATCH 07/16] arm: [MVE intrinsics] factorize vmaxnmq vminnmq

[Christophe Lyon]

Factorize vmaxnmq and vminnmq so that they use the same pattern.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (MAX_MIN_F): New.
	(MVE_FP_M_BINARY): Add VMAXNMQ_M_F, VMINNMQ_M_F.
	(mve_insn): Add vmaxnm, vminnm.
	(max_min_f_str): New.
	* config/arm/mve.md (mve_vmaxnmq_f<mode>, mve_vminnmq_f<mode>):
	Merge into ...
	(@mve_<max_min_f_str>q_f<mode>): ... this.
	(mve_vmaxnmq_m_f<mode>, mve_vminnmq_m_f<mode>): Merge into ...
	(@mve_<mve_insn>q_m_f<mode>): ... this.
---
 gcc/config/arm/iterators.md | 10 ++++++
 gcc/config/arm/mve.md       | 63 ++++++-------------------------------
 2 files changed, 19 insertions(+), 54 deletions(-)

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 5bb7e2be7c8..397ac32720d 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -333,6 +333,9 @@ (define_code_iterator SSPLUSMINUS [ss_plus ss_minus])
 ;; Max/Min iterator, to factorize MVE patterns
 (define_code_iterator MAX_MIN_SU [smax umax smin umin])
 
+;; Floating-point Max/Min iterator, to factorize MVE patterns
+(define_code_iterator MAX_MIN_F [smax smin])
+
 ;; MVE integer unary operations.
 (define_int_iterator MVE_INT_M_UNARY [
 		     VABSQ_M_S
@@ -547,6 +550,8 @@ (define_int_iterator MVE_SHRN_M_N [
 (define_int_iterator MVE_FP_M_BINARY   [
 		     VABDQ_M_F
 		     VADDQ_M_F
+		     VMAXNMQ_M_F
+		     VMINNMQ_M_F
 		     VMULQ_M_F
 		     VSUBQ_M_F
 		     ])
@@ -643,11 +648,13 @@ (define_int_attr mve_insn [
 		 (VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub")
 		 (VMAXAVQ_P_S "vmaxav")
 		 (VMAXAVQ_S "vmaxav")
+		 (VMAXNMQ_M_F "vmaxnm")
 		 (VMAXQ_M_S "vmax") (VMAXQ_M_U "vmax")
 		 (VMAXVQ_P_S "vmaxv") (VMAXVQ_P_U "vmaxv")
 		 (VMAXVQ_S "vmaxv") (VMAXVQ_U "vmaxv")
 		 (VMINAVQ_P_S "vminav")
 		 (VMINAVQ_S "vminav")
+		 (VMINNMQ_M_F "vminnm")
 		 (VMINQ_M_S "vmin") (VMINQ_M_U "vmin")
 		 (VMINVQ_P_S "vminv") (VMINVQ_P_U "vminv")
 		 (VMINVQ_S "vminv") (VMINVQ_U "vminv")
@@ -1516,6 +1523,9 @@ (define_code_attr max_min_supf [
 		 (smin "s") (umin "u")
 		 ])
 
+;; Floating-point max/min for MVE
+(define_code_attr max_min_f_str [(smax "vmaxnm") (smin "vminnm")])
+
 ;;----------------------------------------------------------------------------
 ;; Int attributes
 ;;----------------------------------------------------------------------------
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 715e85c9998..d2863b316e0 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1455,16 +1455,17 @@ (define_insn "mve_vmaxnmavq_f<mode>"
 ])
 
 ;;
-;; [vmaxnmq_f])
+;; [vmaxnmq_f]
+;; [vminnmq_f]
 ;;
-(define_insn "mve_vmaxnmq_f<mode>"
+(define_insn "@mve_<max_min_f_str>q_f<mode>"
   [
    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
-	(smax:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
-		    (match_operand:MVE_0 2 "s_register_operand" "w")))
+	(MAX_MIN_F:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
+			 (match_operand:MVE_0 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vmaxnm.f%#<V_sz_elem>	%q0, %q1, %q2"
+  "<max_min_f_str>.f%#<V_sz_elem>	%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1513,20 +1514,6 @@ (define_insn "mve_vminnmavq_f<mode>"
   [(set_attr "type" "mve_move")
 ])
 
-;;
-;; [vminnmq_f])
-;;
-(define_insn "mve_vminnmq_f<mode>"
-  [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
-	(smin:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
-		    (match_operand:MVE_0 2 "s_register_operand" "w")))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vminnm.f%#<V_sz_elem>	%q0, %q1, %q2"
-  [(set_attr "type" "mve_move")
-])
-
 ;;
 ;; [vminnmvq_f])
 ;;
@@ -4533,8 +4520,10 @@ (define_insn "mve_vrmlsldavhaxq_p_sv4si"
 ;;
 ;; [vabdq_m_f]
 ;; [vaddq_m_f]
-;; [vsubq_m_f]
+;; [vmaxnmq_m_f]
+;; [vminnmq_m_f]
 ;; [vmulq_m_f]
+;; [vsubq_m_f]
 ;;
 (define_insn "@mve_<mve_insn>q_m_f<mode>"
   [
@@ -4844,40 +4833,6 @@ (define_insn "mve_vfmsq_m_f<mode>"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
-;;
-;; [vmaxnmq_m_f])
-;;
-(define_insn "mve_vmaxnmq_m_f<mode>"
-  [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
-	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
-		       (match_operand:MVE_0 2 "s_register_operand" "w")
-		       (match_operand:MVE_0 3 "s_register_operand" "w")
-		       (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-	 VMAXNMQ_M_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vmaxnmt.f%#<V_sz_elem>	%q0, %q2, %q3"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
-;;
-;; [vminnmq_m_f])
-;;
-(define_insn "mve_vminnmq_m_f<mode>"
-  [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
-	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
-		       (match_operand:MVE_0 2 "s_register_operand" "w")
-		       (match_operand:MVE_0 3 "s_register_operand" "w")
-		       (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-	 VMINNMQ_M_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vminnmt.f%#<V_sz_elem>	%q0, %q2, %q3"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
 ;;
 ;; [vornq_m_f])
 ;;
-- 
2.34.1

[PATCH 08/16] arm: [MVE intrinsics] rework vmaxnmq vminnmq

[Christophe Lyon]

Implement vmaxnmq and vminnmq using the new MVE builtins framework.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/arm-mve-builtins-base.cc (vmaxnmq, vminnmq): New.
	* config/arm/arm-mve-builtins-base.def (vmaxnmq, vminnmq): New.
	* config/arm/arm-mve-builtins-base.h (vmaxnmq, vminnmq): New.
	* config/arm/arm_mve.h (vminnmq): Remove.
	(vmaxnmq): Remove.
	(vmaxnmq_m): Remove.
	(vminnmq_m): Remove.
	(vminnmq_x): Remove.
	(vmaxnmq_x): Remove.
	(vminnmq_f16): Remove.
	(vmaxnmq_f16): Remove.
	(vminnmq_f32): Remove.
	(vmaxnmq_f32): Remove.
	(vmaxnmq_m_f32): Remove.
	(vmaxnmq_m_f16): Remove.
	(vminnmq_m_f32): Remove.
	(vminnmq_m_f16): Remove.
	(vminnmq_x_f16): Remove.
	(vminnmq_x_f32): Remove.
	(vmaxnmq_x_f16): Remove.
	(vmaxnmq_x_f32): Remove.
	(__arm_vminnmq_f16): Remove.
	(__arm_vmaxnmq_f16): Remove.
	(__arm_vminnmq_f32): Remove.
	(__arm_vmaxnmq_f32): Remove.
	(__arm_vmaxnmq_m_f32): Remove.
	(__arm_vmaxnmq_m_f16): Remove.
	(__arm_vminnmq_m_f32): Remove.
	(__arm_vminnmq_m_f16): Remove.
	(__arm_vminnmq_x_f16): Remove.
	(__arm_vminnmq_x_f32): Remove.
	(__arm_vmaxnmq_x_f16): Remove.
	(__arm_vmaxnmq_x_f32): Remove.
	(__arm_vminnmq): Remove.
	(__arm_vmaxnmq): Remove.
	(__arm_vmaxnmq_m): Remove.
	(__arm_vminnmq_m): Remove.
	(__arm_vminnmq_x): Remove.
	(__arm_vmaxnmq_x): Remove.
---
 gcc/config/arm/arm-mve-builtins-base.cc  |   2 +
 gcc/config/arm/arm-mve-builtins-base.def |   2 +
 gcc/config/arm/arm-mve-builtins-base.h   |   2 +
 gcc/config/arm/arm_mve.h                 | 224 -----------------------
 4 files changed, 6 insertions(+), 224 deletions(-)

diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc
index cfab3f222ed..dcbd1906563 100644
--- a/gcc/config/arm/arm-mve-builtins-base.cc
+++ b/gcc/config/arm/arm-mve-builtins-base.cc
@@ -236,9 +236,11 @@ FUNCTION_WITH_RTX_M (veorq, XOR, VEORQ)
 FUNCTION_WITH_M_N_NO_F (vhaddq, VHADDQ)
 FUNCTION_WITH_M_N_NO_F (vhsubq, VHSUBQ)
 FUNCTION_PRED_P_S (vmaxavq, VMAXAVQ)
+FUNCTION (vmaxnmq, unspec_based_mve_function_exact_insn, (UNKNOWN, UNKNOWN, SMAX, -1, -1, -1, -1, -1, VMAXNMQ_M_F, -1, -1, -1))
 FUNCTION_WITH_RTX_M_NO_F (vmaxq, SMAX, UMAX, VMAXQ)
 FUNCTION_PRED_P_S_U (vmaxvq, VMAXVQ)
 FUNCTION_PRED_P_S (vminavq, VMINAVQ)
+FUNCTION (vminnmq, unspec_based_mve_function_exact_insn, (UNKNOWN, UNKNOWN, SMIN, -1, -1, -1, -1, -1, VMINNMQ_M_F, -1, -1, -1))
 FUNCTION_WITH_RTX_M_NO_F (vminq, SMIN, UMIN, VMINQ)
 FUNCTION_PRED_P_S_U (vminvq, VMINVQ)
 FUNCTION_WITHOUT_N_NO_F (vmovnbq, VMOVNBQ)
diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def
index d06e134719e..c2155bafeb3 100644
--- a/gcc/config/arm/arm-mve-builtins-base.def
+++ b/gcc/config/arm/arm-mve-builtins-base.def
@@ -86,6 +86,8 @@ DEF_MVE_FUNCTION (vaddq, binary_opt_n, all_float, mx_or_none)
 DEF_MVE_FUNCTION (vandq, binary, all_float, mx_or_none)
 DEF_MVE_FUNCTION (vcreateq, create, all_float, none)
 DEF_MVE_FUNCTION (veorq, binary, all_float, mx_or_none)
+DEF_MVE_FUNCTION (vmaxnmq, binary, all_float, mx_or_none)
+DEF_MVE_FUNCTION (vminnmq, binary, all_float, mx_or_none)
 DEF_MVE_FUNCTION (vmulq, binary_opt_n, all_float, mx_or_none)
 DEF_MVE_FUNCTION (vnegq, unary, all_float, mx_or_none)
 DEF_MVE_FUNCTION (vorrq, binary_orrq, all_float, mx_or_none)
diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h
index 30e0f42a352..0290ee72b4c 100644
--- a/gcc/config/arm/arm-mve-builtins-base.h
+++ b/gcc/config/arm/arm-mve-builtins-base.h
@@ -34,9 +34,11 @@ extern const function_base *const veorq;
 extern const function_base *const vhaddq;
 extern const function_base *const vhsubq;
 extern const function_base *const vmaxavq;
+extern const function_base *const vmaxnmq;
 extern const function_base *const vmaxq;
 extern const function_base *const vmaxvq;
 extern const function_base *const vminavq;
+extern const function_base *const vminnmq;
 extern const function_base *const vminq;
 extern const function_base *const vminvq;
 extern const function_base *const vmovnbq;
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index dddaab74bc0..12e77eee11e 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -309,11 +309,9 @@
 #define vcvtq(__a) __arm_vcvtq(__a)
 #define vcvtq_n(__a, __imm6) __arm_vcvtq_n(__a, __imm6)
 #define vminnmvq(__a, __b) __arm_vminnmvq(__a, __b)
-#define vminnmq(__a, __b) __arm_vminnmq(__a, __b)
 #define vminnmavq(__a, __b) __arm_vminnmavq(__a, __b)
 #define vminnmaq(__a, __b) __arm_vminnmaq(__a, __b)
 #define vmaxnmvq(__a, __b) __arm_vmaxnmvq(__a, __b)
-#define vmaxnmq(__a, __b) __arm_vmaxnmq(__a, __b)
 #define vmaxnmavq(__a, __b) __arm_vmaxnmavq(__a, __b)
 #define vmaxnmaq(__a, __b) __arm_vmaxnmaq(__a, __b)
 #define vcmulq_rot90(__a, __b) __arm_vcmulq_rot90(__a, __b)
@@ -352,10 +350,6 @@
 #define vfmaq_m(__a, __b, __c, __p) __arm_vfmaq_m(__a, __b, __c, __p)
 #define vfmasq_m(__a, __b, __c, __p) __arm_vfmasq_m(__a, __b, __c, __p)
 #define vfmsq_m(__a, __b, __c, __p) __arm_vfmsq_m(__a, __b, __c, __p)
-#define vmaxnmq_m(__inactive, __a, __b, __p) __arm_vmaxnmq_m(__inactive, __a, __b, __p)
-#define vminnmq_m(__inactive, __a, __b, __p) __arm_vminnmq_m(__inactive, __a, __b, __p)
-#define vminnmq_x(__a, __b, __p) __arm_vminnmq_x(__a, __b, __p)
-#define vmaxnmq_x(__a, __b, __p) __arm_vmaxnmq_x(__a, __b, __p)
 #define vcmulq_x(__a, __b, __p) __arm_vcmulq_x(__a, __b, __p)
 #define vcmulq_rot90_x(__a, __b, __p) __arm_vcmulq_rot90_x(__a, __b, __p)
 #define vcmulq_rot180_x(__a, __b, __p) __arm_vcmulq_rot180_x(__a, __b, __p)
@@ -634,11 +628,9 @@
 #define vmlaldavxq_s16(__a, __b) __arm_vmlaldavxq_s16(__a, __b)
 #define vmlaldavq_s16(__a, __b) __arm_vmlaldavq_s16(__a, __b)
 #define vminnmvq_f16(__a, __b) __arm_vminnmvq_f16(__a, __b)
-#define vminnmq_f16(__a, __b) __arm_vminnmq_f16(__a, __b)
 #define vminnmavq_f16(__a, __b) __arm_vminnmavq_f16(__a, __b)
 #define vminnmaq_f16(__a, __b) __arm_vminnmaq_f16(__a, __b)
 #define vmaxnmvq_f16(__a, __b) __arm_vmaxnmvq_f16(__a, __b)
-#define vmaxnmq_f16(__a, __b) __arm_vmaxnmq_f16(__a, __b)
 #define vmaxnmavq_f16(__a, __b) __arm_vmaxnmavq_f16(__a, __b)
 #define vmaxnmaq_f16(__a, __b) __arm_vmaxnmaq_f16(__a, __b)
 #define vcmulq_rot90_f16(__a, __b) __arm_vcmulq_rot90_f16(__a, __b)
@@ -675,11 +667,9 @@
 #define vmlaldavxq_s32(__a, __b) __arm_vmlaldavxq_s32(__a, __b)
 #define vmlaldavq_s32(__a, __b) __arm_vmlaldavq_s32(__a, __b)
 #define vminnmvq_f32(__a, __b) __arm_vminnmvq_f32(__a, __b)
-#define vminnmq_f32(__a, __b) __arm_vminnmq_f32(__a, __b)
 #define vminnmavq_f32(__a, __b) __arm_vminnmavq_f32(__a, __b)
 #define vminnmaq_f32(__a, __b) __arm_vminnmaq_f32(__a, __b)
 #define vmaxnmvq_f32(__a, __b) __arm_vmaxnmvq_f32(__a, __b)
-#define vmaxnmq_f32(__a, __b) __arm_vmaxnmq_f32(__a, __b)
 #define vmaxnmavq_f32(__a, __b) __arm_vmaxnmavq_f32(__a, __b)
 #define vmaxnmaq_f32(__a, __b) __arm_vmaxnmaq_f32(__a, __b)
 #define vcmulq_rot90_f32(__a, __b) __arm_vcmulq_rot90_f32(__a, __b)
@@ -1243,10 +1233,6 @@
 #define vfmasq_m_n_f16(__a, __b, __c, __p) __arm_vfmasq_m_n_f16(__a, __b, __c, __p)
 #define vfmsq_m_f32(__a, __b, __c, __p) __arm_vfmsq_m_f32(__a, __b, __c, __p)
 #define vfmsq_m_f16(__a, __b, __c, __p) __arm_vfmsq_m_f16(__a, __b, __c, __p)
-#define vmaxnmq_m_f32(__inactive, __a, __b, __p) __arm_vmaxnmq_m_f32(__inactive, __a, __b, __p)
-#define vmaxnmq_m_f16(__inactive, __a, __b, __p) __arm_vmaxnmq_m_f16(__inactive, __a, __b, __p)
-#define vminnmq_m_f32(__inactive, __a, __b, __p) __arm_vminnmq_m_f32(__inactive, __a, __b, __p)
-#define vminnmq_m_f16(__inactive, __a, __b, __p) __arm_vminnmq_m_f16(__inactive, __a, __b, __p)
 #define vornq_m_f32(__inactive, __a, __b, __p) __arm_vornq_m_f32(__inactive, __a, __b, __p)
 #define vornq_m_f16(__inactive, __a, __b, __p) __arm_vornq_m_f16(__inactive, __a, __b, __p)
 #define vstrbq_s8( __addr, __value) __arm_vstrbq_s8( __addr, __value)
@@ -1637,10 +1623,6 @@
 #define vrev64q_x_u32(__a, __p) __arm_vrev64q_x_u32(__a, __p)
 #define vdupq_x_n_f16(__a, __p) __arm_vdupq_x_n_f16(__a, __p)
 #define vdupq_x_n_f32(__a, __p) __arm_vdupq_x_n_f32(__a, __p)
-#define vminnmq_x_f16(__a, __b, __p) __arm_vminnmq_x_f16(__a, __b, __p)
-#define vminnmq_x_f32(__a, __b, __p) __arm_vminnmq_x_f32(__a, __b, __p)
-#define vmaxnmq_x_f16(__a, __b, __p) __arm_vmaxnmq_x_f16(__a, __b, __p)
-#define vmaxnmq_x_f32(__a, __b, __p) __arm_vmaxnmq_x_f32(__a, __b, __p)
 #define vcaddq_rot90_x_f16(__a, __b, __p) __arm_vcaddq_rot90_x_f16(__a, __b, __p)
 #define vcaddq_rot90_x_f32(__a, __b, __p) __arm_vcaddq_rot90_x_f32(__a, __b, __p)
 #define vcaddq_rot270_x_f16(__a, __b, __p) __arm_vcaddq_rot270_x_f16(__a, __b, __p)
@@ -10027,13 +10009,6 @@ __arm_vminnmvq_f16 (float16_t __a, float16x8_t __b)
   return __builtin_mve_vminnmvq_fv8hf (__a, __b);
 }
 
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq_f16 (float16x8_t __a, float16x8_t __b)
-{
-  return __builtin_mve_vminnmq_fv8hf (__a, __b);
-}
-
 __extension__ extern __inline float16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminnmavq_f16 (float16_t __a, float16x8_t __b)
@@ -10055,13 +10030,6 @@ __arm_vmaxnmvq_f16 (float16_t __a, float16x8_t __b)
   return __builtin_mve_vmaxnmvq_fv8hf (__a, __b);
 }
 
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq_f16 (float16x8_t __a, float16x8_t __b)
-{
-  return __builtin_mve_vmaxnmq_fv8hf (__a, __b);
-}
-
 __extension__ extern __inline float16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxnmavq_f16 (float16_t __a, float16x8_t __b)
@@ -10223,13 +10191,6 @@ __arm_vminnmvq_f32 (float32_t __a, float32x4_t __b)
   return __builtin_mve_vminnmvq_fv4sf (__a, __b);
 }
 
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq_f32 (float32x4_t __a, float32x4_t __b)
-{
-  return __builtin_mve_vminnmq_fv4sf (__a, __b);
-}
-
 __extension__ extern __inline float32_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminnmavq_f32 (float32_t __a, float32x4_t __b)
@@ -10251,13 +10212,6 @@ __arm_vmaxnmvq_f32 (float32_t __a, float32x4_t __b)
   return __builtin_mve_vmaxnmvq_fv4sf (__a, __b);
 }
 
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq_f32 (float32x4_t __a, float32x4_t __b)
-{
-  return __builtin_mve_vmaxnmq_fv4sf (__a, __b);
-}
-
 __extension__ extern __inline float32_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxnmavq_f32 (float32_t __a, float32x4_t __b)
@@ -11225,34 +11179,6 @@ __arm_vfmsq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16
   return __builtin_mve_vfmsq_m_fv8hf (__a, __b, __c, __p);
 }
 
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxnmq_m_fv4sf (__inactive, __a, __b, __p);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxnmq_m_fv8hf (__inactive, __a, __b, __p);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminnmq_m_fv4sf (__inactive, __a, __b, __p);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminnmq_m_fv8hf (__inactive, __a, __b, __p);
-}
-
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vornq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
@@ -11539,34 +11465,6 @@ __arm_vdupq_x_n_f32 (float32_t __a, mve_pred16_t __p)
   return __builtin_mve_vdupq_m_n_fv4sf (__arm_vuninitializedq_f32 (), __a, __p);
 }
 
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminnmq_m_fv8hf (__arm_vuninitializedq_f16 (), __a, __b, __p);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminnmq_m_fv4sf (__arm_vuninitializedq_f32 (), __a, __b, __p);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxnmq_m_fv8hf (__arm_vuninitializedq_f16 (), __a, __b, __p);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxnmq_m_fv4sf (__arm_vuninitializedq_f32 (), __a, __b, __p);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcaddq_rot90_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
@@ -19275,13 +19173,6 @@ __arm_vminnmvq (float16_t __a, float16x8_t __b)
  return __arm_vminnmvq_f16 (__a, __b);
 }
 
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq (float16x8_t __a, float16x8_t __b)
-{
- return __arm_vminnmq_f16 (__a, __b);
-}
-
 __extension__ extern __inline float16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminnmavq (float16_t __a, float16x8_t __b)
@@ -19303,13 +19194,6 @@ __arm_vmaxnmvq (float16_t __a, float16x8_t __b)
  return __arm_vmaxnmvq_f16 (__a, __b);
 }
 
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq (float16x8_t __a, float16x8_t __b)
-{
- return __arm_vmaxnmq_f16 (__a, __b);
-}
-
 __extension__ extern __inline float16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxnmavq (float16_t __a, float16x8_t __b)
@@ -19471,13 +19355,6 @@ __arm_vminnmvq (float32_t __a, float32x4_t __b)
  return __arm_vminnmvq_f32 (__a, __b);
 }
 
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq (float32x4_t __a, float32x4_t __b)
-{
- return __arm_vminnmq_f32 (__a, __b);
-}
-
 __extension__ extern __inline float32_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminnmavq (float32_t __a, float32x4_t __b)
@@ -19499,13 +19376,6 @@ __arm_vmaxnmvq (float32_t __a, float32x4_t __b)
  return __arm_vmaxnmvq_f32 (__a, __b);
 }
 
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq (float32x4_t __a, float32x4_t __b)
-{
- return __arm_vmaxnmq_f32 (__a, __b);
-}
-
 __extension__ extern __inline float32_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxnmavq (float32_t __a, float32x4_t __b)
@@ -20458,34 +20328,6 @@ __arm_vfmsq_m (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t _
  return __arm_vfmsq_m_f16 (__a, __b, __c, __p);
 }
 
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq_m (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxnmq_m_f32 (__inactive, __a, __b, __p);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq_m (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxnmq_m_f16 (__inactive, __a, __b, __p);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq_m (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vminnmq_m_f32 (__inactive, __a, __b, __p);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq_m (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vminnmq_m_f16 (__inactive, __a, __b, __p);
-}
-
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vornq_m (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
@@ -20696,34 +20538,6 @@ __arm_vstrwq_scatter_base_wb_p (uint32x4_t * __addr, const int __offset, float32
  __arm_vstrwq_scatter_base_wb_p_f32 (__addr, __offset, __value, __p);
 }
 
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq_x (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vminnmq_x_f16 (__a, __b, __p);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq_x (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vminnmq_x_f32 (__a, __b, __p);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq_x (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxnmq_x_f16 (__a, __b, __p);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq_x (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxnmq_x_f32 (__a, __b, __p);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcaddq_rot90_x (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
@@ -21564,12 +21378,6 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
 
-#define __arm_vmaxnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));})
-
 #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
@@ -21605,12 +21413,6 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_float16x8_t]: __arm_vbrsrq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), p1), \
   int (*)[__ARM_mve_type_float32x4_t]: __arm_vbrsrq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), p1));})
 
-#define __arm_vminnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));})
-
 #define __arm_vminnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
@@ -22329,20 +22131,6 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmsq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmsq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
 
-#define __arm_vmaxnmq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  __typeof(p2) __p2 = (p2); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
-
-#define __arm_vminnmq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  __typeof(p2) __p2 = (p2); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
-
 #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
@@ -22747,18 +22535,6 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_x_n_f16_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \
   int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_x_n_f32_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
 
-#define __arm_vmaxnmq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
-  __typeof(p2) __p2 = (p2); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
-
-#define __arm_vminnmq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
-  __typeof(p2) __p2 = (p2); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
-
 #define __arm_vornq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
-- 
2.34.1

[PATCH 09/16] arm: [MVE intrinsics] factorize vmaxnmavq vmaxnmvq vminnmavq vminnmvq

[Christophe Lyon]

Factorize vmaxnmavq vmaxnmvq vminnmavq vminnmvq so that they use the
same pattern.

2022-09-08  Christophe Lyon <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (MVE_VMAXNMxV_MINNMxVQ)
	(MVE_VMAXNMxV_MINNMxVQ_P): New.
	(mve_insn): Add vmaxnmav, vmaxnmv, vminnmav, vminnmv.
	* config/arm/mve.md (mve_vmaxnmavq_f<mode>, mve_vmaxnmvq_f<mode>)
	(mve_vminnmavq_f<mode>, mve_vminnmvq_f<mode>): Merge into ...
	(@mve_<mve_insn>q_f<mode>): ... this.
	(mve_vmaxnmavq_p_f<mode>, mve_vmaxnmvq_p_f<mode>)
	(mve_vminnmavq_p_f<mode>, mve_vminnmvq_p_f<mode>): Merge into ...
	(@mve_<mve_insn>q_p_f<mode>): ... this.
---
 gcc/config/arm/iterators.md |  22 +++++++
 gcc/config/arm/mve.md       | 114 +++++-------------------------------
 2 files changed, 37 insertions(+), 99 deletions(-)

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 397ac32720d..26ad687cefd 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -597,6 +597,20 @@ (define_int_iterator MVE_VMAXVQ_VMINVQ_P [
 		     VMINVQ_P_S VMINVQ_P_U
 		     ])
 
+(define_int_iterator MVE_VMAXNMxV_MINNMxVQ [
+		     VMAXNMAVQ_F
+		     VMAXNMVQ_F
+		     VMINNMAVQ_F
+		     VMINNMVQ_F
+		     ])
+
+(define_int_iterator MVE_VMAXNMxV_MINNMxVQ_P [
+		     VMAXNMAVQ_P_F
+		     VMAXNMVQ_P_F
+		     VMINNMAVQ_P_F
+		     VMINNMVQ_P_F
+		     ])
+
 (define_int_iterator MVE_MOVN [
 		     VMOVNBQ_S VMOVNBQ_U
 		     VMOVNTQ_S VMOVNTQ_U
@@ -648,13 +662,21 @@ (define_int_attr mve_insn [
 		 (VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub")
 		 (VMAXAVQ_P_S "vmaxav")
 		 (VMAXAVQ_S "vmaxav")
+		 (VMAXNMAVQ_F "vmaxnmav")
+		 (VMAXNMAVQ_P_F "vmaxnmav")
 		 (VMAXNMQ_M_F "vmaxnm")
+		 (VMAXNMVQ_F "vmaxnmv")
+		 (VMAXNMVQ_P_F "vmaxnmv")
 		 (VMAXQ_M_S "vmax") (VMAXQ_M_U "vmax")
 		 (VMAXVQ_P_S "vmaxv") (VMAXVQ_P_U "vmaxv")
 		 (VMAXVQ_S "vmaxv") (VMAXVQ_U "vmaxv")
 		 (VMINAVQ_P_S "vminav")
 		 (VMINAVQ_S "vminav")
+		 (VMINNMAVQ_F "vminnmav")
+		 (VMINNMAVQ_P_F "vminnmav")
 		 (VMINNMQ_M_F "vminnm")
+		 (VMINNMVQ_F "vminnmv")
+		 (VMINNMVQ_P_F "vminnmv")
 		 (VMINQ_M_S "vmin") (VMINQ_M_U "vmin")
 		 (VMINVQ_P_S "vminv") (VMINVQ_P_U "vminv")
 		 (VMINVQ_S "vminv") (VMINVQ_U "vminv")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index d2863b316e0..2aebaa99bbf 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1440,17 +1440,20 @@ (define_insn "mve_vmaxnmaq_f<mode>"
 ])
 
 ;;
-;; [vmaxnmavq_f])
+;; [vmaxnmavq_f]
+;; [vmaxnmvq_f]
+;; [vminnmavq_f]
+;; [vminnmvq_f]
 ;;
-(define_insn "mve_vmaxnmavq_f<mode>"
+(define_insn "@mve_<mve_insn>q_f<mode>"
   [
    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
 	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
 			  (match_operand:MVE_0 2 "s_register_operand" "w")]
-	 VMAXNMAVQ_F))
+	 MVE_VMAXNMxV_MINNMxVQ))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vmaxnmav.f%#<V_sz_elem>	%0, %q2"
+  "<mve_insn>.f%#<V_sz_elem>\t%0, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1469,21 +1472,6 @@ (define_insn "@mve_<max_min_f_str>q_f<mode>"
   [(set_attr "type" "mve_move")
 ])
 
-;;
-;; [vmaxnmvq_f])
-;;
-(define_insn "mve_vmaxnmvq_f<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-			  (match_operand:MVE_0 2 "s_register_operand" "w")]
-	 VMAXNMVQ_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vmaxnmv.f%#<V_sz_elem>	%0, %q2"
-  [(set_attr "type" "mve_move")
-])
-
 ;;
 ;; [vminnmaq_f])
 ;;
@@ -1499,36 +1487,6 @@ (define_insn "mve_vminnmaq_f<mode>"
   [(set_attr "type" "mve_move")
 ])
 
-;;
-;; [vminnmavq_f])
-;;
-(define_insn "mve_vminnmavq_f<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-			  (match_operand:MVE_0 2 "s_register_operand" "w")]
-	 VMINNMAVQ_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vminnmav.f%#<V_sz_elem>	%0, %q2"
-  [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vminnmvq_f])
-;;
-(define_insn "mve_vminnmvq_f<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-			  (match_operand:MVE_0 2 "s_register_operand" "w")]
-	 VMINNMVQ_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vminnmv.f%#<V_sz_elem>	%0, %q2"
-  [(set_attr "type" "mve_move")
-])
-
 ;;
 ;; [vmlaldavq_u, vmlaldavq_s])
 ;;
@@ -3202,37 +3160,26 @@ (define_insn "mve_vmaxnmaq_m_f<mode>"
   "vpst\;vmaxnmat.f%#<V_sz_elem>	%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
-;;
-;; [vmaxnmavq_p_f])
-;;
-(define_insn "mve_vmaxnmavq_p_f<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-		       (match_operand:MVE_0 2 "s_register_operand" "w")
-		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VMAXNMAVQ_P_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vmaxnmavt.f%#<V_sz_elem>	%0, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
 
 ;;
-;; [vmaxnmvq_p_f])
+;; [vmaxnmavq_p_f]
+;; [vmaxnmvq_p_f]
+;; [vminnmavq_p_f]
+;; [vminnmvq_p_f]
 ;;
-(define_insn "mve_vmaxnmvq_p_f<mode>"
+(define_insn "@mve_<mve_insn>q_p_f<mode>"
   [
    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
 	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
 		       (match_operand:MVE_0 2 "s_register_operand" "w")
 		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VMAXNMVQ_P_F))
+	 MVE_VMAXNMxV_MINNMxVQ_P))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vmaxnmvt.f%#<V_sz_elem>	%0, %q2"
+  "vpst\;<mve_insn>t.f%#<V_sz_elem>\t%0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
+
 ;;
 ;; [vminnmaq_m_f])
 ;;
@@ -3249,37 +3196,6 @@ (define_insn "mve_vminnmaq_m_f<mode>"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
-;;
-;; [vminnmavq_p_f])
-;;
-(define_insn "mve_vminnmavq_p_f<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-		       (match_operand:MVE_0 2 "s_register_operand" "w")
-		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VMINNMAVQ_P_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vminnmavt.f%#<V_sz_elem>	%0, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-;;
-;; [vminnmvq_p_f])
-;;
-(define_insn "mve_vminnmvq_p_f<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-	(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-		       (match_operand:MVE_0 2 "s_register_operand" "w")
-		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VMINNMVQ_P_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vminnmvt.f%#<V_sz_elem>	%0, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
 ;;
 ;; [vmlaldavaq_s, vmlaldavaq_u])
 ;;
-- 
2.34.1

[PATCH 10/16] arm: [MVE intrinsics] add support for mve_q_p_f

[Christophe Lyon]

We can call code_for_mve_q_p_f only once this function exists, which
is the case after we factorized vmaxnmavq, vmaxnmvq, vminnmavq and
vminnmvq in a previous patch.

2022-09-08  Christophe Lyon <christophe.lyon@arm.com>

	gcc/
	* config/arm/arm-mve-builtins-functions.h
	(unspec_mve_function_exact_insn_pred_p): Use code_for_mve_q_p_f.
---
 gcc/config/arm/arm-mve-builtins-functions.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/arm/arm-mve-builtins-functions.h b/gcc/config/arm/arm-mve-builtins-functions.h
index bf4e209a720..ddedbb2a8e1 100644
--- a/gcc/config/arm/arm-mve-builtins-functions.h
+++ b/gcc/config/arm/arm-mve-builtins-functions.h
@@ -428,7 +428,7 @@ public:
 	  else
 	    code = code_for_mve_q_p (m_unspec_for_p_sint, m_unspec_for_p_sint, e.vector_mode (0));
 	else
-	  gcc_unreachable ();  /* Will be fixed later in the series.  */
+	  code = code_for_mve_q_p_f (m_unspec_for_p_fp, e.vector_mode (0));
 
 	return e.use_exact_insn (code);
 
-- 
2.34.1

[PATCH 11/16] arm: [MVE intrinsics] rework vmaxnmavq vmaxnmvq vminnmavq vminnmvq

[Christophe Lyon]

Implement vmaxnmavq vmaxnmvq vminnmavq vminnmvq using the new MVE
builtins framework.

2022-09-08  Christophe Lyon <christophe.lyon@arm.com>

	gcc/
	* config/arm/arm-mve-builtins-base.cc (FUNCTION_PRED_P_F): New.
	(vmaxnmavq, vmaxnmvq, vminnmavq, vminnmvq): New.
	* config/arm/arm-mve-builtins-base.def (vmaxnmavq, vmaxnmvq)
	(vminnmavq, vminnmvq): New.
	* config/arm/arm-mve-builtins-base.h (vmaxnmavq, vmaxnmvq)
	(vminnmavq, vminnmvq): New.
	* config/arm/arm_mve.h (vminnmvq): Remove.
	(vminnmavq): Remove.
	(vmaxnmvq): Remove.
	(vmaxnmavq): Remove.
	(vmaxnmavq_p): Remove.
	(vmaxnmvq_p): Remove.
	(vminnmavq_p): Remove.
	(vminnmvq_p): Remove.
	(vminnmvq_f16): Remove.
	(vminnmavq_f16): Remove.
	(vmaxnmvq_f16): Remove.
	(vmaxnmavq_f16): Remove.
	(vminnmvq_f32): Remove.
	(vminnmavq_f32): Remove.
	(vmaxnmvq_f32): Remove.
	(vmaxnmavq_f32): Remove.
	(vmaxnmavq_p_f16): Remove.
	(vmaxnmvq_p_f16): Remove.
	(vminnmavq_p_f16): Remove.
	(vminnmvq_p_f16): Remove.
	(vmaxnmavq_p_f32): Remove.
	(vmaxnmvq_p_f32): Remove.
	(vminnmavq_p_f32): Remove.
	(vminnmvq_p_f32): Remove.
	(__arm_vminnmvq_f16): Remove.
	(__arm_vminnmavq_f16): Remove.
	(__arm_vmaxnmvq_f16): Remove.
	(__arm_vmaxnmavq_f16): Remove.
	(__arm_vminnmvq_f32): Remove.
	(__arm_vminnmavq_f32): Remove.
	(__arm_vmaxnmvq_f32): Remove.
	(__arm_vmaxnmavq_f32): Remove.
	(__arm_vmaxnmavq_p_f16): Remove.
	(__arm_vmaxnmvq_p_f16): Remove.
	(__arm_vminnmavq_p_f16): Remove.
	(__arm_vminnmvq_p_f16): Remove.
	(__arm_vmaxnmavq_p_f32): Remove.
	(__arm_vmaxnmvq_p_f32): Remove.
	(__arm_vminnmavq_p_f32): Remove.
	(__arm_vminnmvq_p_f32): Remove.
	(__arm_vminnmvq): Remove.
	(__arm_vminnmavq): Remove.
	(__arm_vmaxnmvq): Remove.
	(__arm_vmaxnmavq): Remove.
	(__arm_vmaxnmavq_p): Remove.
	(__arm_vmaxnmvq_p): Remove.
	(__arm_vminnmavq_p): Remove.
	(__arm_vminnmvq_p): Remove.
	(__arm_vmaxnmavq_m): Remove.
	(__arm_vmaxnmvq_m): Remove.
---
 gcc/config/arm/arm-mve-builtins-base.cc  |  10 +
 gcc/config/arm/arm-mve-builtins-base.def |   4 +
 gcc/config/arm/arm-mve-builtins-base.h   |   4 +
 gcc/config/arm/arm_mve.h                 | 314 -----------------------
 4 files changed, 18 insertions(+), 314 deletions(-)

diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc
index dcbd1906563..af00d070739 100644
--- a/gcc/config/arm/arm-mve-builtins-base.cc
+++ b/gcc/config/arm/arm-mve-builtins-base.cc
@@ -225,6 +225,12 @@ namespace arm_mve {
    (UNSPEC##_S, UNSPEC##_U, -1,						\
     UNSPEC##_P_S, UNSPEC##_P_U, -1))
 
+  /* Helper for builtins without RTX codes, _F mode, _p predicated.  */
+#define FUNCTION_PRED_P_F(NAME, UNSPEC) FUNCTION			\
+  (NAME, unspec_mve_function_exact_insn_pred_p,				\
+   (-1, -1, UNSPEC##_F,							\
+    -1, -1, UNSPEC##_P_F))
+
 FUNCTION_WITHOUT_N (vabdq, VABDQ)
 FUNCTION (vabsq, unspec_based_mve_function_exact_insn, (ABS, ABS, ABS, -1, -1, -1, VABSQ_M_S, -1, VABSQ_M_F, -1, -1, -1))
 FUNCTION_WITH_RTX_M_N (vaddq, PLUS, VADDQ)
@@ -236,11 +242,15 @@ FUNCTION_WITH_RTX_M (veorq, XOR, VEORQ)
 FUNCTION_WITH_M_N_NO_F (vhaddq, VHADDQ)
 FUNCTION_WITH_M_N_NO_F (vhsubq, VHSUBQ)
 FUNCTION_PRED_P_S (vmaxavq, VMAXAVQ)
+FUNCTION_PRED_P_F (vmaxnmavq, VMAXNMAVQ)
 FUNCTION (vmaxnmq, unspec_based_mve_function_exact_insn, (UNKNOWN, UNKNOWN, SMAX, -1, -1, -1, -1, -1, VMAXNMQ_M_F, -1, -1, -1))
+FUNCTION_PRED_P_F (vmaxnmvq, VMAXNMVQ)
 FUNCTION_WITH_RTX_M_NO_F (vmaxq, SMAX, UMAX, VMAXQ)
 FUNCTION_PRED_P_S_U (vmaxvq, VMAXVQ)
 FUNCTION_PRED_P_S (vminavq, VMINAVQ)
+FUNCTION_PRED_P_F (vminnmavq, VMINNMAVQ)
 FUNCTION (vminnmq, unspec_based_mve_function_exact_insn, (UNKNOWN, UNKNOWN, SMIN, -1, -1, -1, -1, -1, VMINNMQ_M_F, -1, -1, -1))
+FUNCTION_PRED_P_F (vminnmvq, VMINNMVQ)
 FUNCTION_WITH_RTX_M_NO_F (vminq, SMIN, UMIN, VMINQ)
 FUNCTION_PRED_P_S_U (vminvq, VMINVQ)
 FUNCTION_WITHOUT_N_NO_F (vmovnbq, VMOVNBQ)
diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def
index c2155bafeb3..19ac75c8f2e 100644
--- a/gcc/config/arm/arm-mve-builtins-base.def
+++ b/gcc/config/arm/arm-mve-builtins-base.def
@@ -86,8 +86,12 @@ DEF_MVE_FUNCTION (vaddq, binary_opt_n, all_float, mx_or_none)
 DEF_MVE_FUNCTION (vandq, binary, all_float, mx_or_none)
 DEF_MVE_FUNCTION (vcreateq, create, all_float, none)
 DEF_MVE_FUNCTION (veorq, binary, all_float, mx_or_none)
+DEF_MVE_FUNCTION (vmaxnmavq, binary_maxvminv, all_float, p_or_none)
 DEF_MVE_FUNCTION (vmaxnmq, binary, all_float, mx_or_none)
+DEF_MVE_FUNCTION (vmaxnmvq, binary_maxvminv, all_float, p_or_none)
+DEF_MVE_FUNCTION (vminnmavq, binary_maxvminv, all_float, p_or_none)
 DEF_MVE_FUNCTION (vminnmq, binary, all_float, mx_or_none)
+DEF_MVE_FUNCTION (vminnmvq, binary_maxvminv, all_float, p_or_none)
 DEF_MVE_FUNCTION (vmulq, binary_opt_n, all_float, mx_or_none)
 DEF_MVE_FUNCTION (vnegq, unary, all_float, mx_or_none)
 DEF_MVE_FUNCTION (vorrq, binary_orrq, all_float, mx_or_none)
diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h
index 0290ee72b4c..dc413fc63df 100644
--- a/gcc/config/arm/arm-mve-builtins-base.h
+++ b/gcc/config/arm/arm-mve-builtins-base.h
@@ -34,11 +34,15 @@ extern const function_base *const veorq;
 extern const function_base *const vhaddq;
 extern const function_base *const vhsubq;
 extern const function_base *const vmaxavq;
+extern const function_base *const vmaxnmavq;
 extern const function_base *const vmaxnmq;
+extern const function_base *const vmaxnmvq;
 extern const function_base *const vmaxq;
 extern const function_base *const vmaxvq;
 extern const function_base *const vminavq;
+extern const function_base *const vminnmavq;
 extern const function_base *const vminnmq;
+extern const function_base *const vminnmvq;
 extern const function_base *const vminq;
 extern const function_base *const vminvq;
 extern const function_base *const vmovnbq;
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 12e77eee11e..ac0e5801d0c 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -308,11 +308,7 @@
 #define vcvtbq_f32(__a) __arm_vcvtbq_f32(__a)
 #define vcvtq(__a) __arm_vcvtq(__a)
 #define vcvtq_n(__a, __imm6) __arm_vcvtq_n(__a, __imm6)
-#define vminnmvq(__a, __b) __arm_vminnmvq(__a, __b)
-#define vminnmavq(__a, __b) __arm_vminnmavq(__a, __b)
 #define vminnmaq(__a, __b) __arm_vminnmaq(__a, __b)
-#define vmaxnmvq(__a, __b) __arm_vmaxnmvq(__a, __b)
-#define vmaxnmavq(__a, __b) __arm_vmaxnmavq(__a, __b)
 #define vmaxnmaq(__a, __b) __arm_vmaxnmaq(__a, __b)
 #define vcmulq_rot90(__a, __b) __arm_vcmulq_rot90(__a, __b)
 #define vcmulq_rot270(__a, __b) __arm_vcmulq_rot270(__a, __b)
@@ -333,11 +329,7 @@
 #define vcvtnq_m(__inactive, __a, __p) __arm_vcvtnq_m(__inactive, __a, __p)
 #define vcvtpq_m(__inactive, __a, __p) __arm_vcvtpq_m(__inactive, __a, __p)
 #define vmaxnmaq_m(__a, __b, __p) __arm_vmaxnmaq_m(__a, __b, __p)
-#define vmaxnmavq_p(__a, __b, __p) __arm_vmaxnmavq_p(__a, __b, __p)
-#define vmaxnmvq_p(__a, __b, __p) __arm_vmaxnmvq_p(__a, __b, __p)
 #define vminnmaq_m(__a, __b, __p) __arm_vminnmaq_m(__a, __b, __p)
-#define vminnmavq_p(__a, __b, __p) __arm_vminnmavq_p(__a, __b, __p)
-#define vminnmvq_p(__a, __b, __p) __arm_vminnmvq_p(__a, __b, __p)
 #define vcvtq_m_n(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n(__inactive, __a, __imm6, __p)
 #define vcmlaq_m(__a, __b, __c, __p) __arm_vcmlaq_m(__a, __b, __c, __p)
 #define vcmlaq_rot180_m(__a, __b, __c, __p) __arm_vcmlaq_rot180_m(__a, __b, __c, __p)
@@ -627,11 +619,7 @@
 #define vmlsldavq_s16(__a, __b) __arm_vmlsldavq_s16(__a, __b)
 #define vmlaldavxq_s16(__a, __b) __arm_vmlaldavxq_s16(__a, __b)
 #define vmlaldavq_s16(__a, __b) __arm_vmlaldavq_s16(__a, __b)
-#define vminnmvq_f16(__a, __b) __arm_vminnmvq_f16(__a, __b)
-#define vminnmavq_f16(__a, __b) __arm_vminnmavq_f16(__a, __b)
 #define vminnmaq_f16(__a, __b) __arm_vminnmaq_f16(__a, __b)
-#define vmaxnmvq_f16(__a, __b) __arm_vmaxnmvq_f16(__a, __b)
-#define vmaxnmavq_f16(__a, __b) __arm_vmaxnmavq_f16(__a, __b)
 #define vmaxnmaq_f16(__a, __b) __arm_vmaxnmaq_f16(__a, __b)
 #define vcmulq_rot90_f16(__a, __b) __arm_vcmulq_rot90_f16(__a, __b)
 #define vcmulq_rot270_f16(__a, __b) __arm_vcmulq_rot270_f16(__a, __b)
@@ -666,11 +654,7 @@
 #define vmlsldavq_s32(__a, __b) __arm_vmlsldavq_s32(__a, __b)
 #define vmlaldavxq_s32(__a, __b) __arm_vmlaldavxq_s32(__a, __b)
 #define vmlaldavq_s32(__a, __b) __arm_vmlaldavq_s32(__a, __b)
-#define vminnmvq_f32(__a, __b) __arm_vminnmvq_f32(__a, __b)
-#define vminnmavq_f32(__a, __b) __arm_vminnmavq_f32(__a, __b)
 #define vminnmaq_f32(__a, __b) __arm_vminnmaq_f32(__a, __b)
-#define vmaxnmvq_f32(__a, __b) __arm_vmaxnmvq_f32(__a, __b)
-#define vmaxnmavq_f32(__a, __b) __arm_vmaxnmavq_f32(__a, __b)
 #define vmaxnmaq_f32(__a, __b) __arm_vmaxnmaq_f32(__a, __b)
 #define vcmulq_rot90_f32(__a, __b) __arm_vcmulq_rot90_f32(__a, __b)
 #define vcmulq_rot270_f32(__a, __b) __arm_vcmulq_rot270_f32(__a, __b)
@@ -945,11 +929,7 @@
 #define vcvtq_m_s16_f16(__inactive, __a, __p) __arm_vcvtq_m_s16_f16(__inactive, __a, __p)
 #define vdupq_m_n_f16(__inactive, __a, __p) __arm_vdupq_m_n_f16(__inactive, __a, __p)
 #define vmaxnmaq_m_f16(__a, __b, __p) __arm_vmaxnmaq_m_f16(__a, __b, __p)
-#define vmaxnmavq_p_f16(__a, __b, __p) __arm_vmaxnmavq_p_f16(__a, __b, __p)
-#define vmaxnmvq_p_f16(__a, __b, __p) __arm_vmaxnmvq_p_f16(__a, __b, __p)
 #define vminnmaq_m_f16(__a, __b, __p) __arm_vminnmaq_m_f16(__a, __b, __p)
-#define vminnmavq_p_f16(__a, __b, __p) __arm_vminnmavq_p_f16(__a, __b, __p)
-#define vminnmvq_p_f16(__a, __b, __p) __arm_vminnmvq_p_f16(__a, __b, __p)
 #define vmlaldavq_p_s16(__a, __b, __p) __arm_vmlaldavq_p_s16(__a, __b, __p)
 #define vmlaldavxq_p_s16(__a, __b, __p) __arm_vmlaldavxq_p_s16(__a, __b, __p)
 #define vmlsldavq_p_s16(__a, __b, __p) __arm_vmlsldavq_p_s16(__a, __b, __p)
@@ -999,11 +979,7 @@
 #define vcvtq_m_s32_f32(__inactive, __a, __p) __arm_vcvtq_m_s32_f32(__inactive, __a, __p)
 #define vdupq_m_n_f32(__inactive, __a, __p) __arm_vdupq_m_n_f32(__inactive, __a, __p)
 #define vmaxnmaq_m_f32(__a, __b, __p) __arm_vmaxnmaq_m_f32(__a, __b, __p)
-#define vmaxnmavq_p_f32(__a, __b, __p) __arm_vmaxnmavq_p_f32(__a, __b, __p)
-#define vmaxnmvq_p_f32(__a, __b, __p) __arm_vmaxnmvq_p_f32(__a, __b, __p)
 #define vminnmaq_m_f32(__a, __b, __p) __arm_vminnmaq_m_f32(__a, __b, __p)
-#define vminnmavq_p_f32(__a, __b, __p) __arm_vminnmavq_p_f32(__a, __b, __p)
-#define vminnmvq_p_f32(__a, __b, __p) __arm_vminnmvq_p_f32(__a, __b, __p)
 #define vmlaldavq_p_s32(__a, __b, __p) __arm_vmlaldavq_p_s32(__a, __b, __p)
 #define vmlaldavxq_p_s32(__a, __b, __p) __arm_vmlaldavxq_p_s32(__a, __b, __p)
 #define vmlsldavq_p_s32(__a, __b, __p) __arm_vmlsldavq_p_s32(__a, __b, __p)
@@ -10002,20 +9978,6 @@ __arm_vornq_f16 (float16x8_t __a, float16x8_t __b)
   return __builtin_mve_vornq_fv8hf (__a, __b);
 }
 
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmvq_f16 (float16_t __a, float16x8_t __b)
-{
-  return __builtin_mve_vminnmvq_fv8hf (__a, __b);
-}
-
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmavq_f16 (float16_t __a, float16x8_t __b)
-{
-  return __builtin_mve_vminnmavq_fv8hf (__a, __b);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminnmaq_f16 (float16x8_t __a, float16x8_t __b)
@@ -10023,20 +9985,6 @@ __arm_vminnmaq_f16 (float16x8_t __a, float16x8_t __b)
   return __builtin_mve_vminnmaq_fv8hf (__a, __b);
 }
 
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmvq_f16 (float16_t __a, float16x8_t __b)
-{
-  return __builtin_mve_vmaxnmvq_fv8hf (__a, __b);
-}
-
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmavq_f16 (float16_t __a, float16x8_t __b)
-{
-  return __builtin_mve_vmaxnmavq_fv8hf (__a, __b);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxnmaq_f16 (float16x8_t __a, float16x8_t __b)
@@ -10184,20 +10132,6 @@ __arm_vornq_f32 (float32x4_t __a, float32x4_t __b)
   return __builtin_mve_vornq_fv4sf (__a, __b);
 }
 
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmvq_f32 (float32_t __a, float32x4_t __b)
-{
-  return __builtin_mve_vminnmvq_fv4sf (__a, __b);
-}
-
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmavq_f32 (float32_t __a, float32x4_t __b)
-{
-  return __builtin_mve_vminnmavq_fv4sf (__a, __b);
-}
-
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminnmaq_f32 (float32x4_t __a, float32x4_t __b)
@@ -10205,20 +10139,6 @@ __arm_vminnmaq_f32 (float32x4_t __a, float32x4_t __b)
   return __builtin_mve_vminnmaq_fv4sf (__a, __b);
 }
 
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmvq_f32 (float32_t __a, float32x4_t __b)
-{
-  return __builtin_mve_vmaxnmvq_fv4sf (__a, __b);
-}
-
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmavq_f32 (float32_t __a, float32x4_t __b)
-{
-  return __builtin_mve_vmaxnmavq_fv4sf (__a, __b);
-}
-
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxnmaq_f32 (float32x4_t __a, float32x4_t __b)
@@ -10493,20 +10413,6 @@ __arm_vmaxnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
   return __builtin_mve_vmaxnmaq_m_fv8hf (__a, __b, __p);
 }
 
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmavq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxnmavq_p_fv8hf (__a, __b, __p);
-}
-
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmvq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxnmvq_p_fv8hf (__a, __b, __p);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
@@ -10514,20 +10420,6 @@ __arm_vminnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
   return __builtin_mve_vminnmaq_m_fv8hf (__a, __b, __p);
 }
 
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmavq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminnmavq_p_fv8hf (__a, __b, __p);
-}
-
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmvq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminnmvq_p_fv8hf (__a, __b, __p);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vpselq_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
@@ -10745,20 +10637,6 @@ __arm_vmaxnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
   return __builtin_mve_vmaxnmaq_m_fv4sf (__a, __b, __p);
 }
 
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmavq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxnmavq_p_fv4sf (__a, __b, __p);
-}
-
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmvq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxnmvq_p_fv4sf (__a, __b, __p);
-}
-
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
@@ -10766,20 +10644,6 @@ __arm_vminnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
   return __builtin_mve_vminnmaq_m_fv4sf (__a, __b, __p);
 }
 
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmavq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminnmavq_p_fv4sf (__a, __b, __p);
-}
-
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmvq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminnmvq_p_fv4sf (__a, __b, __p);
-}
-
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vpselq_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
@@ -19166,20 +19030,6 @@ __arm_vornq (float16x8_t __a, float16x8_t __b)
  return __arm_vornq_f16 (__a, __b);
 }
 
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmvq (float16_t __a, float16x8_t __b)
-{
- return __arm_vminnmvq_f16 (__a, __b);
-}
-
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmavq (float16_t __a, float16x8_t __b)
-{
- return __arm_vminnmavq_f16 (__a, __b);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminnmaq (float16x8_t __a, float16x8_t __b)
@@ -19187,20 +19037,6 @@ __arm_vminnmaq (float16x8_t __a, float16x8_t __b)
  return __arm_vminnmaq_f16 (__a, __b);
 }
 
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmvq (float16_t __a, float16x8_t __b)
-{
- return __arm_vmaxnmvq_f16 (__a, __b);
-}
-
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmavq (float16_t __a, float16x8_t __b)
-{
- return __arm_vmaxnmavq_f16 (__a, __b);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxnmaq (float16x8_t __a, float16x8_t __b)
@@ -19348,20 +19184,6 @@ __arm_vornq (float32x4_t __a, float32x4_t __b)
  return __arm_vornq_f32 (__a, __b);
 }
 
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmvq (float32_t __a, float32x4_t __b)
-{
- return __arm_vminnmvq_f32 (__a, __b);
-}
-
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmavq (float32_t __a, float32x4_t __b)
-{
- return __arm_vminnmavq_f32 (__a, __b);
-}
-
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminnmaq (float32x4_t __a, float32x4_t __b)
@@ -19369,20 +19191,6 @@ __arm_vminnmaq (float32x4_t __a, float32x4_t __b)
  return __arm_vminnmaq_f32 (__a, __b);
 }
 
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmvq (float32_t __a, float32x4_t __b)
-{
- return __arm_vmaxnmvq_f32 (__a, __b);
-}
-
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmavq (float32_t __a, float32x4_t __b)
-{
- return __arm_vmaxnmavq_f32 (__a, __b);
-}
-
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vmaxnmaq (float32x4_t __a, float32x4_t __b)
@@ -19642,20 +19450,6 @@ __arm_vmaxnmaq_m (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
  return __arm_vmaxnmaq_m_f16 (__a, __b, __p);
 }
 
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmavq_p (float16_t __a, float16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxnmavq_p_f16 (__a, __b, __p);
-}
-
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmvq_p (float16_t __a, float16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxnmvq_p_f16 (__a, __b, __p);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminnmaq_m (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
@@ -19663,20 +19457,6 @@ __arm_vminnmaq_m (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
  return __arm_vminnmaq_m_f16 (__a, __b, __p);
 }
 
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmavq_p (float16_t __a, float16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vminnmavq_p_f16 (__a, __b, __p);
-}
-
-__extension__ extern __inline float16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmvq_p (float16_t __a, float16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vminnmvq_p_f16 (__a, __b, __p);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vpselq (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
@@ -19894,20 +19674,6 @@ __arm_vmaxnmaq_m (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
  return __arm_vmaxnmaq_m_f32 (__a, __b, __p);
 }
 
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmavq_p (float32_t __a, float32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxnmavq_p_f32 (__a, __b, __p);
-}
-
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmvq_p (float32_t __a, float32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxnmvq_p_f32 (__a, __b, __p);
-}
-
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vminnmaq_m (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
@@ -19915,20 +19681,6 @@ __arm_vminnmaq_m (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
  return __arm_vminnmaq_m_f32 (__a, __b, __p);
 }
 
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmavq_p (float32_t __a, float32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vminnmavq_p_f32 (__a, __b, __p);
-}
-
-__extension__ extern __inline float32_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmvq_p (float32_t __a, float32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vminnmvq_p_f32 (__a, __b, __p);
-}
-
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vpselq (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
@@ -21372,36 +21124,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));})
 
-#define __arm_vmaxnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
-
-#define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
-
-#define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
-
 #define __arm_vminnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));})
 
-#define __arm_vminnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
-
 #define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int8x16_t]: __arm_vbrsrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \
@@ -21413,12 +21141,6 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_float16x8_t]: __arm_vbrsrq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), p1), \
   int (*)[__ARM_mve_type_float32x4_t]: __arm_vbrsrq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), p1));})
 
-#define __arm_vminnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));})
-
 #define __arm_vqshluq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int8x16_t]: __arm_vqshluq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \
@@ -21890,48 +21612,12 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
-#define __arm_vmaxnmavq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));})
-
-#define __arm_vmaxnmvq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));})
-
-#define __arm_vmaxnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
-
-#define __arm_vmaxnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
-
 #define __arm_vminnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));})
 
-#define __arm_vminnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
-
-#define __arm_vminnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));})
-
 #define __arm_vrev64q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-- 
2.34.1

[PATCH 12/16] arm: [MVE intrinsics] factorize vmaxnmaq vminnmaq

[Christophe Lyon]

Factorize vmaxnmaq and vminnmaq so that they use the same pattern.

2022-09-08  Christophe Lyon <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (MVE_VMAXNMA_VMINNMAQ)
	(MVE_VMAXNMA_VMINNMAQ_M): New.
	(mve_insn): Add vmaxnma, vminnma.
	* config/arm/mve.md (mve_vmaxnmaq_f<mode>, mve_vminnmaq_f<mode>):
	Merge into ...
	(@mve_<mve_insn>q_f<mode>): ... this.
	(mve_vmaxnmaq_m_f<mode>, mve_vminnmaq_m_f<mode>): Merge into ...
	(@mve_<mve_insn>q_m_f<mode>): ... this.
---
 gcc/config/arm/iterators.md | 14 +++++++++++
 gcc/config/arm/mve.md       | 49 ++++++++-----------------------------
 2 files changed, 24 insertions(+), 39 deletions(-)

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 26ad687cefd..8edbf5a55cf 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -611,6 +611,16 @@ (define_int_iterator MVE_VMAXNMxV_MINNMxVQ_P [
 		     VMINNMVQ_P_F
 		     ])
 
+(define_int_iterator MVE_VMAXNMA_VMINNMAQ [
+		     VMAXNMAQ_F
+		     VMINNMAQ_F
+		     ])
+
+(define_int_iterator MVE_VMAXNMA_VMINNMAQ_M [
+		     VMAXNMAQ_M_F
+		     VMINNMAQ_M_F
+		     ])
+
 (define_int_iterator MVE_MOVN [
 		     VMOVNBQ_S VMOVNBQ_U
 		     VMOVNTQ_S VMOVNTQ_U
@@ -662,6 +672,8 @@ (define_int_attr mve_insn [
 		 (VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub")
 		 (VMAXAVQ_P_S "vmaxav")
 		 (VMAXAVQ_S "vmaxav")
+		 (VMAXNMAQ_F "vmaxnma")
+		 (VMAXNMAQ_M_F "vmaxnma")
 		 (VMAXNMAVQ_F "vmaxnmav")
 		 (VMAXNMAVQ_P_F "vmaxnmav")
 		 (VMAXNMQ_M_F "vmaxnm")
@@ -672,6 +684,8 @@ (define_int_attr mve_insn [
 		 (VMAXVQ_S "vmaxv") (VMAXVQ_U "vmaxv")
 		 (VMINAVQ_P_S "vminav")
 		 (VMINAVQ_S "vminav")
+		 (VMINNMAQ_F "vminnma")
+		 (VMINNMAQ_M_F "vminnma")
 		 (VMINNMAVQ_F "vminnmav")
 		 (VMINNMAVQ_P_F "vminnmav")
 		 (VMINNMQ_M_F "vminnm")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 2aebaa99bbf..ef0b6fd3ded 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1425,17 +1425,18 @@ (define_insn "mve_veorq_f<mode>"
 ])
 
 ;;
-;; [vmaxnmaq_f])
+;; [vmaxnmaq_f]
+;; [vminnmaq_f]
 ;;
-(define_insn "mve_vmaxnmaq_f<mode>"
+(define_insn "@mve_<mve_insn>q_f<mode>"
   [
    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
 		       (match_operand:MVE_0 2 "s_register_operand" "w")]
-	 VMAXNMAQ_F))
+	 MVE_VMAXNMA_VMINNMAQ))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vmaxnma.f%#<V_sz_elem>	%q0, %q2"
+  "<mve_insn>.f%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1472,21 +1473,6 @@ (define_insn "@mve_<max_min_f_str>q_f<mode>"
   [(set_attr "type" "mve_move")
 ])
 
-;;
-;; [vminnmaq_f])
-;;
-(define_insn "mve_vminnmaq_f<mode>"
-  [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
-	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
-		       (match_operand:MVE_0 2 "s_register_operand" "w")]
-	 VMINNMAQ_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vminnma.f%#<V_sz_elem>	%q0, %q2"
-  [(set_attr "type" "mve_move")
-])
-
 ;;
 ;; [vmlaldavq_u, vmlaldavq_s])
 ;;
@@ -3146,18 +3132,19 @@ (define_insn "mve_vfmsq_f<mode>"
 ])
 
 ;;
-;; [vmaxnmaq_m_f])
+;; [vmaxnmaq_m_f]
+;; [vminnmaq_m_f]
 ;;
-(define_insn "mve_vmaxnmaq_m_f<mode>"
+(define_insn "@mve_<mve_insn>q_m_f<mode>"
   [
    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
 	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
 		       (match_operand:MVE_0 2 "s_register_operand" "w")
 		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VMAXNMAQ_M_F))
+	 MVE_VMAXNMA_VMINNMAQ_M))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vmaxnmat.f%#<V_sz_elem>	%q0, %q2"
+  "vpst\;<mve_insn>t.f%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3180,22 +3167,6 @@ (define_insn "@mve_<mve_insn>q_p_f<mode>"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
-;;
-;; [vminnmaq_m_f])
-;;
-(define_insn "mve_vminnmaq_m_f<mode>"
-  [
-   (set (match_operand:MVE_0 0 "s_register_operand" "=w")
-	(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
-		       (match_operand:MVE_0 2 "s_register_operand" "w")
-		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VMINNMAQ_M_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vminnmat.f%#<V_sz_elem>	%q0, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
 ;;
 ;; [vmlaldavaq_s, vmlaldavaq_u])
 ;;
-- 
2.34.1

[PATCH 13/16] arm: [MVE intrinsics] rework vmaxnmaq vminnmaq

[Christophe Lyon]

Implement vmaxnmaq and vminnmaq using the new MVE builtins framework.

2022-09-08  Christophe Lyon <christophe.lyon@arm.com>

	gcc/
	* config/arm/arm-mve-builtins-base.cc (vmaxnmaq, vminnmaq): New.
	* config/arm/arm-mve-builtins-base.def (vmaxnmaq, vminnmaq): New.
	* config/arm/arm-mve-builtins-base.h (vmaxnmaq, vminnmaq): New.
	* config/arm/arm-mve-builtins.cc
	(function_instance::has_inactive_argument): Handle vmaxnmaq and
	vminnmaq.
	* config/arm/arm_mve.h (vminnmaq): Remove.
	(vmaxnmaq): Remove.
	(vmaxnmaq_m): Remove.
	(vminnmaq_m): Remove.
	(vminnmaq_f16): Remove.
	(vmaxnmaq_f16): Remove.
	(vminnmaq_f32): Remove.
	(vmaxnmaq_f32): Remove.
	(vmaxnmaq_m_f16): Remove.
	(vminnmaq_m_f16): Remove.
	(vmaxnmaq_m_f32): Remove.
	(vminnmaq_m_f32): Remove.
	(__arm_vminnmaq_f16): Remove.
	(__arm_vmaxnmaq_f16): Remove.
	(__arm_vminnmaq_f32): Remove.
	(__arm_vmaxnmaq_f32): Remove.
	(__arm_vmaxnmaq_m_f16): Remove.
	(__arm_vminnmaq_m_f16): Remove.
	(__arm_vmaxnmaq_m_f32): Remove.
	(__arm_vminnmaq_m_f32): Remove.
	(__arm_vminnmaq): Remove.
	(__arm_vmaxnmaq): Remove.
	(__arm_vmaxnmaq_m): Remove.
	(__arm_vminnmaq_m): Remove.
---
 gcc/config/arm/arm-mve-builtins-base.cc  |   2 +
 gcc/config/arm/arm-mve-builtins-base.def |   2 +
 gcc/config/arm/arm-mve-builtins-base.h   |   2 +
 gcc/config/arm/arm-mve-builtins.cc       |   2 +
 gcc/config/arm/arm_mve.h                 | 148 -----------------------
 5 files changed, 8 insertions(+), 148 deletions(-)

diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc
index af00d070739..8082e97a7ea 100644
--- a/gcc/config/arm/arm-mve-builtins-base.cc
+++ b/gcc/config/arm/arm-mve-builtins-base.cc
@@ -242,12 +242,14 @@ FUNCTION_WITH_RTX_M (veorq, XOR, VEORQ)
 FUNCTION_WITH_M_N_NO_F (vhaddq, VHADDQ)
 FUNCTION_WITH_M_N_NO_F (vhsubq, VHSUBQ)
 FUNCTION_PRED_P_S (vmaxavq, VMAXAVQ)
+FUNCTION_ONLY_F (vmaxnmaq, VMAXNMAQ)
 FUNCTION_PRED_P_F (vmaxnmavq, VMAXNMAVQ)
 FUNCTION (vmaxnmq, unspec_based_mve_function_exact_insn, (UNKNOWN, UNKNOWN, SMAX, -1, -1, -1, -1, -1, VMAXNMQ_M_F, -1, -1, -1))
 FUNCTION_PRED_P_F (vmaxnmvq, VMAXNMVQ)
 FUNCTION_WITH_RTX_M_NO_F (vmaxq, SMAX, UMAX, VMAXQ)
 FUNCTION_PRED_P_S_U (vmaxvq, VMAXVQ)
 FUNCTION_PRED_P_S (vminavq, VMINAVQ)
+FUNCTION_ONLY_F (vminnmaq, VMINNMAQ)
 FUNCTION_PRED_P_F (vminnmavq, VMINNMAVQ)
 FUNCTION (vminnmq, unspec_based_mve_function_exact_insn, (UNKNOWN, UNKNOWN, SMIN, -1, -1, -1, -1, -1, VMINNMQ_M_F, -1, -1, -1))
 FUNCTION_PRED_P_F (vminnmvq, VMINNMVQ)
diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def
index 19ac75c8f2e..45e2135452b 100644
--- a/gcc/config/arm/arm-mve-builtins-base.def
+++ b/gcc/config/arm/arm-mve-builtins-base.def
@@ -86,9 +86,11 @@ DEF_MVE_FUNCTION (vaddq, binary_opt_n, all_float, mx_or_none)
 DEF_MVE_FUNCTION (vandq, binary, all_float, mx_or_none)
 DEF_MVE_FUNCTION (vcreateq, create, all_float, none)
 DEF_MVE_FUNCTION (veorq, binary, all_float, mx_or_none)
+DEF_MVE_FUNCTION (vmaxnmaq, binary, all_float, m_or_none)
 DEF_MVE_FUNCTION (vmaxnmavq, binary_maxvminv, all_float, p_or_none)
 DEF_MVE_FUNCTION (vmaxnmq, binary, all_float, mx_or_none)
 DEF_MVE_FUNCTION (vmaxnmvq, binary_maxvminv, all_float, p_or_none)
+DEF_MVE_FUNCTION (vminnmaq, binary, all_float, m_or_none)
 DEF_MVE_FUNCTION (vminnmavq, binary_maxvminv, all_float, p_or_none)
 DEF_MVE_FUNCTION (vminnmq, binary, all_float, mx_or_none)
 DEF_MVE_FUNCTION (vminnmvq, binary_maxvminv, all_float, p_or_none)
diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h
index dc413fc63df..0242c33ac94 100644
--- a/gcc/config/arm/arm-mve-builtins-base.h
+++ b/gcc/config/arm/arm-mve-builtins-base.h
@@ -34,12 +34,14 @@ extern const function_base *const veorq;
 extern const function_base *const vhaddq;
 extern const function_base *const vhsubq;
 extern const function_base *const vmaxavq;
+extern const function_base *const vmaxnmaq;
 extern const function_base *const vmaxnmavq;
 extern const function_base *const vmaxnmq;
 extern const function_base *const vmaxnmvq;
 extern const function_base *const vmaxq;
 extern const function_base *const vmaxvq;
 extern const function_base *const vminavq;
+extern const function_base *const vminnmaq;
 extern const function_base *const vminnmavq;
 extern const function_base *const vminnmq;
 extern const function_base *const vminnmvq;
diff --git a/gcc/config/arm/arm-mve-builtins.cc b/gcc/config/arm/arm-mve-builtins.cc
index 38639f75785..5752434c968 100644
--- a/gcc/config/arm/arm-mve-builtins.cc
+++ b/gcc/config/arm/arm-mve-builtins.cc
@@ -670,6 +670,8 @@ function_instance::has_inactive_argument () const
     return false;
 
   if (mode_suffix_id == MODE_r
+      || base == functions::vmaxnmaq
+      || base == functions::vminnmaq
       || base == functions::vmovnbq
       || base == functions::vmovntq
       || base == functions::vqmovnbq
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index ac0e5801d0c..d25a9bf69d1 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -308,8 +308,6 @@
 #define vcvtbq_f32(__a) __arm_vcvtbq_f32(__a)
 #define vcvtq(__a) __arm_vcvtq(__a)
 #define vcvtq_n(__a, __imm6) __arm_vcvtq_n(__a, __imm6)
-#define vminnmaq(__a, __b) __arm_vminnmaq(__a, __b)
-#define vmaxnmaq(__a, __b) __arm_vmaxnmaq(__a, __b)
 #define vcmulq_rot90(__a, __b) __arm_vcmulq_rot90(__a, __b)
 #define vcmulq_rot270(__a, __b) __arm_vcmulq_rot270(__a, __b)
 #define vcmulq_rot180(__a, __b) __arm_vcmulq_rot180(__a, __b)
@@ -328,8 +326,6 @@
 #define vcvtmq_m(__inactive, __a, __p) __arm_vcvtmq_m(__inactive, __a, __p)
 #define vcvtnq_m(__inactive, __a, __p) __arm_vcvtnq_m(__inactive, __a, __p)
 #define vcvtpq_m(__inactive, __a, __p) __arm_vcvtpq_m(__inactive, __a, __p)
-#define vmaxnmaq_m(__a, __b, __p) __arm_vmaxnmaq_m(__a, __b, __p)
-#define vminnmaq_m(__a, __b, __p) __arm_vminnmaq_m(__a, __b, __p)
 #define vcvtq_m_n(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n(__inactive, __a, __imm6, __p)
 #define vcmlaq_m(__a, __b, __c, __p) __arm_vcmlaq_m(__a, __b, __c, __p)
 #define vcmlaq_rot180_m(__a, __b, __c, __p) __arm_vcmlaq_rot180_m(__a, __b, __c, __p)
@@ -619,8 +615,6 @@
 #define vmlsldavq_s16(__a, __b) __arm_vmlsldavq_s16(__a, __b)
 #define vmlaldavxq_s16(__a, __b) __arm_vmlaldavxq_s16(__a, __b)
 #define vmlaldavq_s16(__a, __b) __arm_vmlaldavq_s16(__a, __b)
-#define vminnmaq_f16(__a, __b) __arm_vminnmaq_f16(__a, __b)
-#define vmaxnmaq_f16(__a, __b) __arm_vmaxnmaq_f16(__a, __b)
 #define vcmulq_rot90_f16(__a, __b) __arm_vcmulq_rot90_f16(__a, __b)
 #define vcmulq_rot270_f16(__a, __b) __arm_vcmulq_rot270_f16(__a, __b)
 #define vcmulq_rot180_f16(__a, __b) __arm_vcmulq_rot180_f16(__a, __b)
@@ -654,8 +648,6 @@
 #define vmlsldavq_s32(__a, __b) __arm_vmlsldavq_s32(__a, __b)
 #define vmlaldavxq_s32(__a, __b) __arm_vmlaldavxq_s32(__a, __b)
 #define vmlaldavq_s32(__a, __b) __arm_vmlaldavq_s32(__a, __b)
-#define vminnmaq_f32(__a, __b) __arm_vminnmaq_f32(__a, __b)
-#define vmaxnmaq_f32(__a, __b) __arm_vmaxnmaq_f32(__a, __b)
 #define vcmulq_rot90_f32(__a, __b) __arm_vcmulq_rot90_f32(__a, __b)
 #define vcmulq_rot270_f32(__a, __b) __arm_vcmulq_rot270_f32(__a, __b)
 #define vcmulq_rot180_f32(__a, __b) __arm_vcmulq_rot180_f32(__a, __b)
@@ -928,8 +920,6 @@
 #define vcvtpq_m_s16_f16(__inactive, __a, __p) __arm_vcvtpq_m_s16_f16(__inactive, __a, __p)
 #define vcvtq_m_s16_f16(__inactive, __a, __p) __arm_vcvtq_m_s16_f16(__inactive, __a, __p)
 #define vdupq_m_n_f16(__inactive, __a, __p) __arm_vdupq_m_n_f16(__inactive, __a, __p)
-#define vmaxnmaq_m_f16(__a, __b, __p) __arm_vmaxnmaq_m_f16(__a, __b, __p)
-#define vminnmaq_m_f16(__a, __b, __p) __arm_vminnmaq_m_f16(__a, __b, __p)
 #define vmlaldavq_p_s16(__a, __b, __p) __arm_vmlaldavq_p_s16(__a, __b, __p)
 #define vmlaldavxq_p_s16(__a, __b, __p) __arm_vmlaldavxq_p_s16(__a, __b, __p)
 #define vmlsldavq_p_s16(__a, __b, __p) __arm_vmlsldavq_p_s16(__a, __b, __p)
@@ -978,8 +968,6 @@
 #define vcvtpq_m_s32_f32(__inactive, __a, __p) __arm_vcvtpq_m_s32_f32(__inactive, __a, __p)
 #define vcvtq_m_s32_f32(__inactive, __a, __p) __arm_vcvtq_m_s32_f32(__inactive, __a, __p)
 #define vdupq_m_n_f32(__inactive, __a, __p) __arm_vdupq_m_n_f32(__inactive, __a, __p)
-#define vmaxnmaq_m_f32(__a, __b, __p) __arm_vmaxnmaq_m_f32(__a, __b, __p)
-#define vminnmaq_m_f32(__a, __b, __p) __arm_vminnmaq_m_f32(__a, __b, __p)
 #define vmlaldavq_p_s32(__a, __b, __p) __arm_vmlaldavq_p_s32(__a, __b, __p)
 #define vmlaldavxq_p_s32(__a, __b, __p) __arm_vmlaldavxq_p_s32(__a, __b, __p)
 #define vmlsldavq_p_s32(__a, __b, __p) __arm_vmlsldavq_p_s32(__a, __b, __p)
@@ -9978,20 +9966,6 @@ __arm_vornq_f16 (float16x8_t __a, float16x8_t __b)
   return __builtin_mve_vornq_fv8hf (__a, __b);
 }
 
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmaq_f16 (float16x8_t __a, float16x8_t __b)
-{
-  return __builtin_mve_vminnmaq_fv8hf (__a, __b);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmaq_f16 (float16x8_t __a, float16x8_t __b)
-{
-  return __builtin_mve_vmaxnmaq_fv8hf (__a, __b);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmulq_rot90_f16 (float16x8_t __a, float16x8_t __b)
@@ -10132,20 +10106,6 @@ __arm_vornq_f32 (float32x4_t __a, float32x4_t __b)
   return __builtin_mve_vornq_fv4sf (__a, __b);
 }
 
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmaq_f32 (float32x4_t __a, float32x4_t __b)
-{
-  return __builtin_mve_vminnmaq_fv4sf (__a, __b);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmaq_f32 (float32x4_t __a, float32x4_t __b)
-{
-  return __builtin_mve_vmaxnmaq_fv4sf (__a, __b);
-}
-
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmulq_rot90_f32 (float32x4_t __a, float32x4_t __b)
@@ -10406,20 +10366,6 @@ __arm_vdupq_m_n_f16 (float16x8_t __inactive, float16_t __a, mve_pred16_t __p)
   return __builtin_mve_vdupq_m_n_fv8hf (__inactive, __a, __p);
 }
 
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxnmaq_m_fv8hf (__a, __b, __p);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminnmaq_m_fv8hf (__a, __b, __p);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vpselq_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
@@ -10630,20 +10576,6 @@ __arm_vdupq_m_n_f32 (float32x4_t __inactive, float32_t __a, mve_pred16_t __p)
   return __builtin_mve_vdupq_m_n_fv4sf (__inactive, __a, __p);
 }
 
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxnmaq_m_fv4sf (__a, __b, __p);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminnmaq_m_fv4sf (__a, __b, __p);
-}
-
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vpselq_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
@@ -19030,20 +18962,6 @@ __arm_vornq (float16x8_t __a, float16x8_t __b)
  return __arm_vornq_f16 (__a, __b);
 }
 
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmaq (float16x8_t __a, float16x8_t __b)
-{
- return __arm_vminnmaq_f16 (__a, __b);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmaq (float16x8_t __a, float16x8_t __b)
-{
- return __arm_vmaxnmaq_f16 (__a, __b);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmulq_rot90 (float16x8_t __a, float16x8_t __b)
@@ -19184,20 +19102,6 @@ __arm_vornq (float32x4_t __a, float32x4_t __b)
  return __arm_vornq_f32 (__a, __b);
 }
 
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmaq (float32x4_t __a, float32x4_t __b)
-{
- return __arm_vminnmaq_f32 (__a, __b);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmaq (float32x4_t __a, float32x4_t __b)
-{
- return __arm_vmaxnmaq_f32 (__a, __b);
-}
-
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmulq_rot90 (float32x4_t __a, float32x4_t __b)
@@ -19443,20 +19347,6 @@ __arm_vdupq_m (float16x8_t __inactive, float16_t __a, mve_pred16_t __p)
  return __arm_vdupq_m_n_f16 (__inactive, __a, __p);
 }
 
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmaq_m (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxnmaq_m_f16 (__a, __b, __p);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmaq_m (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vminnmaq_m_f16 (__a, __b, __p);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vpselq (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
@@ -19667,20 +19557,6 @@ __arm_vdupq_m (float32x4_t __inactive, float32_t __a, mve_pred16_t __p)
  return __arm_vdupq_m_n_f32 (__inactive, __a, __p);
 }
 
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmaq_m (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxnmaq_m_f32 (__a, __b, __p);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmaq_m (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vminnmaq_m_f32 (__a, __b, __p);
-}
-
 __extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vpselq (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
@@ -21118,18 +20994,6 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot90_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot90_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));})
 
-#define __arm_vmaxnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));})
-
-#define __arm_vminnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)));})
-
 #define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
   int (*)[__ARM_mve_type_int8x16_t]: __arm_vbrsrq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1), \
@@ -21606,18 +21470,6 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double)), \
   int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double)));})
 
-#define __arm_vmaxnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));})
-
-#define __arm_vminnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \
-  int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));})
-
 #define __arm_vrev64q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-- 
2.34.1

[PATCH 14/16] arm: [MVE intrinsics] add binary_maxamina shape

[Christophe Lyon]

This patch adds the binary_maxamina shape description.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/arm-mve-builtins-shapes.cc (binary_maxamina): New.
	* config/arm/arm-mve-builtins-shapes.h (binary_maxamina): New.
---
 gcc/config/arm/arm-mve-builtins-shapes.cc | 40 +++++++++++++++++++++++
 gcc/config/arm/arm-mve-builtins-shapes.h  |  1 +
 2 files changed, 41 insertions(+)

diff --git a/gcc/config/arm/arm-mve-builtins-shapes.cc b/gcc/config/arm/arm-mve-builtins-shapes.cc
index 1324abd1c12..c9eac80d1e3 100644
--- a/gcc/config/arm/arm-mve-builtins-shapes.cc
+++ b/gcc/config/arm/arm-mve-builtins-shapes.cc
@@ -401,6 +401,46 @@ struct binary_rshift_def : public overloaded_base<0>
 };
 SHAPE (binary_rshift)
 
+
+/* <uT0>_t vfoo[_t0](<uT0>_t, <T0>_t)
+
+   i.e. binary operations that take a vector of unsigned elements as first argument and a
+   vector of signed elements as second argument, and produce a vector of unsigned elements.
+
+   Example: vminaq.
+   uint8x16_t [__arm_]vminaq[_s8](uint8x16_t a, int8x16_t b)
+   uint8x16_t [__arm_]vminaq_m[_s8](uint8x16_t a, int8x16_t b, mve_pred16_t p)  */
+struct binary_maxamina_def : public overloaded_base<0>
+{
+  void
+  build (function_builder &b, const function_group_info &group,
+	 bool preserve_user_namespace) const override
+  {
+    b.add_overloaded_functions (group, MODE_none, preserve_user_namespace);
+    build_all (b, "vu0,vu0,vs0", group, MODE_none, preserve_user_namespace);
+  }
+
+  tree
+  resolve (function_resolver &r) const override
+  {
+    unsigned int i, nargs;
+    type_suffix_index type;
+    if (!r.check_gp_argument (2, i, nargs)
+	|| (type = r.infer_vector_type (i)) == NUM_TYPE_SUFFIXES)
+      return error_mark_node;
+
+    /* Check that the first argument has the expeected unsigned
+       type.  */
+    type_suffix_index return_type
+      = find_type_suffix (TYPE_unsigned, type_suffixes[type].element_bits);
+    if (!r.require_matching_vector_type (0, return_type))
+      return error_mark_node;
+
+    return r.resolve_to (r.mode_suffix_id, type);
+  }
+};
+SHAPE (binary_maxamina)
+
 /* <uS0>_t vfoo[_<t0>](<uS0>_t, <T0>_t)
 
    Example: vmaxavq.
diff --git a/gcc/config/arm/arm-mve-builtins-shapes.h b/gcc/config/arm/arm-mve-builtins-shapes.h
index cf4c523ab1a..7f582d7375a 100644
--- a/gcc/config/arm/arm-mve-builtins-shapes.h
+++ b/gcc/config/arm/arm-mve-builtins-shapes.h
@@ -37,6 +37,7 @@ namespace arm_mve
     extern const function_shape *const binary;
     extern const function_shape *const binary_lshift;
     extern const function_shape *const binary_lshift_r;
+    extern const function_shape *const binary_maxamina;
     extern const function_shape *const binary_maxavminav;
     extern const function_shape *const binary_maxvminv;
     extern const function_shape *const binary_move_narrow;
-- 
2.34.1

[PATCH 15/16] arm: [MVE intrinsics] factorize vmaxaq vminaq

[Christophe Lyon]

Factorize vmaxaq vminaq so that they use the same pattern.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (MVE_VMAXAVMINAQ, MVE_VMAXAVMINAQ_M):
	New.
	(mve_insn): Add vmaxa, vmina.
	(supf): Add VMAXAQ_S, VMAXAQ_M_S, VMINAQ_S, VMINAQ_M_S.
	* config/arm/mve.md (mve_vmaxaq_s<mode>, mve_vminaq_s<mode>):
	Merge into ...
	(@mve_<mve_insn>q_<supf><mode>): ... this.
	(mve_vmaxaq_m_s<mode>, mve_vminaq_m_s<mode>): Merge into ...
	(@mve_<mve_insn>q_m_<supf><mode>): ... this.
---
 gcc/config/arm/iterators.md | 18 ++++++++++++++
 gcc/config/arm/mve.md       | 49 ++++++++-----------------------------
 2 files changed, 28 insertions(+), 39 deletions(-)

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 8edbf5a55cf..3c70fd7f56d 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -621,6 +621,16 @@ (define_int_iterator MVE_VMAXNMA_VMINNMAQ_M [
 		     VMINNMAQ_M_F
 		     ])
 
+(define_int_iterator MVE_VMAXAVMINAQ [
+		     VMAXAQ_S
+		     VMINAQ_S
+		     ])
+
+(define_int_iterator MVE_VMAXAVMINAQ_M [
+		     VMAXAQ_M_S
+		     VMINAQ_M_S
+		     ])
+
 (define_int_iterator MVE_MOVN [
 		     VMOVNBQ_S VMOVNBQ_U
 		     VMOVNTQ_S VMOVNTQ_U
@@ -670,6 +680,8 @@ (define_int_attr mve_insn [
 		 (VHSUBQ_M_S "vhsub") (VHSUBQ_M_U "vhsub")
 		 (VHSUBQ_N_S "vhsub") (VHSUBQ_N_U "vhsub")
 		 (VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub")
+		 (VMAXAQ_M_S "vmaxa")
+		 (VMAXAQ_S "vmaxa")
 		 (VMAXAVQ_P_S "vmaxav")
 		 (VMAXAVQ_S "vmaxav")
 		 (VMAXNMAQ_F "vmaxnma")
@@ -682,6 +694,8 @@ (define_int_attr mve_insn [
 		 (VMAXQ_M_S "vmax") (VMAXQ_M_U "vmax")
 		 (VMAXVQ_P_S "vmaxv") (VMAXVQ_P_U "vmaxv")
 		 (VMAXVQ_S "vmaxv") (VMAXVQ_U "vmaxv")
+		 (VMINAQ_M_S "vmina")
+		 (VMINAQ_S "vmina")
 		 (VMINAVQ_P_S "vminav")
 		 (VMINAVQ_S "vminav")
 		 (VMINNMAQ_F "vminnma")
@@ -2064,6 +2078,10 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
 		       (VMAXAVQ_P_S "s")
 		       (VMINAVQ_S "s")
 		       (VMINAVQ_P_S "s")
+		       (VMAXAQ_S "s")
+		       (VMAXAQ_M_S "s")
+		       (VMINAQ_S "s")
+		       (VMINAQ_M_S "s")
 		       ])
 
 ;; Both kinds of return insn.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index ef0b6fd3ded..45bca6d6215 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -948,17 +948,18 @@ (define_insn "mve_vhcaddq_rot90_s<mode>"
 ])
 
 ;;
-;; [vmaxaq_s])
+;; [vmaxaq_s]
+;; [vminaq_s]
 ;;
-(define_insn "mve_vmaxaq_s<mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
 		       (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VMAXAQ_S))
+	 MVE_VMAXAVMINAQ))
   ]
   "TARGET_HAVE_MVE"
-  "vmaxa.s%#<V_sz_elem>	%q0, %q2"
+  "<mve_insn>.s%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -996,21 +997,6 @@ (define_insn "@mve_<mve_insn>q_<supf><mode>"
   [(set_attr "type" "mve_move")
 ])
 
-;;
-;; [vminaq_s])
-;;
-(define_insn "mve_vminaq_s<mode>"
-  [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VMINAQ_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vmina.s%#<V_sz_elem>\t%q0, %q2"
-  [(set_attr "type" "mve_move")
-])
-
 ;;
 ;; [vmladavq_u, vmladavq_s])
 ;;
@@ -2239,18 +2225,19 @@ (define_insn "mve_vdupq_m_n_<supf><mode>"
    (set_attr "length""8")])
 
 ;;
-;; [vmaxaq_m_s])
+;; [vmaxaq_m_s]
+;; [vminaq_m_s]
 ;;
-(define_insn "mve_vmaxaq_m_s<mode>"
+(define_insn "@mve_<mve_insn>q_m_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
 		       (match_operand:MVE_2 2 "s_register_operand" "w")
 		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VMAXAQ_M_S))
+	 MVE_VMAXAVMINAQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmaxat.s%#<V_sz_elem>	%q0, %q2"
+  "vpst\;<mve_insn>t.s%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -2273,22 +2260,6 @@ (define_insn "@mve_<mve_insn>q_p_<supf><mode>"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
-;;
-;; [vminaq_m_s])
-;;
-(define_insn "mve_vminaq_m_s<mode>"
-  [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")
-		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VMINAQ_M_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vminat.s%#<V_sz_elem>	%q0, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
 ;;
 ;; [vmladavaq_u, vmladavaq_s])
 ;;
-- 
2.34.1

[PATCH 16/16] arm: [MVE intrinsics] rework vmaxaq vminaq

[Christophe Lyon]

Implement vmaxaq and vminaq using the new MVE builtins framework.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/arm-mve-builtins-base.cc (vmaxaq, vminaq): New.
	* config/arm/arm-mve-builtins-base.def (vmaxaq, vminaq): New.
	* config/arm/arm-mve-builtins-base.h (vmaxaq, vminaq): New.
	* config/arm/arm-mve-builtins.cc
	(function_instance::has_inactive_argument): Handle vmaxaq and
	vminaq.
	* config/arm/arm_mve.h (vminaq): Remove.
	(vmaxaq): Remove.
	(vminaq_m): Remove.
	(vmaxaq_m): Remove.
	(vminaq_s8): Remove.
	(vmaxaq_s8): Remove.
	(vminaq_s16): Remove.
	(vmaxaq_s16): Remove.
	(vminaq_s32): Remove.
	(vmaxaq_s32): Remove.
	(vminaq_m_s8): Remove.
	(vmaxaq_m_s8): Remove.
	(vminaq_m_s16): Remove.
	(vmaxaq_m_s16): Remove.
	(vminaq_m_s32): Remove.
	(vmaxaq_m_s32): Remove.
	(__arm_vminaq_s8): Remove.
	(__arm_vmaxaq_s8): Remove.
	(__arm_vminaq_s16): Remove.
	(__arm_vmaxaq_s16): Remove.
	(__arm_vminaq_s32): Remove.
	(__arm_vmaxaq_s32): Remove.
	(__arm_vminaq_m_s8): Remove.
	(__arm_vmaxaq_m_s8): Remove.
	(__arm_vminaq_m_s16): Remove.
	(__arm_vmaxaq_m_s16): Remove.
	(__arm_vminaq_m_s32): Remove.
	(__arm_vmaxaq_m_s32): Remove.
	(__arm_vminaq): Remove.
	(__arm_vmaxaq): Remove.
	(__arm_vminaq_m): Remove.
	(__arm_vmaxaq_m): Remove.
---
 gcc/config/arm/arm-mve-builtins-base.cc  |   2 +
 gcc/config/arm/arm-mve-builtins-base.def |   2 +
 gcc/config/arm/arm-mve-builtins-base.h   |   2 +
 gcc/config/arm/arm-mve-builtins.cc       |   2 +
 gcc/config/arm/arm_mve.h                 | 240 -----------------------
 5 files changed, 8 insertions(+), 240 deletions(-)

diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc
index 8082e97a7ea..edca0d9ac6c 100644
--- a/gcc/config/arm/arm-mve-builtins-base.cc
+++ b/gcc/config/arm/arm-mve-builtins-base.cc
@@ -242,6 +242,7 @@ FUNCTION_WITH_RTX_M (veorq, XOR, VEORQ)
 FUNCTION_WITH_M_N_NO_F (vhaddq, VHADDQ)
 FUNCTION_WITH_M_N_NO_F (vhsubq, VHSUBQ)
 FUNCTION_PRED_P_S (vmaxavq, VMAXAVQ)
+FUNCTION_WITHOUT_N_NO_U_F (vmaxaq, VMAXAQ)
 FUNCTION_ONLY_F (vmaxnmaq, VMAXNMAQ)
 FUNCTION_PRED_P_F (vmaxnmavq, VMAXNMAVQ)
 FUNCTION (vmaxnmq, unspec_based_mve_function_exact_insn, (UNKNOWN, UNKNOWN, SMAX, -1, -1, -1, -1, -1, VMAXNMQ_M_F, -1, -1, -1))
@@ -249,6 +250,7 @@ FUNCTION_PRED_P_F (vmaxnmvq, VMAXNMVQ)
 FUNCTION_WITH_RTX_M_NO_F (vmaxq, SMAX, UMAX, VMAXQ)
 FUNCTION_PRED_P_S_U (vmaxvq, VMAXVQ)
 FUNCTION_PRED_P_S (vminavq, VMINAVQ)
+FUNCTION_WITHOUT_N_NO_U_F (vminaq, VMINAQ)
 FUNCTION_ONLY_F (vminnmaq, VMINNMAQ)
 FUNCTION_PRED_P_F (vminnmavq, VMINNMAVQ)
 FUNCTION (vminnmq, unspec_based_mve_function_exact_insn, (UNKNOWN, UNKNOWN, SMIN, -1, -1, -1, -1, -1, VMINNMQ_M_F, -1, -1, -1))
diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def
index 45e2135452b..48a07c8d888 100644
--- a/gcc/config/arm/arm-mve-builtins-base.def
+++ b/gcc/config/arm/arm-mve-builtins-base.def
@@ -28,9 +28,11 @@ DEF_MVE_FUNCTION (vcreateq, create, all_integer_with_64, none)
 DEF_MVE_FUNCTION (veorq, binary, all_integer, mx_or_none)
 DEF_MVE_FUNCTION (vhaddq, binary_opt_n, all_integer, mx_or_none)
 DEF_MVE_FUNCTION (vhsubq, binary_opt_n, all_integer, mx_or_none)
+DEF_MVE_FUNCTION (vmaxaq, binary_maxamina, all_signed, m_or_none)
 DEF_MVE_FUNCTION (vmaxavq, binary_maxavminav, all_signed, p_or_none)
 DEF_MVE_FUNCTION (vmaxq, binary, all_integer, mx_or_none)
 DEF_MVE_FUNCTION (vmaxvq, binary_maxvminv, all_integer, p_or_none)
+DEF_MVE_FUNCTION (vminaq, binary_maxamina, all_signed, m_or_none)
 DEF_MVE_FUNCTION (vminavq, binary_maxavminav, all_signed, p_or_none)
 DEF_MVE_FUNCTION (vminq, binary, all_integer, mx_or_none)
 DEF_MVE_FUNCTION (vminvq, binary_maxvminv, all_integer, p_or_none)
diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h
index 0242c33ac94..31417435f6f 100644
--- a/gcc/config/arm/arm-mve-builtins-base.h
+++ b/gcc/config/arm/arm-mve-builtins-base.h
@@ -33,6 +33,7 @@ extern const function_base *const vcreateq;
 extern const function_base *const veorq;
 extern const function_base *const vhaddq;
 extern const function_base *const vhsubq;
+extern const function_base *const vmaxaq;
 extern const function_base *const vmaxavq;
 extern const function_base *const vmaxnmaq;
 extern const function_base *const vmaxnmavq;
@@ -40,6 +41,7 @@ extern const function_base *const vmaxnmq;
 extern const function_base *const vmaxnmvq;
 extern const function_base *const vmaxq;
 extern const function_base *const vmaxvq;
+extern const function_base *const vminaq;
 extern const function_base *const vminavq;
 extern const function_base *const vminnmaq;
 extern const function_base *const vminnmavq;
diff --git a/gcc/config/arm/arm-mve-builtins.cc b/gcc/config/arm/arm-mve-builtins.cc
index 5752434c968..9dc762c9fc0 100644
--- a/gcc/config/arm/arm-mve-builtins.cc
+++ b/gcc/config/arm/arm-mve-builtins.cc
@@ -670,7 +670,9 @@ function_instance::has_inactive_argument () const
     return false;
 
   if (mode_suffix_id == MODE_r
+      || base == functions::vmaxaq
       || base == functions::vmaxnmaq
+      || base == functions::vminaq
       || base == functions::vminnmaq
       || base == functions::vmovnbq
       || base == functions::vmovntq
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index d25a9bf69d1..373797689cc 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -65,8 +65,6 @@
 #define vbicq(__a, __b) __arm_vbicq(__a, __b)
 #define vaddvq_p(__a, __p) __arm_vaddvq_p(__a, __p)
 #define vaddvaq(__a, __b) __arm_vaddvaq(__a, __b)
-#define vminaq(__a, __b) __arm_vminaq(__a, __b)
-#define vmaxaq(__a, __b) __arm_vmaxaq(__a, __b)
 #define vbrsrq(__a, __b) __arm_vbrsrq(__a, __b)
 #define vcmpltq(__a, __b) __arm_vcmpltq(__a, __b)
 #define vcmpleq(__a, __b) __arm_vcmpleq(__a, __b)
@@ -115,8 +113,6 @@
 #define vaddvaq_p(__a, __b, __p) __arm_vaddvaq_p(__a, __b, __p)
 #define vsriq(__a, __b, __imm) __arm_vsriq(__a, __b, __imm)
 #define vsliq(__a, __b, __imm) __arm_vsliq(__a, __b, __imm)
-#define vminaq_m(__a, __b, __p) __arm_vminaq_m(__a, __b, __p)
-#define vmaxaq_m(__a, __b, __p) __arm_vmaxaq_m(__a, __b, __p)
 #define vcmpltq_m(__a, __b, __p) __arm_vcmpltq_m(__a, __b, __p)
 #define vcmpleq_m(__a, __b, __p) __arm_vcmpleq_m(__a, __b, __p)
 #define vcmpgtq_m(__a, __b, __p) __arm_vcmpgtq_m(__a, __b, __p)
@@ -468,8 +464,6 @@
 #define vbicq_u8(__a, __b) __arm_vbicq_u8(__a, __b)
 #define vaddvq_p_u8(__a, __p) __arm_vaddvq_p_u8(__a, __p)
 #define vaddvaq_u8(__a, __b) __arm_vaddvaq_u8(__a, __b)
-#define vminaq_s8(__a, __b) __arm_vminaq_s8(__a, __b)
-#define vmaxaq_s8(__a, __b) __arm_vmaxaq_s8(__a, __b)
 #define vbrsrq_n_u8(__a, __b) __arm_vbrsrq_n_u8(__a, __b)
 #define vcmpneq_n_s8(__a, __b) __arm_vcmpneq_n_s8(__a, __b)
 #define vcmpltq_s8(__a, __b) __arm_vcmpltq_s8(__a, __b)
@@ -514,8 +508,6 @@
 #define vbicq_u16(__a, __b) __arm_vbicq_u16(__a, __b)
 #define vaddvq_p_u16(__a, __p) __arm_vaddvq_p_u16(__a, __p)
 #define vaddvaq_u16(__a, __b) __arm_vaddvaq_u16(__a, __b)
-#define vminaq_s16(__a, __b) __arm_vminaq_s16(__a, __b)
-#define vmaxaq_s16(__a, __b) __arm_vmaxaq_s16(__a, __b)
 #define vbrsrq_n_u16(__a, __b) __arm_vbrsrq_n_u16(__a, __b)
 #define vcmpneq_n_s16(__a, __b) __arm_vcmpneq_n_s16(__a, __b)
 #define vcmpltq_s16(__a, __b) __arm_vcmpltq_s16(__a, __b)
@@ -560,8 +552,6 @@
 #define vbicq_u32(__a, __b) __arm_vbicq_u32(__a, __b)
 #define vaddvq_p_u32(__a, __p) __arm_vaddvq_p_u32(__a, __p)
 #define vaddvaq_u32(__a, __b) __arm_vaddvaq_u32(__a, __b)
-#define vminaq_s32(__a, __b) __arm_vminaq_s32(__a, __b)
-#define vmaxaq_s32(__a, __b) __arm_vmaxaq_s32(__a, __b)
 #define vbrsrq_n_u32(__a, __b) __arm_vbrsrq_n_u32(__a, __b)
 #define vcmpneq_n_s32(__a, __b) __arm_vcmpneq_n_s32(__a, __b)
 #define vcmpltq_s32(__a, __b) __arm_vcmpltq_s32(__a, __b)
@@ -717,8 +707,6 @@
 #define vaddvaq_p_u8(__a, __b, __p) __arm_vaddvaq_p_u8(__a, __b, __p)
 #define vsriq_n_u8(__a, __b,  __imm) __arm_vsriq_n_u8(__a, __b,  __imm)
 #define vsliq_n_u8(__a, __b,  __imm) __arm_vsliq_n_u8(__a, __b,  __imm)
-#define vminaq_m_s8(__a, __b, __p) __arm_vminaq_m_s8(__a, __b, __p)
-#define vmaxaq_m_s8(__a, __b, __p) __arm_vmaxaq_m_s8(__a, __b, __p)
 #define vcmpneq_m_s8(__a, __b, __p) __arm_vcmpneq_m_s8(__a, __b, __p)
 #define vcmpneq_m_n_s8(__a, __b, __p) __arm_vcmpneq_m_n_s8(__a, __b, __p)
 #define vcmpltq_m_s8(__a, __b, __p) __arm_vcmpltq_m_s8(__a, __b, __p)
@@ -779,8 +767,6 @@
 #define vaddvaq_p_u16(__a, __b, __p) __arm_vaddvaq_p_u16(__a, __b, __p)
 #define vsriq_n_u16(__a, __b,  __imm) __arm_vsriq_n_u16(__a, __b,  __imm)
 #define vsliq_n_u16(__a, __b,  __imm) __arm_vsliq_n_u16(__a, __b,  __imm)
-#define vminaq_m_s16(__a, __b, __p) __arm_vminaq_m_s16(__a, __b, __p)
-#define vmaxaq_m_s16(__a, __b, __p) __arm_vmaxaq_m_s16(__a, __b, __p)
 #define vcmpneq_m_s16(__a, __b, __p) __arm_vcmpneq_m_s16(__a, __b, __p)
 #define vcmpneq_m_n_s16(__a, __b, __p) __arm_vcmpneq_m_n_s16(__a, __b, __p)
 #define vcmpltq_m_s16(__a, __b, __p) __arm_vcmpltq_m_s16(__a, __b, __p)
@@ -841,8 +827,6 @@
 #define vaddvaq_p_u32(__a, __b, __p) __arm_vaddvaq_p_u32(__a, __b, __p)
 #define vsriq_n_u32(__a, __b,  __imm) __arm_vsriq_n_u32(__a, __b,  __imm)
 #define vsliq_n_u32(__a, __b,  __imm) __arm_vsliq_n_u32(__a, __b,  __imm)
-#define vminaq_m_s32(__a, __b, __p) __arm_vminaq_m_s32(__a, __b, __p)
-#define vmaxaq_m_s32(__a, __b, __p) __arm_vmaxaq_m_s32(__a, __b, __p)
 #define vcmpneq_m_s32(__a, __b, __p) __arm_vcmpneq_m_s32(__a, __b, __p)
 #define vcmpneq_m_n_s32(__a, __b, __p) __arm_vcmpneq_m_n_s32(__a, __b, __p)
 #define vcmpltq_m_s32(__a, __b, __p) __arm_vcmpltq_m_s32(__a, __b, __p)
@@ -2321,20 +2305,6 @@ __arm_vaddvaq_u8 (uint32_t __a, uint8x16_t __b)
   return __builtin_mve_vaddvaq_uv16qi (__a, __b);
 }
 
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminaq_s8 (uint8x16_t __a, int8x16_t __b)
-{
-  return __builtin_mve_vminaq_sv16qi (__a, __b);
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxaq_s8 (uint8x16_t __a, int8x16_t __b)
-{
-  return __builtin_mve_vmaxaq_sv16qi (__a, __b);
-}
-
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vbrsrq_n_u8 (uint8x16_t __a, int32_t __b)
@@ -2645,20 +2615,6 @@ __arm_vaddvaq_u16 (uint32_t __a, uint16x8_t __b)
   return __builtin_mve_vaddvaq_uv8hi (__a, __b);
 }
 
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminaq_s16 (uint16x8_t __a, int16x8_t __b)
-{
-  return __builtin_mve_vminaq_sv8hi (__a, __b);
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxaq_s16 (uint16x8_t __a, int16x8_t __b)
-{
-  return __builtin_mve_vmaxaq_sv8hi (__a, __b);
-}
-
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vbrsrq_n_u16 (uint16x8_t __a, int32_t __b)
@@ -2969,20 +2925,6 @@ __arm_vaddvaq_u32 (uint32_t __a, uint32x4_t __b)
   return __builtin_mve_vaddvaq_uv4si (__a, __b);
 }
 
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminaq_s32 (uint32x4_t __a, int32x4_t __b)
-{
-  return __builtin_mve_vminaq_sv4si (__a, __b);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxaq_s32 (uint32x4_t __a, int32x4_t __b)
-{
-  return __builtin_mve_vmaxaq_sv4si (__a, __b);
-}
-
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vbrsrq_n_u32 (uint32x4_t __a, int32_t __b)
@@ -3716,20 +3658,6 @@ __arm_vsliq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm)
   return __builtin_mve_vsliq_n_uv16qi (__a, __b, __imm);
 }
 
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminaq_m_s8 (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminaq_m_sv16qi (__a, __b, __p);
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxaq_m_s8 (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxaq_m_sv16qi (__a, __b, __p);
-}
-
 __extension__ extern __inline mve_pred16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmpneq_m_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
@@ -4150,20 +4078,6 @@ __arm_vsliq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm)
   return __builtin_mve_vsliq_n_uv8hi (__a, __b, __imm);
 }
 
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminaq_m_s16 (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminaq_m_sv8hi (__a, __b, __p);
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxaq_m_s16 (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxaq_m_sv8hi (__a, __b, __p);
-}
-
 __extension__ extern __inline mve_pred16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmpneq_m_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
@@ -4584,20 +4498,6 @@ __arm_vsliq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm)
   return __builtin_mve_vsliq_n_uv4si (__a, __b, __imm);
 }
 
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminaq_m_s32 (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vminaq_m_sv4si (__a, __b, __p);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxaq_m_s32 (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
-{
-  return __builtin_mve_vmaxaq_m_sv4si (__a, __b, __p);
-}
-
 __extension__ extern __inline mve_pred16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmpneq_m_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
@@ -12254,20 +12154,6 @@ __arm_vaddvaq (uint32_t __a, uint8x16_t __b)
  return __arm_vaddvaq_u8 (__a, __b);
 }
 
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminaq (uint8x16_t __a, int8x16_t __b)
-{
- return __arm_vminaq_s8 (__a, __b);
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxaq (uint8x16_t __a, int8x16_t __b)
-{
- return __arm_vmaxaq_s8 (__a, __b);
-}
-
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vbrsrq (uint8x16_t __a, int32_t __b)
@@ -12576,20 +12462,6 @@ __arm_vaddvaq (uint32_t __a, uint16x8_t __b)
  return __arm_vaddvaq_u16 (__a, __b);
 }
 
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminaq (uint16x8_t __a, int16x8_t __b)
-{
- return __arm_vminaq_s16 (__a, __b);
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxaq (uint16x8_t __a, int16x8_t __b)
-{
- return __arm_vmaxaq_s16 (__a, __b);
-}
-
 __extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vbrsrq (uint16x8_t __a, int32_t __b)
@@ -12898,20 +12770,6 @@ __arm_vaddvaq (uint32_t __a, uint32x4_t __b)
  return __arm_vaddvaq_u32 (__a, __b);
 }
 
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminaq (uint32x4_t __a, int32x4_t __b)
-{
- return __arm_vminaq_s32 (__a, __b);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxaq (uint32x4_t __a, int32x4_t __b)
-{
- return __arm_vmaxaq_s32 (__a, __b);
-}
-
 __extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vbrsrq (uint32x4_t __a, int32_t __b)
@@ -13605,20 +13463,6 @@ __arm_vsliq (uint8x16_t __a, uint8x16_t __b, const int __imm)
  return __arm_vsliq_n_u8 (__a, __b, __imm);
 }
 
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminaq_m (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
-{
- return __arm_vminaq_m_s8 (__a, __b, __p);
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxaq_m (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxaq_m_s8 (__a, __b, __p);
-}
-
 __extension__ extern __inline mve_pred16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmpneq_m (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
@@ -14039,20 +13883,6 @@ __arm_vsliq (uint16x8_t __a, uint16x8_t __b, const int __imm)
  return __arm_vsliq_n_u16 (__a, __b, __imm);
 }
 
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminaq_m (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vminaq_m_s16 (__a, __b, __p);
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxaq_m (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxaq_m_s16 (__a, __b, __p);
-}
-
 __extension__ extern __inline mve_pred16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmpneq_m (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
@@ -14473,20 +14303,6 @@ __arm_vsliq (uint32x4_t __a, uint32x4_t __b, const int __imm)
  return __arm_vsliq_n_u32 (__a, __b, __imm);
 }
 
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminaq_m (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vminaq_m_s32 (__a, __b, __p);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxaq_m (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
-{
- return __arm_vmaxaq_m_s32 (__a, __b, __p);
-}
-
 __extension__ extern __inline mve_pred16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vcmpneq_m (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
@@ -21069,20 +20885,6 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot90_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot90_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
 
-#define __arm_vminaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminaq_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminaq_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminaq_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
-
-#define __arm_vmaxaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxaq_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxaq_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxaq_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
-
 #define __arm_vmullbq_int(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
@@ -21109,20 +20911,6 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlcq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \
   int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlcq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));})
 
-#define __arm_vmaxaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxaq_m_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxaq_m_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxaq_m_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));})
-
-#define __arm_vminaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminaq_m_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminaq_m_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminaq_m_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));})
-
 #define __arm_vmlaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
@@ -22254,20 +22042,6 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_int_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmullbq_int_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)));})
 
-#define __arm_vminaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminaq_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminaq_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminaq_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
-
-#define __arm_vmaxaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxaq_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxaq_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxaq_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));})
-
 #define __arm_vhcaddq_rot90(p0,p1) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
@@ -22624,13 +22398,6 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vdupq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), (uint16_t) __p1, p2), \
   int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vdupq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), (uint32_t) __p1, p2));})
 
-#define __arm_vmaxaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxaq_m_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxaq_m_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxaq_m_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));})
-
 #define __arm_vmlaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   __typeof(p2) __p2 = (p2); \
@@ -22697,13 +22464,6 @@ extern void *__ARM_undef;
   int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmladhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t)), \
   int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmladhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t)));})
 
-#define __arm_vminaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
-  __typeof(p1) __p1 = (p1); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-  int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminaq_m_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \
-  int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminaq_m_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \
-  int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminaq_m_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2));})
-
 #define __arm_vmovlbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
   __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
-- 
2.34.1

RE: [PATCH 06/16] arm: add smax/smin expanders for v*hf

[Kyrylo Tkachov]

> -----Original Message-----
> From: Christophe Lyon <christophe.lyon@arm.com>
> Sent: Tuesday, May 9, 2023 1:19 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>;
> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
> <Richard.Sandiford@arm.com>
> Cc: Christophe Lyon <Christophe.Lyon@arm.com>
> Subject: [PATCH 06/16] arm: add smax/smin expanders for v*hf
> 
> This patch adds the missing expanders for smax/smin for v*hf modes.
> 
> 2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>
> 
> 	gcc/
> 	* config/arm/vec-common.md (smin<mode>3): New.
> 	(smax<mode>3): New.
> ---
>  gcc/config/arm/vec-common.md | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-
> common.md
> index b5fc86fdf28..1f9b7992da4 100644
> --- a/gcc/config/arm/vec-common.md
> +++ b/gcc/config/arm/vec-common.md
> @@ -116,6 +116,13 @@ (define_expand "smin<mode>3"
>     "ARM_HAVE_<MODE>_ARITH"
>  )
> 
> +(define_expand "smin<mode>3"
> +  [(set (match_operand:VH 0 "s_register_operand")
> +	(smin:VH (match_operand:VH 1 "s_register_operand")
> +		 (match_operand:VH 2 "s_register_operand")))]
> +   "ARM_HAVE_<MODE>_ARITH"
> +)
> +
>  (define_expand "umin<mode>3"
>    [(set (match_operand:VINTW 0 "s_register_operand")
>  	(umin:VINTW (match_operand:VINTW 1 "s_register_operand")
> @@ -130,6 +137,13 @@ (define_expand "smax<mode>3"
>     "ARM_HAVE_<MODE>_ARITH"
>  )
> 
> +(define_expand "smax<mode>3"
> +  [(set (match_operand:VH 0 "s_register_operand")
> +	(smax:VH (match_operand:VH 1 "s_register_operand")
> +		 (match_operand:VH 2 "s_register_operand")))]
> +   "ARM_HAVE_<MODE>_ARITH"
> +)

We already have expanders for smin and smax, can we just extend their mode iterators to include the VH modes?
The ARM_HAVE_<MODE>_ARITH checks should still gate them properly and we could avoid adding more bloat in this file.
Thanks,
Kyrill

> +
>  (define_expand "umax<mode>3"
>    [(set (match_operand:VINTW 0 "s_register_operand")
>  	(umax:VINTW (match_operand:VINTW 1 "s_register_operand")
> --
> 2.34.1

RE: [PATCH 01/16] arm: [MVE intrinsics] add binary_maxvminv shape

[Kyrylo Tkachov]

Hi Christophe,

> -----Original Message-----
> From: Christophe Lyon <christophe.lyon@arm.com>
> Sent: Tuesday, May 9, 2023 1:19 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>;
> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
> <Richard.Sandiford@arm.com>
> Cc: Christophe Lyon <Christophe.Lyon@arm.com>
> Subject: [PATCH 01/16] arm: [MVE intrinsics] add binary_maxvminv shape
> 
> This patch adds the binary_maxvminv shape description.

This patch series is fairly mechanical (that's not to say simple!) and in line with the other series in this area.
You obviously know what you're doing here so I'm comfortable approving it.
I did have a look at the patches individually and with the comment on patch 06/16 addressed this series is ok for trunk.
Thanks,
Kyrill

> 
> 2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>
> 
> 	gcc/
> 	* config/arm/arm-mve-builtins-shapes.cc (binary_maxvminv): New.
> 	* config/arm/arm-mve-builtins-shapes.h (binary_maxvminv): New.
> ---
>  gcc/config/arm/arm-mve-builtins-shapes.cc | 30 +++++++++++++++++++++++
>  gcc/config/arm/arm-mve-builtins-shapes.h  |  1 +
>  2 files changed, 31 insertions(+)
> 
> diff --git a/gcc/config/arm/arm-mve-builtins-shapes.cc b/gcc/config/arm/arm-
> mve-builtins-shapes.cc
> index 1d43b8871bf..19c3c47a20e 100644
> --- a/gcc/config/arm/arm-mve-builtins-shapes.cc
> +++ b/gcc/config/arm/arm-mve-builtins-shapes.cc
> @@ -401,6 +401,36 @@ struct binary_rshift_def : public
> overloaded_base<0>
>  };
>  SHAPE (binary_rshift)
> 
> +/* <S0>_t vfoo[_<t0>](<S0>_t, <T0>_t)
> +
> +   Example: vmaxvq.
> +   int8_t [__arm_]vmaxvq[_s8](int8_t a, int8x16_t b)
> +   int8_t [__arm_]vmaxvq_p[_s8](int8_t a, int8x16_t b, mve_pred16_t p)  */
> +struct binary_maxvminv_def : public overloaded_base<0>
> +{
> +  void
> +  build (function_builder &b, const function_group_info &group,
> +	 bool preserve_user_namespace) const override
> +  {
> +    b.add_overloaded_functions (group, MODE_none,
> preserve_user_namespace);
> +    build_all (b, "s0,s0,v0", group, MODE_none, preserve_user_namespace);
> +  }
> +
> +  tree
> +  resolve (function_resolver &r) const override
> +  {
> +    unsigned int i, nargs;
> +    type_suffix_index type;
> +    if (!r.check_gp_argument (2, i, nargs)
> +	|| !r.require_derived_scalar_type (0, r.SAME_TYPE_CLASS)
> +	|| (type = r.infer_vector_type (1)) == NUM_TYPE_SUFFIXES)
> +      return error_mark_node;
> +
> +    return r.resolve_to (r.mode_suffix_id, type);
> +  }
> +};
> +SHAPE (binary_maxvminv)
> +
>  /* <T0:half>_t vfoo[_t0](<T0:half>_t, <T0>_t)
> 
>     Example: vmovnbq.
> diff --git a/gcc/config/arm/arm-mve-builtins-shapes.h b/gcc/config/arm/arm-
> mve-builtins-shapes.h
> index dd2597dc6f5..9debf1d8733 100644
> --- a/gcc/config/arm/arm-mve-builtins-shapes.h
> +++ b/gcc/config/arm/arm-mve-builtins-shapes.h
> @@ -37,6 +37,7 @@ namespace arm_mve
>      extern const function_shape *const binary;
>      extern const function_shape *const binary_lshift;
>      extern const function_shape *const binary_lshift_r;
> +    extern const function_shape *const binary_maxvminv;
>      extern const function_shape *const binary_move_narrow;
>      extern const function_shape *const binary_move_narrow_unsigned;
>      extern const function_shape *const binary_opt_n;
> --
> 2.34.1

Re: [PATCH 06/16] arm: add smax/smin expanders for v*hf

[Christophe Lyon]

On 5/9/23 15:48, Kyrylo Tkachov wrote:
> 
> 
>> -----Original Message-----
>> From: Christophe Lyon <christophe.lyon@arm.com>
>> Sent: Tuesday, May 9, 2023 1:19 PM
>> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>;
>> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
>> <Richard.Sandiford@arm.com>
>> Cc: Christophe Lyon <Christophe.Lyon@arm.com>
>> Subject: [PATCH 06/16] arm: add smax/smin expanders for v*hf
>>
>> This patch adds the missing expanders for smax/smin for v*hf modes.
>>
>> 2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>
>>
>> 	gcc/
>> 	* config/arm/vec-common.md (smin<mode>3): New.
>> 	(smax<mode>3): New.
>> ---
>>   gcc/config/arm/vec-common.md | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
>>
>> diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-
>> common.md
>> index b5fc86fdf28..1f9b7992da4 100644
>> --- a/gcc/config/arm/vec-common.md
>> +++ b/gcc/config/arm/vec-common.md
>> @@ -116,6 +116,13 @@ (define_expand "smin<mode>3"
>>      "ARM_HAVE_<MODE>_ARITH"
>>   )
>>
>> +(define_expand "smin<mode>3"
>> +  [(set (match_operand:VH 0 "s_register_operand")
>> +	(smin:VH (match_operand:VH 1 "s_register_operand")
>> +		 (match_operand:VH 2 "s_register_operand")))]
>> +   "ARM_HAVE_<MODE>_ARITH"
>> +)
>> +
>>   (define_expand "umin<mode>3"
>>     [(set (match_operand:VINTW 0 "s_register_operand")
>>   	(umin:VINTW (match_operand:VINTW 1 "s_register_operand")
>> @@ -130,6 +137,13 @@ (define_expand "smax<mode>3"
>>      "ARM_HAVE_<MODE>_ARITH"
>>   )
>>
>> +(define_expand "smax<mode>3"
>> +  [(set (match_operand:VH 0 "s_register_operand")
>> +	(smax:VH (match_operand:VH 1 "s_register_operand")
>> +		 (match_operand:VH 2 "s_register_operand")))]
>> +   "ARM_HAVE_<MODE>_ARITH"
>> +)
> 
> We already have expanders for smin and smax, can we just extend their mode iterators to include the VH modes?
> The ARM_HAVE_<MODE>_ARITH checks should still gate them properly and we could avoid adding more bloat in this file.

I opted for the most localized changes, to avoid breaking Neon since 
there are already so many similar iterators ;-)

It seems I can just use the existing VDQWH, which seems to be VALLW (as 
already used by smax) plus V8HF/V4HF which is just what we want.

Also, ISTM that VALLW == VDQW, am I misreading?

Thanks,

Christophe


> Thanks,
> Kyrill
> 
>> +
>>   (define_expand "umax<mode>3"
>>     [(set (match_operand:VINTW 0 "s_register_operand")
>>   	(umax:VINTW (match_operand:VINTW 1 "s_register_operand")
>> --
>> 2.34.1
> 

RE: [PATCH 06/16] arm: add smax/smin expanders for v*hf

[Kyrylo Tkachov]

> -----Original Message-----
> From: Christophe Lyon <Christophe.Lyon@arm.com>
> Sent: Tuesday, May 9, 2023 6:18 PM
> To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; gcc-patches@gcc.gnu.org;
> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
> <Richard.Sandiford@arm.com>
> Subject: Re: [PATCH 06/16] arm: add smax/smin expanders for v*hf
> 
> 
> 
> On 5/9/23 15:48, Kyrylo Tkachov wrote:
> >
> >
> >> -----Original Message-----
> >> From: Christophe Lyon <christophe.lyon@arm.com>
> >> Sent: Tuesday, May 9, 2023 1:19 PM
> >> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>;
> >> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
> >> <Richard.Sandiford@arm.com>
> >> Cc: Christophe Lyon <Christophe.Lyon@arm.com>
> >> Subject: [PATCH 06/16] arm: add smax/smin expanders for v*hf
> >>
> >> This patch adds the missing expanders for smax/smin for v*hf modes.
> >>
> >> 2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>
> >>
> >> 	gcc/
> >> 	* config/arm/vec-common.md (smin<mode>3): New.
> >> 	(smax<mode>3): New.
> >> ---
> >>   gcc/config/arm/vec-common.md | 14 ++++++++++++++
> >>   1 file changed, 14 insertions(+)
> >>
> >> diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-
> >> common.md
> >> index b5fc86fdf28..1f9b7992da4 100644
> >> --- a/gcc/config/arm/vec-common.md
> >> +++ b/gcc/config/arm/vec-common.md
> >> @@ -116,6 +116,13 @@ (define_expand "smin<mode>3"
> >>      "ARM_HAVE_<MODE>_ARITH"
> >>   )
> >>
> >> +(define_expand "smin<mode>3"
> >> +  [(set (match_operand:VH 0 "s_register_operand")
> >> +	(smin:VH (match_operand:VH 1 "s_register_operand")
> >> +		 (match_operand:VH 2 "s_register_operand")))]
> >> +   "ARM_HAVE_<MODE>_ARITH"
> >> +)
> >> +
> >>   (define_expand "umin<mode>3"
> >>     [(set (match_operand:VINTW 0 "s_register_operand")
> >>   	(umin:VINTW (match_operand:VINTW 1 "s_register_operand")
> >> @@ -130,6 +137,13 @@ (define_expand "smax<mode>3"
> >>      "ARM_HAVE_<MODE>_ARITH"
> >>   )
> >>
> >> +(define_expand "smax<mode>3"
> >> +  [(set (match_operand:VH 0 "s_register_operand")
> >> +	(smax:VH (match_operand:VH 1 "s_register_operand")
> >> +		 (match_operand:VH 2 "s_register_operand")))]
> >> +   "ARM_HAVE_<MODE>_ARITH"
> >> +)
> >
> > We already have expanders for smin and smax, can we just extend their
> mode iterators to include the VH modes?
> > The ARM_HAVE_<MODE>_ARITH checks should still gate them properly and
> we could avoid adding more bloat in this file.
> 
> I opted for the most localized changes, to avoid breaking Neon since
> there are already so many similar iterators ;-)
> 
> It seems I can just use the existing VDQWH, which seems to be VALLW (as
> already used by smax) plus V8HF/V4HF which is just what we want.

Yes, let's use that.

> 
> Also, ISTM that VALLW == VDQW, am I misreading?

They do look the same. I'm generally okay with removing duplicate iterators unless their name seems to have a very specific meaning that would be confusing in other contexts.
But VALLW and VDQW seem equally confusing 😉
Thanks,
KYrill

> 
> Thanks,
> 
> Christophe
> 
> 
> > Thanks,
> > Kyrill
> >
> >> +
> >>   (define_expand "umax<mode>3"
> >>     [(set (match_operand:VINTW 0 "s_register_operand")
> >>   	(umax:VINTW (match_operand:VINTW 1 "s_register_operand")
> >> --
> >> 2.34.1
> >

Re: [PATCH 06/16] arm: add smax/smin expanders for v*hf

[Christophe Lyon]

On 5/9/23 19:31, Kyrylo Tkachov wrote:
> 
> 
>> -----Original Message-----
>> From: Christophe Lyon <Christophe.Lyon@arm.com>
>> Sent: Tuesday, May 9, 2023 6:18 PM
>> To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; gcc-patches@gcc.gnu.org;
>> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
>> <Richard.Sandiford@arm.com>
>> Subject: Re: [PATCH 06/16] arm: add smax/smin expanders for v*hf
>>
>>
>>
>> On 5/9/23 15:48, Kyrylo Tkachov wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: Christophe Lyon <christophe.lyon@arm.com>
>>>> Sent: Tuesday, May 9, 2023 1:19 PM
>>>> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>;
>>>> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
>>>> <Richard.Sandiford@arm.com>
>>>> Cc: Christophe Lyon <Christophe.Lyon@arm.com>
>>>> Subject: [PATCH 06/16] arm: add smax/smin expanders for v*hf
>>>>
>>>> This patch adds the missing expanders for smax/smin for v*hf modes.
>>>>
>>>> 2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>
>>>>
>>>> 	gcc/
>>>> 	* config/arm/vec-common.md (smin<mode>3): New.
>>>> 	(smax<mode>3): New.
>>>> ---
>>>>    gcc/config/arm/vec-common.md | 14 ++++++++++++++
>>>>    1 file changed, 14 insertions(+)
>>>>
>>>> diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-
>>>> common.md
>>>> index b5fc86fdf28..1f9b7992da4 100644
>>>> --- a/gcc/config/arm/vec-common.md
>>>> +++ b/gcc/config/arm/vec-common.md
>>>> @@ -116,6 +116,13 @@ (define_expand "smin<mode>3"
>>>>       "ARM_HAVE_<MODE>_ARITH"
>>>>    )
>>>>
>>>> +(define_expand "smin<mode>3"
>>>> +  [(set (match_operand:VH 0 "s_register_operand")
>>>> +	(smin:VH (match_operand:VH 1 "s_register_operand")
>>>> +		 (match_operand:VH 2 "s_register_operand")))]
>>>> +   "ARM_HAVE_<MODE>_ARITH"
>>>> +)
>>>> +
>>>>    (define_expand "umin<mode>3"
>>>>      [(set (match_operand:VINTW 0 "s_register_operand")
>>>>    	(umin:VINTW (match_operand:VINTW 1 "s_register_operand")
>>>> @@ -130,6 +137,13 @@ (define_expand "smax<mode>3"
>>>>       "ARM_HAVE_<MODE>_ARITH"
>>>>    )
>>>>
>>>> +(define_expand "smax<mode>3"
>>>> +  [(set (match_operand:VH 0 "s_register_operand")
>>>> +	(smax:VH (match_operand:VH 1 "s_register_operand")
>>>> +		 (match_operand:VH 2 "s_register_operand")))]
>>>> +   "ARM_HAVE_<MODE>_ARITH"
>>>> +)
>>>
>>> We already have expanders for smin and smax, can we just extend their
>> mode iterators to include the VH modes?
>>> The ARM_HAVE_<MODE>_ARITH checks should still gate them properly and
>> we could avoid adding more bloat in this file.
>>
>> I opted for the most localized changes, to avoid breaking Neon since
>> there are already so many similar iterators ;-)
>>
>> It seems I can just use the existing VDQWH, which seems to be VALLW (as
>> already used by smax) plus V8HF/V4HF which is just what we want.
> 
> Yes, let's use that.
> 
Thanks, I'll do that. OK to push with change, or do you want me to post 
the updated patch?

>>
>> Also, ISTM that VALLW == VDQW, am I misreading?
> 
> They do look the same. I'm generally okay with removing duplicate iterators unless their name seems to have a very specific meaning that would be confusing in other contexts.
> But VALLW and VDQW seem equally confusing 😉
Thanks for confirming the "confusing" bit :-)

Christophe

> Thanks,
> KYrill
> 
>>
>> Thanks,
>>
>> Christophe
>>
>>
>>> Thanks,
>>> Kyrill
>>>
>>>> +
>>>>    (define_expand "umax<mode>3"
>>>>      [(set (match_operand:VINTW 0 "s_register_operand")
>>>>    	(umax:VINTW (match_operand:VINTW 1 "s_register_operand")
>>>> --
>>>> 2.34.1
>>>

RE: [PATCH 06/16] arm: add smax/smin expanders for v*hf

[Kyrylo Tkachov]

> -----Original Message-----
> From: Christophe Lyon <Christophe.Lyon@arm.com>
> Sent: Tuesday, May 9, 2023 6:33 PM
> To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; gcc-patches@gcc.gnu.org;
> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
> <Richard.Sandiford@arm.com>
> Subject: Re: [PATCH 06/16] arm: add smax/smin expanders for v*hf
> 
> 
> 
> On 5/9/23 19:31, Kyrylo Tkachov wrote:
> >
> >
> >> -----Original Message-----
> >> From: Christophe Lyon <Christophe.Lyon@arm.com>
> >> Sent: Tuesday, May 9, 2023 6:18 PM
> >> To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; gcc-patches@gcc.gnu.org;
> >> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
> >> <Richard.Sandiford@arm.com>
> >> Subject: Re: [PATCH 06/16] arm: add smax/smin expanders for v*hf
> >>
> >>
> >>
> >> On 5/9/23 15:48, Kyrylo Tkachov wrote:
> >>>
> >>>
> >>>> -----Original Message-----
> >>>> From: Christophe Lyon <christophe.lyon@arm.com>
> >>>> Sent: Tuesday, May 9, 2023 1:19 PM
> >>>> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov
> <Kyrylo.Tkachov@arm.com>;
> >>>> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
> >>>> <Richard.Sandiford@arm.com>
> >>>> Cc: Christophe Lyon <Christophe.Lyon@arm.com>
> >>>> Subject: [PATCH 06/16] arm: add smax/smin expanders for v*hf
> >>>>
> >>>> This patch adds the missing expanders for smax/smin for v*hf modes.
> >>>>
> >>>> 2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>
> >>>>
> >>>> 	gcc/
> >>>> 	* config/arm/vec-common.md (smin<mode>3): New.
> >>>> 	(smax<mode>3): New.
> >>>> ---
> >>>>    gcc/config/arm/vec-common.md | 14 ++++++++++++++
> >>>>    1 file changed, 14 insertions(+)
> >>>>
> >>>> diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-
> >>>> common.md
> >>>> index b5fc86fdf28..1f9b7992da4 100644
> >>>> --- a/gcc/config/arm/vec-common.md
> >>>> +++ b/gcc/config/arm/vec-common.md
> >>>> @@ -116,6 +116,13 @@ (define_expand "smin<mode>3"
> >>>>       "ARM_HAVE_<MODE>_ARITH"
> >>>>    )
> >>>>
> >>>> +(define_expand "smin<mode>3"
> >>>> +  [(set (match_operand:VH 0 "s_register_operand")
> >>>> +	(smin:VH (match_operand:VH 1 "s_register_operand")
> >>>> +		 (match_operand:VH 2 "s_register_operand")))]
> >>>> +   "ARM_HAVE_<MODE>_ARITH"
> >>>> +)
> >>>> +
> >>>>    (define_expand "umin<mode>3"
> >>>>      [(set (match_operand:VINTW 0 "s_register_operand")
> >>>>    	(umin:VINTW (match_operand:VINTW 1 "s_register_operand")
> >>>> @@ -130,6 +137,13 @@ (define_expand "smax<mode>3"
> >>>>       "ARM_HAVE_<MODE>_ARITH"
> >>>>    )
> >>>>
> >>>> +(define_expand "smax<mode>3"
> >>>> +  [(set (match_operand:VH 0 "s_register_operand")
> >>>> +	(smax:VH (match_operand:VH 1 "s_register_operand")
> >>>> +		 (match_operand:VH 2 "s_register_operand")))]
> >>>> +   "ARM_HAVE_<MODE>_ARITH"
> >>>> +)
> >>>
> >>> We already have expanders for smin and smax, can we just extend their
> >> mode iterators to include the VH modes?
> >>> The ARM_HAVE_<MODE>_ARITH checks should still gate them properly
> and
> >> we could avoid adding more bloat in this file.
> >>
> >> I opted for the most localized changes, to avoid breaking Neon since
> >> there are already so many similar iterators ;-)
> >>
> >> It seems I can just use the existing VDQWH, which seems to be VALLW (as
> >> already used by smax) plus V8HF/V4HF which is just what we want.
> >
> > Yes, let's use that.
> >
> Thanks, I'll do that. OK to push with change, or do you want me to post
> the updated patch?

Please post the updated patch for archival on the list and commit the series.
Thanks,
Kyrill

> 
> >>
> >> Also, ISTM that VALLW == VDQW, am I misreading?
> >
> > They do look the same. I'm generally okay with removing duplicate iterators
> unless their name seems to have a very specific meaning that would be
> confusing in other contexts.
> > But VALLW and VDQW seem equally confusing 😉
> Thanks for confirming the "confusing" bit :-)
> 
> Christophe
> 
> > Thanks,
> > KYrill
> >
> >>
> >> Thanks,
> >>
> >> Christophe
> >>
> >>
> >>> Thanks,
> >>> Kyrill
> >>>
> >>>> +
> >>>>    (define_expand "umax<mode>3"
> >>>>      [(set (match_operand:VINTW 0 "s_register_operand")
> >>>>    	(umax:VINTW (match_operand:VINTW 1 "s_register_operand")
> >>>> --
> >>>> 2.34.1
> >>>

[PATCH v2 06/16] arm: add smax/smin expanders for v*hf

[Christophe Lyon]

This patch adds the missing expanders for smax/smin for v*hf modes,
by using the VDQWH iterator instead of VALLW.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/vec-common.md (smin<mode>3): Use VDQWH iterator.
	(smax<mode>3): Likewise.
---
 gcc/config/arm/vec-common.md | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index b5fc86fdf28..6183c931e36 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -110,9 +110,9 @@ (define_expand "mul<mode>3"
 )
 
 (define_expand "smin<mode>3"
-  [(set (match_operand:VALLW 0 "s_register_operand")
-	(smin:VALLW (match_operand:VALLW 1 "s_register_operand")
-		    (match_operand:VALLW 2 "s_register_operand")))]
+  [(set (match_operand:VDQWH 0 "s_register_operand")
+	(smin:VDQWH (match_operand:VDQWH 1 "s_register_operand")
+		    (match_operand:VDQWH 2 "s_register_operand")))]
    "ARM_HAVE_<MODE>_ARITH"
 )
 
@@ -124,9 +124,9 @@ (define_expand "umin<mode>3"
 )
 
 (define_expand "smax<mode>3"
-  [(set (match_operand:VALLW 0 "s_register_operand")
-	(smax:VALLW (match_operand:VALLW 1 "s_register_operand")
-		    (match_operand:VALLW 2 "s_register_operand")))]
+  [(set (match_operand:VDQWH 0 "s_register_operand")
+	(smax:VDQWH (match_operand:VDQWH 1 "s_register_operand")
+		    (match_operand:VDQWH 2 "s_register_operand")))]
    "ARM_HAVE_<MODE>_ARITH"
 )
 
-- 
2.34.1

Re: [PATCH 01/16] arm: [MVE intrinsics] add binary_maxvminv shape

[Christophe Lyon]

On 5/9/23 15:50, Kyrylo Tkachov wrote:
> Hi Christophe,
> 
>> -----Original Message-----
>> From: Christophe Lyon <christophe.lyon@arm.com>
>> Sent: Tuesday, May 9, 2023 1:19 PM
>> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>;
>> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
>> <Richard.Sandiford@arm.com>
>> Cc: Christophe Lyon <Christophe.Lyon@arm.com>
>> Subject: [PATCH 01/16] arm: [MVE intrinsics] add binary_maxvminv shape
>>
>> This patch adds the binary_maxvminv shape description.
> 
> This patch series is fairly mechanical (that's not to say simple!) and in line with the other series in this area.

Yeah it took me a bit of time & thinking to put the series in a 
mechanical shape, hopefully easy to review.

> You obviously know what you're doing here so I'm comfortable approving it.
> I did have a look at the patches individually and with the comment on patch 06/16 addressed this series is ok for trunk.

Thanks,

Christophe

> Thanks,
> Kyrill
> 
>>
>> 2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>
>>
>> 	gcc/
>> 	* config/arm/arm-mve-builtins-shapes.cc (binary_maxvminv): New.
>> 	* config/arm/arm-mve-builtins-shapes.h (binary_maxvminv): New.
>> ---
>>   gcc/config/arm/arm-mve-builtins-shapes.cc | 30 +++++++++++++++++++++++
>>   gcc/config/arm/arm-mve-builtins-shapes.h  |  1 +
>>   2 files changed, 31 insertions(+)
>>
>> diff --git a/gcc/config/arm/arm-mve-builtins-shapes.cc b/gcc/config/arm/arm-
>> mve-builtins-shapes.cc
>> index 1d43b8871bf..19c3c47a20e 100644
>> --- a/gcc/config/arm/arm-mve-builtins-shapes.cc
>> +++ b/gcc/config/arm/arm-mve-builtins-shapes.cc
>> @@ -401,6 +401,36 @@ struct binary_rshift_def : public
>> overloaded_base<0>
>>   };
>>   SHAPE (binary_rshift)
>>
>> +/* <S0>_t vfoo[_<t0>](<S0>_t, <T0>_t)
>> +
>> +   Example: vmaxvq.
>> +   int8_t [__arm_]vmaxvq[_s8](int8_t a, int8x16_t b)
>> +   int8_t [__arm_]vmaxvq_p[_s8](int8_t a, int8x16_t b, mve_pred16_t p)  */
>> +struct binary_maxvminv_def : public overloaded_base<0>
>> +{
>> +  void
>> +  build (function_builder &b, const function_group_info &group,
>> +	 bool preserve_user_namespace) const override
>> +  {
>> +    b.add_overloaded_functions (group, MODE_none,
>> preserve_user_namespace);
>> +    build_all (b, "s0,s0,v0", group, MODE_none, preserve_user_namespace);
>> +  }
>> +
>> +  tree
>> +  resolve (function_resolver &r) const override
>> +  {
>> +    unsigned int i, nargs;
>> +    type_suffix_index type;
>> +    if (!r.check_gp_argument (2, i, nargs)
>> +	|| !r.require_derived_scalar_type (0, r.SAME_TYPE_CLASS)
>> +	|| (type = r.infer_vector_type (1)) == NUM_TYPE_SUFFIXES)
>> +      return error_mark_node;
>> +
>> +    return r.resolve_to (r.mode_suffix_id, type);
>> +  }
>> +};
>> +SHAPE (binary_maxvminv)
>> +
>>   /* <T0:half>_t vfoo[_t0](<T0:half>_t, <T0>_t)
>>
>>      Example: vmovnbq.
>> diff --git a/gcc/config/arm/arm-mve-builtins-shapes.h b/gcc/config/arm/arm-
>> mve-builtins-shapes.h
>> index dd2597dc6f5..9debf1d8733 100644
>> --- a/gcc/config/arm/arm-mve-builtins-shapes.h
>> +++ b/gcc/config/arm/arm-mve-builtins-shapes.h
>> @@ -37,6 +37,7 @@ namespace arm_mve
>>       extern const function_shape *const binary;
>>       extern const function_shape *const binary_lshift;
>>       extern const function_shape *const binary_lshift_r;
>> +    extern const function_shape *const binary_maxvminv;
>>       extern const function_shape *const binary_move_narrow;
>>       extern const function_shape *const binary_move_narrow_unsigned;
>>       extern const function_shape *const binary_opt_n;
>> --
>> 2.34.1
>