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* [PATCH] RISC-V: Remove FRM_REGNUM dependency for rtx conversions
@ 2023-05-24 11:26 juzhe.zhong
  2023-05-25  4:02 ` Kito Cheng
  0 siblings, 1 reply; 3+ messages in thread
From: juzhe.zhong @ 2023-05-24 11:26 UTC (permalink / raw)
  To: gcc-patches; +Cc: kito.cheng, palmer, rdapp.gcc, jeffreyalaw, Juzhe-Zhong

From: Juzhe-Zhong <juzhe.zhong@rivai.ai>

According to RVV ISA:
The conversions use the dynamic rounding mode in frm, except for the rtz variants, which round towards zero.

So rtz conversion patterns should not have FRM dependency.

We can't support mode switching for FRM yet since rvv intrinsic doc is not updated but
I think this patch is correct.

gcc/ChangeLog:

        * config/riscv/vector.md: Remove FRM_REGNUM dependency in rtz instructions.

---
 gcc/config/riscv/vector.md | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 9afef0d12bc..15f66efaa48 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7072,10 +7072,8 @@
 	     (match_operand 5 "const_int_operand"            "  i,  i,  i,  i")
 	     (match_operand 6 "const_int_operand"            "  i,  i,  i,  i")
 	     (match_operand 7 "const_int_operand"            "  i,  i,  i,  i")
-	     (match_operand 8 "const_int_operand"            "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)
-	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_fix:<VCONVERT>
 	     (match_operand:VF 3 "register_operand"          " vr, vr, vr, vr"))
 	  (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu,  0, vu,  0")))]
@@ -7142,10 +7140,8 @@
 	     (match_operand 5 "const_int_operand"            "    i,    i")
 	     (match_operand 6 "const_int_operand"            "    i,    i")
 	     (match_operand 7 "const_int_operand"            "    i,    i")
-	     (match_operand 8 "const_int_operand"            "    i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)
-	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_fix:VWCONVERTI
 	     (match_operand:<VNCONVERT> 3 "register_operand" "   vr,   vr"))
 	  (match_operand:VWCONVERTI 2 "vector_merge_operand" "   vu,    0")))]
@@ -7233,10 +7229,8 @@
 	     (match_operand 5 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
 	     (match_operand 6 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
 	     (match_operand 7 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
-	     (match_operand 8 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)
-	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_fix:<VNCONVERT>
 	     (match_operand:VF 3 "register_operand"           "  0,  0,  0,  0,   vr,   vr"))
 	  (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu,  0, vu,  0,   vu,    0")))]
-- 
2.36.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] RISC-V: Remove FRM_REGNUM dependency for rtx conversions
  2023-05-24 11:26 [PATCH] RISC-V: Remove FRM_REGNUM dependency for rtx conversions juzhe.zhong
@ 2023-05-25  4:02 ` Kito Cheng
  2023-05-25  6:20   ` Li, Pan2
  0 siblings, 1 reply; 3+ messages in thread
From: Kito Cheng @ 2023-05-25  4:02 UTC (permalink / raw)
  To: juzhe.zhong; +Cc: gcc-patches, palmer, rdapp.gcc, jeffreyalaw

LGTM, thanks :)

On Wed, May 24, 2023 at 7:26 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> According to RVV ISA:
> The conversions use the dynamic rounding mode in frm, except for the rtz variants, which round towards zero.
>
> So rtz conversion patterns should not have FRM dependency.
>
> We can't support mode switching for FRM yet since rvv intrinsic doc is not updated but
> I think this patch is correct.
>
> gcc/ChangeLog:
>
>         * config/riscv/vector.md: Remove FRM_REGNUM dependency in rtz instructions.
>
> ---
>  gcc/config/riscv/vector.md | 12 +++---------
>  1 file changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 9afef0d12bc..15f66efaa48 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -7072,10 +7072,8 @@
>              (match_operand 5 "const_int_operand"            "  i,  i,  i,  i")
>              (match_operand 6 "const_int_operand"            "  i,  i,  i,  i")
>              (match_operand 7 "const_int_operand"            "  i,  i,  i,  i")
> -            (match_operand 8 "const_int_operand"            "  i,  i,  i,  i")
>              (reg:SI VL_REGNUM)
> -            (reg:SI VTYPE_REGNUM)
> -            (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> +            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
>           (any_fix:<VCONVERT>
>              (match_operand:VF 3 "register_operand"          " vr, vr, vr, vr"))
>           (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu,  0, vu,  0")))]
> @@ -7142,10 +7140,8 @@
>              (match_operand 5 "const_int_operand"            "    i,    i")
>              (match_operand 6 "const_int_operand"            "    i,    i")
>              (match_operand 7 "const_int_operand"            "    i,    i")
> -            (match_operand 8 "const_int_operand"            "    i,    i")
>              (reg:SI VL_REGNUM)
> -            (reg:SI VTYPE_REGNUM)
> -            (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> +            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
>           (any_fix:VWCONVERTI
>              (match_operand:<VNCONVERT> 3 "register_operand" "   vr,   vr"))
>           (match_operand:VWCONVERTI 2 "vector_merge_operand" "   vu,    0")))]
> @@ -7233,10 +7229,8 @@
>              (match_operand 5 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
>              (match_operand 6 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
>              (match_operand 7 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
> -            (match_operand 8 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
>              (reg:SI VL_REGNUM)
> -            (reg:SI VTYPE_REGNUM)
> -            (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> +            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
>           (any_fix:<VNCONVERT>
>              (match_operand:VF 3 "register_operand"           "  0,  0,  0,  0,   vr,   vr"))
>           (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu,  0, vu,  0,   vu,    0")))]
> --
> 2.36.1
>

^ permalink raw reply	[flat|nested] 3+ messages in thread

* RE: [PATCH] RISC-V: Remove FRM_REGNUM dependency for rtx conversions
  2023-05-25  4:02 ` Kito Cheng
@ 2023-05-25  6:20   ` Li, Pan2
  0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2023-05-25  6:20 UTC (permalink / raw)
  To: Kito Cheng, juzhe.zhong; +Cc: gcc-patches, palmer, rdapp.gcc, jeffreyalaw

Committed, thanks Kito.

Pan

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Kito Cheng via Gcc-patches
Sent: Thursday, May 25, 2023 12:02 PM
To: juzhe.zhong@rivai.ai
Cc: gcc-patches@gcc.gnu.org; palmer@rivosinc.com; rdapp.gcc@gmail.com; jeffreyalaw@gmail.com
Subject: Re: [PATCH] RISC-V: Remove FRM_REGNUM dependency for rtx conversions

LGTM, thanks :)

On Wed, May 24, 2023 at 7:26 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> According to RVV ISA:
> The conversions use the dynamic rounding mode in frm, except for the rtz variants, which round towards zero.
>
> So rtz conversion patterns should not have FRM dependency.
>
> We can't support mode switching for FRM yet since rvv intrinsic doc is 
> not updated but I think this patch is correct.
>
> gcc/ChangeLog:
>
>         * config/riscv/vector.md: Remove FRM_REGNUM dependency in rtz instructions.
>
> ---
>  gcc/config/riscv/vector.md | 12 +++---------
>  1 file changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md 
> index 9afef0d12bc..15f66efaa48 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -7072,10 +7072,8 @@
>              (match_operand 5 "const_int_operand"            "  i,  i,  i,  i")
>              (match_operand 6 "const_int_operand"            "  i,  i,  i,  i")
>              (match_operand 7 "const_int_operand"            "  i,  i,  i,  i")
> -            (match_operand 8 "const_int_operand"            "  i,  i,  i,  i")
>              (reg:SI VL_REGNUM)
> -            (reg:SI VTYPE_REGNUM)
> -            (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> +            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
>           (any_fix:<VCONVERT>
>              (match_operand:VF 3 "register_operand"          " vr, vr, vr, vr"))
>           (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu,  0, 
> vu,  0")))] @@ -7142,10 +7140,8 @@
>              (match_operand 5 "const_int_operand"            "    i,    i")
>              (match_operand 6 "const_int_operand"            "    i,    i")
>              (match_operand 7 "const_int_operand"            "    i,    i")
> -            (match_operand 8 "const_int_operand"            "    i,    i")
>              (reg:SI VL_REGNUM)
> -            (reg:SI VTYPE_REGNUM)
> -            (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> +            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
>           (any_fix:VWCONVERTI
>              (match_operand:<VNCONVERT> 3 "register_operand" "   vr,   vr"))
>           (match_operand:VWCONVERTI 2 "vector_merge_operand" "   vu,    0")))]
> @@ -7233,10 +7229,8 @@
>              (match_operand 5 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
>              (match_operand 6 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
>              (match_operand 7 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
> -            (match_operand 8 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
>              (reg:SI VL_REGNUM)
> -            (reg:SI VTYPE_REGNUM)
> -            (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> +            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
>           (any_fix:<VNCONVERT>
>              (match_operand:VF 3 "register_operand"           "  0,  0,  0,  0,   vr,   vr"))
>           (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu,  0, vu,  0,   vu,    0")))]
> --
> 2.36.1
>

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2023-05-25  6:20 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2023-05-24 11:26 [PATCH] RISC-V: Remove FRM_REGNUM dependency for rtx conversions juzhe.zhong
2023-05-25  4:02 ` Kito Cheng
2023-05-25  6:20   ` Li, Pan2

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