* [PATCH 1/2] RISC-V: Recognized zihintntl extensions
@ 2023-07-13 5:38 Monk Chiang
2023-07-13 5:38 ` [PATCH 2/2] RISC-V: Implement locality for __builtin_prefetch Monk Chiang
2023-07-14 7:11 ` [PATCH 1/2] RISC-V: Recognized zihintntl extensions Kito Cheng
0 siblings, 2 replies; 4+ messages in thread
From: Monk Chiang @ 2023-07-13 5:38 UTC (permalink / raw)
To: gcc-patches, kito.cheng; +Cc: Monk Chiang
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zihintntl item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZIHINTNTL): New macro.
(TARGET_ZIHINTNTL): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-22.c: New test.
* gcc.target/riscv/predef-28.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 4 ++
gcc/config/riscv/riscv-opts.h | 2 +
gcc/testsuite/gcc.target/riscv/arch-22.c | 5 +++
gcc/testsuite/gcc.target/riscv/predef-28.c | 47 ++++++++++++++++++++++
4 files changed, 58 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-28.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 6091d8f281b..28c8f0c1489 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -206,6 +206,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"zksh", ISA_SPEC_CLASS_NONE, 1, 0},
{"zkt", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0},
+
{"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
{"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
{"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1267,6 +1269,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zksh", &gcc_options::x_riscv_zk_subext, MASK_ZKSH},
{"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT},
+ {"zihintntl", &gcc_options::x_riscv_zi_subext, MASK_ZIHINTNTL},
+
{"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ},
{"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM},
{"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index cfcf608ea62..beee241aa1b 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -101,9 +101,11 @@ enum riscv_entity
#define MASK_ZICSR (1 << 0)
#define MASK_ZIFENCEI (1 << 1)
+#define MASK_ZIHINTNTL (1 << 2)
#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
+#define TARGET_ZIHINTNTL ((riscv_zi_subext & MASK_ZIHINTNTL) != 0)
#define MASK_ZAWRS (1 << 0)
#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-22.c b/gcc/testsuite/gcc.target/riscv/arch-22.c
new file mode 100644
index 00000000000..cdc18e13d0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-22.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zihintntl -mabi=lp64 -mcmodel=medlow" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-28.c b/gcc/testsuite/gcc.target/riscv/predef-28.c
new file mode 100644
index 00000000000..81fdad571e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-28.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zihintntl -mabi=lp64 -mcmodel=medlow" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if !defined(__riscv_m)
+#error "__riscv_m"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if !defined(__riscv_zihintntl)
+#error "__riscv_zihintntl"
+#endif
+
+ return 0;
+}
--
2.40.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] RISC-V: Implement locality for __builtin_prefetch
2023-07-13 5:38 [PATCH 1/2] RISC-V: Recognized zihintntl extensions Monk Chiang
@ 2023-07-13 5:38 ` Monk Chiang
2023-07-14 7:13 ` Kito Cheng
2023-07-14 7:11 ` [PATCH 1/2] RISC-V: Recognized zihintntl extensions Kito Cheng
1 sibling, 1 reply; 4+ messages in thread
From: Monk Chiang @ 2023-07-13 5:38 UTC (permalink / raw)
To: gcc-patches, kito.cheng; +Cc: Monk Chiang
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand):
Add 'N' for print a non-temporal locality hints instruction.
* config/riscv/riscv.md (prefetch):
Add NTLH instruction for prefetch.r and prefetch.w.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/prefetch-zihintntl.c: New test.
---
gcc/config/riscv/riscv.cc | 22 +++++++++++++++++++
gcc/config/riscv/riscv.md | 10 ++++++---
.../gcc.target/riscv/prefetch-zihintntl.c | 20 +++++++++++++++++
3 files changed, 49 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 706c18416db..42f80088bab 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4532,6 +4532,7 @@ riscv_memmodel_needs_amo_release (enum memmodel model)
'A' Print the atomic operation suffix for memory model OP.
'I' Print the LR suffix for memory model OP.
'J' Print the SC suffix for memory model OP.
+ 'N' Print a non-temporal locality hints instruction.
'z' Print x0 if OP is zero, otherwise print OP normally.
'i' Print i if the operand is not a register.
'S' Print shift-index of single-bit mask OP.
@@ -4718,6 +4719,27 @@ riscv_print_operand (FILE *file, rtx op, int letter)
break;
}
+ case 'N':
+ {
+ const char *ntl_hint = NULL;
+ switch (INTVAL (op))
+ {
+ case 0:
+ ntl_hint = "ntl.all";
+ break;
+ case 1:
+ ntl_hint = "ntl.pall";
+ break;
+ case 2:
+ ntl_hint = "ntl.p1";
+ break;
+ }
+
+ if (ntl_hint)
+ asm_fprintf (file, "%s\n\t", ntl_hint);
+ break;
+ }
+
case 'i':
if (code != REG)
fputs ("i", file);
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 7988026d129..3357c981b5d 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3256,11 +3256,15 @@
{
switch (INTVAL (operands[1]))
{
- case 0: return "prefetch.r\t%a0";
- case 1: return "prefetch.w\t%a0";
+ case 0: return TARGET_ZIHINTNTL ? "%N2prefetch.r\t%a0" : "prefetch.r\t%a0";
+ case 1: return TARGET_ZIHINTNTL ? "%N2prefetch.w\t%a0" : "prefetch.w\t%a0";
default: gcc_unreachable ();
}
-})
+}
+ [(set (attr "length") (if_then_else (and (match_test "TARGET_ZIHINTNTL")
+ (match_test "INTVAL (operands[2]) != 3"))
+ (const_string "8")
+ (const_string "4")))])
(define_insn "riscv_prefetchi_<mode>"
[(unspec_volatile:X [(match_operand:X 0 "address_operand" "r")
diff --git a/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c
new file mode 100644
index 00000000000..78a3afe6833
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c
@@ -0,0 +1,20 @@
+/* { dg-do compile target { { rv64-*-*}}} */
+/* { dg-options "-march=rv64gc_zicbop_zihintntl -mabi=lp64" } */
+
+void foo (char *p)
+{
+ __builtin_prefetch (p, 0, 0);
+ __builtin_prefetch (p, 0, 1);
+ __builtin_prefetch (p, 0, 2);
+ __builtin_prefetch (p, 0, 3);
+ __builtin_prefetch (p, 1, 0);
+ __builtin_prefetch (p, 1, 1);
+ __builtin_prefetch (p, 1, 2);
+ __builtin_prefetch (p, 1, 3);
+}
+
+/* { dg-final { scan-assembler-times "ntl.all" 2 } } */
+/* { dg-final { scan-assembler-times "ntl.pall" 2 } } */
+/* { dg-final { scan-assembler-times "ntl.p1" 2 } } */
+/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
+/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */
--
2.40.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] RISC-V: Recognized zihintntl extensions
2023-07-13 5:38 [PATCH 1/2] RISC-V: Recognized zihintntl extensions Monk Chiang
2023-07-13 5:38 ` [PATCH 2/2] RISC-V: Implement locality for __builtin_prefetch Monk Chiang
@ 2023-07-14 7:11 ` Kito Cheng
1 sibling, 0 replies; 4+ messages in thread
From: Kito Cheng @ 2023-07-14 7:11 UTC (permalink / raw)
To: Monk Chiang; +Cc: gcc-patches
Committed, thanks :)
On Thu, Jul 13, 2023 at 1:39 PM Monk Chiang via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> (riscv_implied_info): Add zihintntl item.
> (riscv_ext_version_table): Ditto.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv-opts.h (MASK_ZIHINTNTL): New macro.
> (TARGET_ZIHINTNTL): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-22.c: New test.
> * gcc.target/riscv/predef-28.c: New test.
> ---
> gcc/common/config/riscv/riscv-common.cc | 4 ++
> gcc/config/riscv/riscv-opts.h | 2 +
> gcc/testsuite/gcc.target/riscv/arch-22.c | 5 +++
> gcc/testsuite/gcc.target/riscv/predef-28.c | 47 ++++++++++++++++++++++
> 4 files changed, 58 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-28.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 6091d8f281b..28c8f0c1489 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -206,6 +206,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
> {"zksh", ISA_SPEC_CLASS_NONE, 1, 0},
> {"zkt", ISA_SPEC_CLASS_NONE, 1, 0},
>
> + {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0},
> +
> {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
> {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
> {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1267,6 +1269,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
> {"zksh", &gcc_options::x_riscv_zk_subext, MASK_ZKSH},
> {"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT},
>
> + {"zihintntl", &gcc_options::x_riscv_zi_subext, MASK_ZIHINTNTL},
> +
> {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ},
> {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM},
> {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP},
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index cfcf608ea62..beee241aa1b 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -101,9 +101,11 @@ enum riscv_entity
>
> #define MASK_ZICSR (1 << 0)
> #define MASK_ZIFENCEI (1 << 1)
> +#define MASK_ZIHINTNTL (1 << 2)
>
> #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
> #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
> +#define TARGET_ZIHINTNTL ((riscv_zi_subext & MASK_ZIHINTNTL) != 0)
>
> #define MASK_ZAWRS (1 << 0)
> #define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-22.c b/gcc/testsuite/gcc.target/riscv/arch-22.c
> new file mode 100644
> index 00000000000..cdc18e13d0f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-22.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv64gc_zihintntl -mabi=lp64 -mcmodel=medlow" } */
> +int foo()
> +{
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-28.c b/gcc/testsuite/gcc.target/riscv/predef-28.c
> new file mode 100644
> index 00000000000..81fdad571e7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/predef-28.c
> @@ -0,0 +1,47 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_zihintntl -mabi=lp64 -mcmodel=medlow" } */
> +
> +int main () {
> +
> +#ifndef __riscv_arch_test
> +#error "__riscv_arch_test"
> +#endif
> +
> +#if __riscv_xlen != 64
> +#error "__riscv_xlen"
> +#endif
> +
> +#if !defined(__riscv_i)
> +#error "__riscv_i"
> +#endif
> +
> +#if !defined(__riscv_c)
> +#error "__riscv_c"
> +#endif
> +
> +#if defined(__riscv_e)
> +#error "__riscv_e"
> +#endif
> +
> +#if !defined(__riscv_a)
> +#error "__riscv_a"
> +#endif
> +
> +#if !defined(__riscv_m)
> +#error "__riscv_m"
> +#endif
> +
> +#if !defined(__riscv_f)
> +#error "__riscv_f"
> +#endif
> +
> +#if !defined(__riscv_d)
> +#error "__riscv_d"
> +#endif
> +
> +#if !defined(__riscv_zihintntl)
> +#error "__riscv_zihintntl"
> +#endif
> +
> + return 0;
> +}
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] RISC-V: Implement locality for __builtin_prefetch
2023-07-13 5:38 ` [PATCH 2/2] RISC-V: Implement locality for __builtin_prefetch Monk Chiang
@ 2023-07-14 7:13 ` Kito Cheng
0 siblings, 0 replies; 4+ messages in thread
From: Kito Cheng @ 2023-07-14 7:13 UTC (permalink / raw)
To: Monk Chiang; +Cc: gcc-patches
Corresponding PR on c-api-doc under discussion, so defer this until
that settles down :)
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/46
On Thu, Jul 13, 2023 at 1:40 PM Monk Chiang via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_print_operand):
> Add 'N' for print a non-temporal locality hints instruction.
> * config/riscv/riscv.md (prefetch):
> Add NTLH instruction for prefetch.r and prefetch.w.
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/prefetch-zihintntl.c: New test.
> ---
> gcc/config/riscv/riscv.cc | 22 +++++++++++++++++++
> gcc/config/riscv/riscv.md | 10 ++++++---
> .../gcc.target/riscv/prefetch-zihintntl.c | 20 +++++++++++++++++
> 3 files changed, 49 insertions(+), 3 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 706c18416db..42f80088bab 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -4532,6 +4532,7 @@ riscv_memmodel_needs_amo_release (enum memmodel model)
> 'A' Print the atomic operation suffix for memory model OP.
> 'I' Print the LR suffix for memory model OP.
> 'J' Print the SC suffix for memory model OP.
> + 'N' Print a non-temporal locality hints instruction.
> 'z' Print x0 if OP is zero, otherwise print OP normally.
> 'i' Print i if the operand is not a register.
> 'S' Print shift-index of single-bit mask OP.
> @@ -4718,6 +4719,27 @@ riscv_print_operand (FILE *file, rtx op, int letter)
> break;
> }
>
> + case 'N':
> + {
> + const char *ntl_hint = NULL;
> + switch (INTVAL (op))
> + {
> + case 0:
> + ntl_hint = "ntl.all";
> + break;
> + case 1:
> + ntl_hint = "ntl.pall";
> + break;
> + case 2:
> + ntl_hint = "ntl.p1";
> + break;
> + }
> +
> + if (ntl_hint)
> + asm_fprintf (file, "%s\n\t", ntl_hint);
> + break;
> + }
> +
> case 'i':
> if (code != REG)
> fputs ("i", file);
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 7988026d129..3357c981b5d 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -3256,11 +3256,15 @@
> {
> switch (INTVAL (operands[1]))
> {
> - case 0: return "prefetch.r\t%a0";
> - case 1: return "prefetch.w\t%a0";
> + case 0: return TARGET_ZIHINTNTL ? "%N2prefetch.r\t%a0" : "prefetch.r\t%a0";
> + case 1: return TARGET_ZIHINTNTL ? "%N2prefetch.w\t%a0" : "prefetch.w\t%a0";
> default: gcc_unreachable ();
> }
> -})
> +}
> + [(set (attr "length") (if_then_else (and (match_test "TARGET_ZIHINTNTL")
> + (match_test "INTVAL (operands[2]) != 3"))
> + (const_string "8")
> + (const_string "4")))])
>
> (define_insn "riscv_prefetchi_<mode>"
> [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r")
> diff --git a/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c
> new file mode 100644
> index 00000000000..78a3afe6833
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile target { { rv64-*-*}}} */
> +/* { dg-options "-march=rv64gc_zicbop_zihintntl -mabi=lp64" } */
> +
> +void foo (char *p)
> +{
> + __builtin_prefetch (p, 0, 0);
> + __builtin_prefetch (p, 0, 1);
> + __builtin_prefetch (p, 0, 2);
> + __builtin_prefetch (p, 0, 3);
> + __builtin_prefetch (p, 1, 0);
> + __builtin_prefetch (p, 1, 1);
> + __builtin_prefetch (p, 1, 2);
> + __builtin_prefetch (p, 1, 3);
> +}
> +
> +/* { dg-final { scan-assembler-times "ntl.all" 2 } } */
> +/* { dg-final { scan-assembler-times "ntl.pall" 2 } } */
> +/* { dg-final { scan-assembler-times "ntl.p1" 2 } } */
> +/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
> +/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-07-14 7:11 ` [PATCH 1/2] RISC-V: Recognized zihintntl extensions Kito Cheng
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