[PATCH V3] RISC-V: Add TARGET_MIN_VLEN > 4096 check

[Juzhe-Zhong <juzhe.zhong@rivai.ai>]

gcc/ChangeLog:

        * config/riscv/riscv.cc (riscv_option_override): Add sorry check.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: New test.
        * gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: New test.

---
 gcc/config/riscv/riscv.cc                                 | 8 ++++++++
 .../gcc.target/riscv/rvv/base/zvl-unimplemented-1.c       | 4 ++++
 .../gcc.target/riscv/rvv/base/zvl-unimplemented-2.c       | 4 ++++
 3 files changed, 16 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6ed735d6983..82e7c27b057 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6672,6 +6672,14 @@ riscv_option_override (void)
       riscv_stack_protector_guard_offset = offs;
     }
 
+  /* FIXME: We don't allow TARGET_MIN_VLEN > 4096 since the datatypes of
+     both GET_MODE_SIZE and GET_MODE_BITSIZE are poly_uint16.
+
+     We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535.  */
+  if (TARGET_MIN_VLEN > 4096)
+    sorry (
+      "Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension");
+
   /* Convert -march to a chunks count.  */
   riscv_vector_chunks = riscv_convert_vector_bits ();
 }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c
new file mode 100644
index 00000000000..03f67035ca4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */
+
+void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c
new file mode 100644
index 00000000000..075112f2f81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=scalable" } */
+
+void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" }
-- 
2.36.1