* [PATCH v1] RISC-V: Enhance the test case for RVV vfsub/vfrsub rounding
@ 2023-08-02 7:59 pan2.li
2023-08-08 13:11 ` Li, Pan2
2023-08-08 14:10 ` Jeff Law
0 siblings, 2 replies; 4+ messages in thread
From: pan2.li @ 2023-08-02 7:59 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang
From: Pan Li <pan2.li@intel.com>
This patch would like to enhance the vfsub/vfrsub rounding API test for
below 2 purposes.
* The non-rm API has no frm related insn generated.
* The rm API has the frm backup/restore/set insn generated.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-rsub.c: Enhance
cases.
* gcc.target/riscv/rvv/base/float-point-single-sub.c: Ditto.
---
.../riscv/rvv/base/float-point-single-rsub.c | 16 +++++++++++++++-
.../riscv/rvv/base/float-point-single-sub.c | 16 +++++++++++++++-
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
index 1d770adc32c..86c56b7c6cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
@@ -16,4 +16,18 @@ test_vfrsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
return __riscv_vfrsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl);
}
-/* { dg-final { scan-assembler-times {vfrsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
+vfloat32m1_t
+test_vfrsub_vf_f32m1 (vfloat32m1_t op1, float32_t op2, size_t vl) {
+ return __riscv_vfrsub_vf_f32m1 (op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfrsub_vf_f32m1_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+ size_t vl) {
+ return __riscv_vfrsub_vf_f32m1_m (mask, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfrsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
index 34ed03a31d9..8075dced0b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
@@ -27,4 +27,18 @@ test_vfsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
return __riscv_vfsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl);
}
-/* { dg-final { scan-assembler-times {vfsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+vfloat32m1_t
+test_riscv_vfsub_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfsub_vv_f32m1 (op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfsub_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfsub_vv_f32m1_m (mask, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH v1] RISC-V: Enhance the test case for RVV vfsub/vfrsub rounding
2023-08-02 7:59 [PATCH v1] RISC-V: Enhance the test case for RVV vfsub/vfrsub rounding pan2.li
@ 2023-08-08 13:11 ` Li, Pan2
2023-08-08 14:10 ` Jeff Law
1 sibling, 0 replies; 4+ messages in thread
From: Li, Pan2 @ 2023-08-08 13:11 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, Wang, Yanzhang
Kindly ping.
Pan
-----Original Message-----
From: Li, Pan2 <pan2.li@intel.com>
Sent: Wednesday, August 2, 2023 3:59 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: [PATCH v1] RISC-V: Enhance the test case for RVV vfsub/vfrsub rounding
From: Pan Li <pan2.li@intel.com>
This patch would like to enhance the vfsub/vfrsub rounding API test for
below 2 purposes.
* The non-rm API has no frm related insn generated.
* The rm API has the frm backup/restore/set insn generated.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-rsub.c: Enhance
cases.
* gcc.target/riscv/rvv/base/float-point-single-sub.c: Ditto.
---
.../riscv/rvv/base/float-point-single-rsub.c | 16 +++++++++++++++-
.../riscv/rvv/base/float-point-single-sub.c | 16 +++++++++++++++-
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
index 1d770adc32c..86c56b7c6cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
@@ -16,4 +16,18 @@ test_vfrsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
return __riscv_vfrsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl);
}
-/* { dg-final { scan-assembler-times {vfrsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
+vfloat32m1_t
+test_vfrsub_vf_f32m1 (vfloat32m1_t op1, float32_t op2, size_t vl) {
+ return __riscv_vfrsub_vf_f32m1 (op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfrsub_vf_f32m1_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+ size_t vl) {
+ return __riscv_vfrsub_vf_f32m1_m (mask, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfrsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
index 34ed03a31d9..8075dced0b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
@@ -27,4 +27,18 @@ test_vfsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
return __riscv_vfsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl);
}
-/* { dg-final { scan-assembler-times {vfsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+vfloat32m1_t
+test_riscv_vfsub_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfsub_vv_f32m1 (op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfsub_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfsub_vv_f32m1_m (mask, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v1] RISC-V: Enhance the test case for RVV vfsub/vfrsub rounding
2023-08-02 7:59 [PATCH v1] RISC-V: Enhance the test case for RVV vfsub/vfrsub rounding pan2.li
2023-08-08 13:11 ` Li, Pan2
@ 2023-08-08 14:10 ` Jeff Law
2023-08-08 14:22 ` Li, Pan2
1 sibling, 1 reply; 4+ messages in thread
From: Jeff Law @ 2023-08-08 14:10 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: juzhe.zhong, kito.cheng, yanzhang.wang
On 8/2/23 01:59, Pan Li via Gcc-patches wrote:
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to enhance the vfsub/vfrsub rounding API test for
> below 2 purposes.
>
> * The non-rm API has no frm related insn generated.
> * The rm API has the frm backup/restore/set insn generated.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-single-rsub.c: Enhance
> cases.
> * gcc.target/riscv/rvv/base/float-point-single-sub.c: Ditto.
OK.
jeff
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH v1] RISC-V: Enhance the test case for RVV vfsub/vfrsub rounding
2023-08-08 14:10 ` Jeff Law
@ 2023-08-08 14:22 ` Li, Pan2
0 siblings, 0 replies; 4+ messages in thread
From: Li, Pan2 @ 2023-08-08 14:22 UTC (permalink / raw)
To: Jeff Law, gcc-patches; +Cc: juzhe.zhong, kito.cheng, Wang, Yanzhang
Committed, thanks Jeff.
Pan
-----Original Message-----
From: Jeff Law <jeffreyalaw@gmail.com>
Sent: Tuesday, August 8, 2023 10:10 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Enhance the test case for RVV vfsub/vfrsub rounding
On 8/2/23 01:59, Pan Li via Gcc-patches wrote:
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to enhance the vfsub/vfrsub rounding API test for
> below 2 purposes.
>
> * The non-rm API has no frm related insn generated.
> * The rm API has the frm backup/restore/set insn generated.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-single-rsub.c: Enhance
> cases.
> * gcc.target/riscv/rvv/base/float-point-single-sub.c: Ditto.
OK.
jeff
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-08-02 7:59 [PATCH v1] RISC-V: Enhance the test case for RVV vfsub/vfrsub rounding pan2.li
2023-08-08 13:11 ` Li, Pan2
2023-08-08 14:10 ` Jeff Law
2023-08-08 14:22 ` Li, Pan2
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