* [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
@ 2023-08-06 3:36 pan2.li
2023-08-07 0:45 ` juzhe.zhong
` (2 more replies)
0 siblings, 3 replies; 17+ messages in thread
From: pan2.li @ 2023-08-06 3:36 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the define insn has frm operands.
This patch would like to refactor frm and eliminate the above
assumptions, as well as unblock the underlying rounding mode intrinsic
API support.
After refactor, the default frm will be none, and the selected insn type
will be dyn. For the floating point which honors the frm, we will
set the frm_mode attr explicitly in define_insn.
Passed both the riscv.exp and rvv.exp for rv32/rv64 tests.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_frm_mode): Remove operand
assumptions.
* config/riscv/riscv-v.cc (get_frm_mode): New function.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn):
* config/riscv/vector.md: Set frm_mode attr explicitly.
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 28 ++++
gcc/config/riscv/riscv-vector-builtins.cc | 22 ++-
gcc/config/riscv/vector.md | 170 ++++++++++++++--------
4 files changed, 159 insertions(+), 62 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 324991e2619..33f7cb1d670 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -236,6 +236,7 @@ bool check_builtin_call (location_t, vec<location_t>, unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
bool legitimize_move (rtx, rtx);
+int get_frm_mode (rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 278452b9e05..d5fb8611d6e 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1513,6 +1513,34 @@ expand_const_vector (rtx target, rtx src)
gcc_unreachable ();
}
+/* Get the frm mode with given CONST_INT rtx, the default mode is
+ FRM_MODE_DYN. */
+int
+get_frm_mode (rtx operand)
+{
+ gcc_assert (CONST_INT_P (operand));
+
+ switch (INTVAL (operand))
+ {
+ case FRM_RNE:
+ return FRM_MODE_RNE;
+ case FRM_RTZ:
+ return FRM_MODE_RTZ;
+ case FRM_RDN:
+ return FRM_MODE_RDN;
+ case FRM_RUP:
+ return FRM_MODE_RUP;
+ case FRM_RMM:
+ return FRM_MODE_RMM;
+ case FRM_DYN:
+ return FRM_MODE_DYN;
+ default:
+ return FRM_MODE_DYN;
+ }
+
+ gcc_unreachable ();
+}
+
/* Expand a pre-RA RVV data move from SRC to DEST.
It expands move for RVV fractional vector modes. */
bool
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 528dca7ae85..abab06c00ed 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)
}
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
- add_input_operand (argno);
+ {
+ if (base->has_rounding_mode_operand_p ()
+ && argno == call_expr_nargs (exp) - 2)
+ {
+ /* Since the rounding mode argument position is not consistent with
+ the instruction pattern, we need to skip rounding mode argument
+ here. */
+ continue;
+ }
+ add_input_operand (argno);
+ }
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
- /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
- We add default rounding mode for the intrinsics that didn't model rounding
- mode yet. */
+ if (base->has_rounding_mode_operand_p ())
+ add_input_operand (call_expr_nargs (exp) - 2);
+
+ /* The RVV floating-point only support dynamic rounding mode in the
+ FRM register. */
if (opno != insn_data[icode].n_generator_args)
- add_input_operand (Pmode, const0_rtx);
+ add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
return generate_insn (icode);
}
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 750b2de8df9..db3ee105ef4 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -867,26 +867,8 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
;; Defines rounding mode of an floating-point operation.
(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
- (cond
- [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
- (const_string "rne")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ")
- (const_string "rtz")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN")
- (const_string "rdn")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP")
- (const_string "rup")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM")
- (const_string "rmm")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN")
- (const_string "dyn")]
- (const_string "none"))]
- (const_string "none")))
+ (const_string "dyn")]
+ (const_string "none")))
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
@@ -6147,7 +6129,9 @@ (define_insn "@pred_<optab><mode>"
"TARGET_VECTOR"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6190,7 +6174,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6234,7 +6220,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_reverse_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6257,7 +6245,9 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
"TARGET_VECTOR"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<copysign><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6408,7 +6398,9 @@ (define_insn "*pred_<madd_msub><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6441,7 +6433,9 @@ (define_insn "*pred_<macc_msac><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6478,7 +6472,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6535,7 +6531,9 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6569,7 +6567,9 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6606,7 +6606,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand")
@@ -6668,7 +6670,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6702,7 +6706,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6740,7 +6746,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6799,7 +6807,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6834,7 +6844,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6872,7 +6884,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point unary operations
@@ -6908,7 +6922,9 @@ (define_insn "@pred_<optab><mode>"
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -7002,7 +7018,9 @@ (define_insn "@pred_dual_widen_<optab><mode>"
"TARGET_VECTOR"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_dual_widen_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7027,7 +7045,9 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_add<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7050,7 +7070,9 @@ (define_insn "@pred_single_widen_add<mode>"
"TARGET_VECTOR"
"vfwadd.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_sub<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7073,7 +7095,9 @@ (define_insn "@pred_single_widen_sub<mode>"
"TARGET_VECTOR"
"vfwsub.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7097,7 +7121,9 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated widen floating-point ternary operations
@@ -7130,7 +7156,9 @@ (define_insn "@pred_widen_mul_<optab><mode>"
"TARGET_VECTOR"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7157,7 +7185,9 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7184,7 +7214,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7212,7 +7244,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point comparison operations
@@ -7522,7 +7556,9 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<fix_cvt><mode>"
[(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
@@ -7562,7 +7598,9 @@ (define_insn "@pred_<float_cvt><mode>"
"TARGET_VECTOR"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point widen conversions
@@ -7590,7 +7628,9 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_widen_<fix_cvt><mode>"
[(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
@@ -7675,7 +7715,9 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_narrow_<fix_cvt><mode>"
[(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7715,7 +7757,9 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
"TARGET_VECTOR"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7736,7 +7780,9 @@ (define_insn "@pred_trunc<mode>"
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -8016,7 +8062,9 @@ (define_insn "@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for SF
(define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
@@ -8042,7 +8090,9 @@ (define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for DF
(define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
@@ -8068,7 +8118,9 @@ (define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VDF:MODE>")])
+ (set_attr "mode" "<VDF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for HF, aka SF = HF op SF
(define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
@@ -8090,7 +8142,9 @@ (define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for SF, aka DF = SF * DF
(define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
@@ -8112,7 +8166,9 @@ (define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated permutation operations
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-06 3:36 [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic pan2.li
@ 2023-08-07 0:45 ` juzhe.zhong
2023-08-07 1:22 ` Li, Pan2
2023-08-08 5:25 ` [PATCH v2] " pan2.li
2023-08-10 3:12 ` [PATCH v3] " pan2.li
2 siblings, 1 reply; 17+ messages in thread
From: juzhe.zhong @ 2023-08-07 0:45 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: pan2.li, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 25173 bytes --]
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
I don't think we need "(enum attr_frm_mode)"
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-08-06 11:36
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
From: Pan Li <pan2.li@intel.com>
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the define insn has frm operands.
This patch would like to refactor frm and eliminate the above
assumptions, as well as unblock the underlying rounding mode intrinsic
API support.
After refactor, the default frm will be none, and the selected insn type
will be dyn. For the floating point which honors the frm, we will
set the frm_mode attr explicitly in define_insn.
Passed both the riscv.exp and rvv.exp for rv32/rv64 tests.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_frm_mode): Remove operand
assumptions.
* config/riscv/riscv-v.cc (get_frm_mode): New function.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn):
* config/riscv/vector.md: Set frm_mode attr explicitly.
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 28 ++++
gcc/config/riscv/riscv-vector-builtins.cc | 22 ++-
gcc/config/riscv/vector.md | 170 ++++++++++++++--------
4 files changed, 159 insertions(+), 62 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 324991e2619..33f7cb1d670 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -236,6 +236,7 @@ bool check_builtin_call (location_t, vec<location_t>, unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
bool legitimize_move (rtx, rtx);
+int get_frm_mode (rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 278452b9e05..d5fb8611d6e 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1513,6 +1513,34 @@ expand_const_vector (rtx target, rtx src)
gcc_unreachable ();
}
+/* Get the frm mode with given CONST_INT rtx, the default mode is
+ FRM_MODE_DYN. */
+int
+get_frm_mode (rtx operand)
+{
+ gcc_assert (CONST_INT_P (operand));
+
+ switch (INTVAL (operand))
+ {
+ case FRM_RNE:
+ return FRM_MODE_RNE;
+ case FRM_RTZ:
+ return FRM_MODE_RTZ;
+ case FRM_RDN:
+ return FRM_MODE_RDN;
+ case FRM_RUP:
+ return FRM_MODE_RUP;
+ case FRM_RMM:
+ return FRM_MODE_RMM;
+ case FRM_DYN:
+ return FRM_MODE_DYN;
+ default:
+ return FRM_MODE_DYN;
+ }
+
+ gcc_unreachable ();
+}
+
/* Expand a pre-RA RVV data move from SRC to DEST.
It expands move for RVV fractional vector modes. */
bool
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 528dca7ae85..abab06c00ed 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)
}
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
- add_input_operand (argno);
+ {
+ if (base->has_rounding_mode_operand_p ()
+ && argno == call_expr_nargs (exp) - 2)
+ {
+ /* Since the rounding mode argument position is not consistent with
+ the instruction pattern, we need to skip rounding mode argument
+ here. */
+ continue;
+ }
+ add_input_operand (argno);
+ }
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
- /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
- We add default rounding mode for the intrinsics that didn't model rounding
- mode yet. */
+ if (base->has_rounding_mode_operand_p ())
+ add_input_operand (call_expr_nargs (exp) - 2);
+
+ /* The RVV floating-point only support dynamic rounding mode in the
+ FRM register. */
if (opno != insn_data[icode].n_generator_args)
- add_input_operand (Pmode, const0_rtx);
+ add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
return generate_insn (icode);
}
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 750b2de8df9..db3ee105ef4 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -867,26 +867,8 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
;; Defines rounding mode of an floating-point operation.
(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
- (cond
- [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
- (const_string "rne")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ")
- (const_string "rtz")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN")
- (const_string "rdn")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP")
- (const_string "rup")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM")
- (const_string "rmm")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN")
- (const_string "dyn")]
- (const_string "none"))]
- (const_string "none")))
+ (const_string "dyn")]
+ (const_string "none")))
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
@@ -6147,7 +6129,9 @@ (define_insn "@pred_<optab><mode>"
"TARGET_VECTOR"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6190,7 +6174,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6234,7 +6220,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_reverse_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6257,7 +6245,9 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
"TARGET_VECTOR"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<copysign><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6408,7 +6398,9 @@ (define_insn "*pred_<madd_msub><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6441,7 +6433,9 @@ (define_insn "*pred_<macc_msac><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6478,7 +6472,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6535,7 +6531,9 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6569,7 +6567,9 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6606,7 +6606,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand")
@@ -6668,7 +6670,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6702,7 +6706,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6740,7 +6746,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6799,7 +6807,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6834,7 +6844,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6872,7 +6884,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point unary operations
@@ -6908,7 +6922,9 @@ (define_insn "@pred_<optab><mode>"
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -7002,7 +7018,9 @@ (define_insn "@pred_dual_widen_<optab><mode>"
"TARGET_VECTOR"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_dual_widen_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7027,7 +7045,9 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_add<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7050,7 +7070,9 @@ (define_insn "@pred_single_widen_add<mode>"
"TARGET_VECTOR"
"vfwadd.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_sub<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7073,7 +7095,9 @@ (define_insn "@pred_single_widen_sub<mode>"
"TARGET_VECTOR"
"vfwsub.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7097,7 +7121,9 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated widen floating-point ternary operations
@@ -7130,7 +7156,9 @@ (define_insn "@pred_widen_mul_<optab><mode>"
"TARGET_VECTOR"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7157,7 +7185,9 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7184,7 +7214,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7212,7 +7244,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point comparison operations
@@ -7522,7 +7556,9 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<fix_cvt><mode>"
[(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
@@ -7562,7 +7598,9 @@ (define_insn "@pred_<float_cvt><mode>"
"TARGET_VECTOR"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point widen conversions
@@ -7590,7 +7628,9 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_widen_<fix_cvt><mode>"
[(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
@@ -7675,7 +7715,9 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_narrow_<fix_cvt><mode>"
[(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7715,7 +7757,9 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
"TARGET_VECTOR"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7736,7 +7780,9 @@ (define_insn "@pred_trunc<mode>"
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -8016,7 +8062,9 @@ (define_insn "@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for SF
(define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
@@ -8042,7 +8090,9 @@ (define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for DF
(define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
@@ -8068,7 +8118,9 @@ (define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VDF:MODE>")])
+ (set_attr "mode" "<VDF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for HF, aka SF = HF op SF
(define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
@@ -8090,7 +8142,9 @@ (define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for SF, aka DF = SF * DF
(define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
@@ -8112,7 +8166,9 @@ (define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated permutation operations
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-07 0:45 ` juzhe.zhong
@ 2023-08-07 1:22 ` Li, Pan2
2023-08-07 1:30 ` juzhe.zhong
0 siblings, 1 reply; 17+ messages in thread
From: Li, Pan2 @ 2023-08-07 1:22 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Wang, Yanzhang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 26138 bytes --]
We will have below error if there is no cast here.
../gcc/config/riscv/vector.md:6134:36: error: invalid conversion from 'int' to 'attr_frm_mode' [-fpermissive]
Or we can return attr_frm_mode in get_frm_mode but it requires some additional header files. Is there any guidance here in GCC coding style?
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Monday, August 7, 2023 8:46 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
I don't think we need "(enum attr_frm_mode)"
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-08-06 11:36
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the define insn has frm operands.
This patch would like to refactor frm and eliminate the above
assumptions, as well as unblock the underlying rounding mode intrinsic
API support.
After refactor, the default frm will be none, and the selected insn type
will be dyn. For the floating point which honors the frm, we will
set the frm_mode attr explicitly in define_insn.
Passed both the riscv.exp and rvv.exp for rv32/rv64 tests.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_frm_mode): Remove operand
assumptions.
* config/riscv/riscv-v.cc (get_frm_mode): New function.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn):
* config/riscv/vector.md: Set frm_mode attr explicitly.
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 28 ++++
gcc/config/riscv/riscv-vector-builtins.cc | 22 ++-
gcc/config/riscv/vector.md | 170 ++++++++++++++--------
4 files changed, 159 insertions(+), 62 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 324991e2619..33f7cb1d670 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -236,6 +236,7 @@ bool check_builtin_call (location_t, vec<location_t>, unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
bool legitimize_move (rtx, rtx);
+int get_frm_mode (rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 278452b9e05..d5fb8611d6e 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1513,6 +1513,34 @@ expand_const_vector (rtx target, rtx src)
gcc_unreachable ();
}
+/* Get the frm mode with given CONST_INT rtx, the default mode is
+ FRM_MODE_DYN. */
+int
+get_frm_mode (rtx operand)
+{
+ gcc_assert (CONST_INT_P (operand));
+
+ switch (INTVAL (operand))
+ {
+ case FRM_RNE:
+ return FRM_MODE_RNE;
+ case FRM_RTZ:
+ return FRM_MODE_RTZ;
+ case FRM_RDN:
+ return FRM_MODE_RDN;
+ case FRM_RUP:
+ return FRM_MODE_RUP;
+ case FRM_RMM:
+ return FRM_MODE_RMM;
+ case FRM_DYN:
+ return FRM_MODE_DYN;
+ default:
+ return FRM_MODE_DYN;
+ }
+
+ gcc_unreachable ();
+}
+
/* Expand a pre-RA RVV data move from SRC to DEST.
It expands move for RVV fractional vector modes. */
bool
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 528dca7ae85..abab06c00ed 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)
}
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
- add_input_operand (argno);
+ {
+ if (base->has_rounding_mode_operand_p ()
+ && argno == call_expr_nargs (exp) - 2)
+ {
+ /* Since the rounding mode argument position is not consistent with
+ the instruction pattern, we need to skip rounding mode argument
+ here. */
+ continue;
+ }
+ add_input_operand (argno);
+ }
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
- /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
- We add default rounding mode for the intrinsics that didn't model rounding
- mode yet. */
+ if (base->has_rounding_mode_operand_p ())
+ add_input_operand (call_expr_nargs (exp) - 2);
+
+ /* The RVV floating-point only support dynamic rounding mode in the
+ FRM register. */
if (opno != insn_data[icode].n_generator_args)
- add_input_operand (Pmode, const0_rtx);
+ add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
return generate_insn (icode);
}
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 750b2de8df9..db3ee105ef4 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -867,26 +867,8 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
;; Defines rounding mode of an floating-point operation.
(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
- (cond
- [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
- (const_string "rne")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ")
- (const_string "rtz")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN")
- (const_string "rdn")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP")
- (const_string "rup")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM")
- (const_string "rmm")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN")
- (const_string "dyn")]
- (const_string "none"))]
- (const_string "none")))
+ (const_string "dyn")]
+ (const_string "none")))
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
@@ -6147,7 +6129,9 @@ (define_insn "@pred_<optab><mode>"
"TARGET_VECTOR"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6190,7 +6174,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6234,7 +6220,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_reverse_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6257,7 +6245,9 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
"TARGET_VECTOR"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<copysign><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6408,7 +6398,9 @@ (define_insn "*pred_<madd_msub><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6441,7 +6433,9 @@ (define_insn "*pred_<macc_msac><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6478,7 +6472,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6535,7 +6531,9 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6569,7 +6567,9 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6606,7 +6606,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand")
@@ -6668,7 +6670,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6702,7 +6706,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6740,7 +6746,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6799,7 +6807,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6834,7 +6844,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6872,7 +6884,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point unary operations
@@ -6908,7 +6922,9 @@ (define_insn "@pred_<optab><mode>"
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -7002,7 +7018,9 @@ (define_insn "@pred_dual_widen_<optab><mode>"
"TARGET_VECTOR"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_dual_widen_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7027,7 +7045,9 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_add<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7050,7 +7070,9 @@ (define_insn "@pred_single_widen_add<mode>"
"TARGET_VECTOR"
"vfwadd.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_sub<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7073,7 +7095,9 @@ (define_insn "@pred_single_widen_sub<mode>"
"TARGET_VECTOR"
"vfwsub.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7097,7 +7121,9 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated widen floating-point ternary operations
@@ -7130,7 +7156,9 @@ (define_insn "@pred_widen_mul_<optab><mode>"
"TARGET_VECTOR"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7157,7 +7185,9 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7184,7 +7214,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7212,7 +7244,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point comparison operations
@@ -7522,7 +7556,9 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<fix_cvt><mode>"
[(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
@@ -7562,7 +7598,9 @@ (define_insn "@pred_<float_cvt><mode>"
"TARGET_VECTOR"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point widen conversions
@@ -7590,7 +7628,9 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_widen_<fix_cvt><mode>"
[(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
@@ -7675,7 +7715,9 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_narrow_<fix_cvt><mode>"
[(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7715,7 +7757,9 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
"TARGET_VECTOR"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7736,7 +7780,9 @@ (define_insn "@pred_trunc<mode>"
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -8016,7 +8062,9 @@ (define_insn "@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for SF
(define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
@@ -8042,7 +8090,9 @@ (define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for DF
(define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
@@ -8068,7 +8118,9 @@ (define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VDF:MODE>")])
+ (set_attr "mode" "<VDF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for HF, aka SF = HF op SF
(define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
@@ -8090,7 +8142,9 @@ (define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for SF, aka DF = SF * DF
(define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
@@ -8112,7 +8166,9 @@ (define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated permutation operations
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-07 1:22 ` Li, Pan2
@ 2023-08-07 1:30 ` juzhe.zhong
2023-08-07 1:34 ` Li, Pan2
0 siblings, 1 reply; 17+ messages in thread
From: juzhe.zhong @ 2023-08-07 1:30 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 26168 bytes --]
I have no ideal. I would prefer kito makes decision here.
juzhe.zhong@rivai.ai
From: Li, Pan2
Date: 2023-08-07 09:22
To: juzhe.zhong@rivai.ai; gcc-patches
CC: Wang, Yanzhang; kito.cheng
Subject: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
We will have below error if there is no cast here.
../gcc/config/riscv/vector.md:6134:36: error: invalid conversion from ‘int’ to ‘attr_frm_mode’ [-fpermissive]
Or we can return attr_frm_mode in get_frm_mode but it requires some additional header files. Is there any guidance here in GCC coding style?
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Monday, August 7, 2023 8:46 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
+ (set (attr "frm_mode")+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
I don't think we need "(enum attr_frm_mode)"
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-08-06 11:36
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
From: Pan Li <pan2.li@intel.com>
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the define insn has frm operands.
This patch would like to refactor frm and eliminate the above
assumptions, as well as unblock the underlying rounding mode intrinsic
API support.
After refactor, the default frm will be none, and the selected insn type
will be dyn. For the floating point which honors the frm, we will
set the frm_mode attr explicitly in define_insn.
Passed both the riscv.exp and rvv.exp for rv32/rv64 tests.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_frm_mode): Remove operand
assumptions.
* config/riscv/riscv-v.cc (get_frm_mode): New function.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn):
* config/riscv/vector.md: Set frm_mode attr explicitly.
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 28 ++++
gcc/config/riscv/riscv-vector-builtins.cc | 22 ++-
gcc/config/riscv/vector.md | 170 ++++++++++++++--------
4 files changed, 159 insertions(+), 62 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 324991e2619..33f7cb1d670 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -236,6 +236,7 @@ bool check_builtin_call (location_t, vec<location_t>, unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
bool legitimize_move (rtx, rtx);
+int get_frm_mode (rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 278452b9e05..d5fb8611d6e 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1513,6 +1513,34 @@ expand_const_vector (rtx target, rtx src)
gcc_unreachable ();
}
+/* Get the frm mode with given CONST_INT rtx, the default mode is
+ FRM_MODE_DYN. */
+int
+get_frm_mode (rtx operand)
+{
+ gcc_assert (CONST_INT_P (operand));
+
+ switch (INTVAL (operand))
+ {
+ case FRM_RNE:
+ return FRM_MODE_RNE;
+ case FRM_RTZ:
+ return FRM_MODE_RTZ;
+ case FRM_RDN:
+ return FRM_MODE_RDN;
+ case FRM_RUP:
+ return FRM_MODE_RUP;
+ case FRM_RMM:
+ return FRM_MODE_RMM;
+ case FRM_DYN:
+ return FRM_MODE_DYN;
+ default:
+ return FRM_MODE_DYN;
+ }
+
+ gcc_unreachable ();
+}
+
/* Expand a pre-RA RVV data move from SRC to DEST.
It expands move for RVV fractional vector modes. */
bool
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 528dca7ae85..abab06c00ed 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)
}
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
- add_input_operand (argno);
+ {
+ if (base->has_rounding_mode_operand_p ()
+ && argno == call_expr_nargs (exp) - 2)
+ {
+ /* Since the rounding mode argument position is not consistent with
+ the instruction pattern, we need to skip rounding mode argument
+ here. */
+ continue;
+ }
+ add_input_operand (argno);
+ }
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
- /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
- We add default rounding mode for the intrinsics that didn't model rounding
- mode yet. */
+ if (base->has_rounding_mode_operand_p ())
+ add_input_operand (call_expr_nargs (exp) - 2);
+
+ /* The RVV floating-point only support dynamic rounding mode in the
+ FRM register. */
if (opno != insn_data[icode].n_generator_args)
- add_input_operand (Pmode, const0_rtx);
+ add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
return generate_insn (icode);
}
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 750b2de8df9..db3ee105ef4 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -867,26 +867,8 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
;; Defines rounding mode of an floating-point operation.
(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
- (cond
- [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
- (const_string "rne")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ")
- (const_string "rtz")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN")
- (const_string "rdn")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP")
- (const_string "rup")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM")
- (const_string "rmm")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN")
- (const_string "dyn")]
- (const_string "none"))]
- (const_string "none")))
+ (const_string "dyn")]
+ (const_string "none")))
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
@@ -6147,7 +6129,9 @@ (define_insn "@pred_<optab><mode>"
"TARGET_VECTOR"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6190,7 +6174,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6234,7 +6220,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_reverse_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6257,7 +6245,9 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
"TARGET_VECTOR"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<copysign><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6408,7 +6398,9 @@ (define_insn "*pred_<madd_msub><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6441,7 +6433,9 @@ (define_insn "*pred_<macc_msac><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6478,7 +6472,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6535,7 +6531,9 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6569,7 +6567,9 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6606,7 +6606,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand")
@@ -6668,7 +6670,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6702,7 +6706,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6740,7 +6746,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6799,7 +6807,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6834,7 +6844,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6872,7 +6884,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point unary operations
@@ -6908,7 +6922,9 @@ (define_insn "@pred_<optab><mode>"
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -7002,7 +7018,9 @@ (define_insn "@pred_dual_widen_<optab><mode>"
"TARGET_VECTOR"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_dual_widen_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7027,7 +7045,9 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_add<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7050,7 +7070,9 @@ (define_insn "@pred_single_widen_add<mode>"
"TARGET_VECTOR"
"vfwadd.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_sub<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7073,7 +7095,9 @@ (define_insn "@pred_single_widen_sub<mode>"
"TARGET_VECTOR"
"vfwsub.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7097,7 +7121,9 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated widen floating-point ternary operations
@@ -7130,7 +7156,9 @@ (define_insn "@pred_widen_mul_<optab><mode>"
"TARGET_VECTOR"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7157,7 +7185,9 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7184,7 +7214,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7212,7 +7244,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point comparison operations
@@ -7522,7 +7556,9 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<fix_cvt><mode>"
[(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
@@ -7562,7 +7598,9 @@ (define_insn "@pred_<float_cvt><mode>"
"TARGET_VECTOR"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point widen conversions
@@ -7590,7 +7628,9 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_widen_<fix_cvt><mode>"
[(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
@@ -7675,7 +7715,9 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_narrow_<fix_cvt><mode>"
[(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7715,7 +7757,9 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
"TARGET_VECTOR"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7736,7 +7780,9 @@ (define_insn "@pred_trunc<mode>"
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -8016,7 +8062,9 @@ (define_insn "@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for SF
(define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
@@ -8042,7 +8090,9 @@ (define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for DF
(define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
@@ -8068,7 +8118,9 @@ (define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VDF:MODE>")])
+ (set_attr "mode" "<VDF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for HF, aka SF = HF op SF
(define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
@@ -8090,7 +8142,9 @@ (define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for SF, aka DF = SF * DF
(define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
@@ -8112,7 +8166,9 @@ (define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated permutation operations
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-07 1:30 ` juzhe.zhong
@ 2023-08-07 1:34 ` Li, Pan2
2023-08-07 3:26 ` Kito Cheng
0 siblings, 1 reply; 17+ messages in thread
From: Li, Pan2 @ 2023-08-07 1:34 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Wang, Yanzhang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 27245 bytes --]
Sure thing, let’s wait kito’s comment for this.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Monday, August 7, 2023 9:31 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
I have no ideal. I would prefer kito makes decision here.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: Li, Pan2<mailto:pan2.li@intel.com>
Date: 2023-08-07 09:22
To: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>; gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: Wang, Yanzhang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
We will have below error if there is no cast here.
../gcc/config/riscv/vector.md:6134:36: error: invalid conversion from ‘int’ to ‘attr_frm_mode’ [-fpermissive]
Or we can return attr_frm_mode in get_frm_mode but it requires some additional header files. Is there any guidance here in GCC coding style?
Pan
From: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai> <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Sent: Monday, August 7, 2023 8:46 AM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>; kito.cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>
Subject: Re: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
I don't think we need "(enum attr_frm_mode)"
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-08-06 11:36
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the define insn has frm operands.
This patch would like to refactor frm and eliminate the above
assumptions, as well as unblock the underlying rounding mode intrinsic
API support.
After refactor, the default frm will be none, and the selected insn type
will be dyn. For the floating point which honors the frm, we will
set the frm_mode attr explicitly in define_insn.
Passed both the riscv.exp and rvv.exp for rv32/rv64 tests.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_frm_mode): Remove operand
assumptions.
* config/riscv/riscv-v.cc (get_frm_mode): New function.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn):
* config/riscv/vector.md: Set frm_mode attr explicitly.
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 28 ++++
gcc/config/riscv/riscv-vector-builtins.cc | 22 ++-
gcc/config/riscv/vector.md | 170 ++++++++++++++--------
4 files changed, 159 insertions(+), 62 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 324991e2619..33f7cb1d670 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -236,6 +236,7 @@ bool check_builtin_call (location_t, vec<location_t>, unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
bool legitimize_move (rtx, rtx);
+int get_frm_mode (rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 278452b9e05..d5fb8611d6e 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1513,6 +1513,34 @@ expand_const_vector (rtx target, rtx src)
gcc_unreachable ();
}
+/* Get the frm mode with given CONST_INT rtx, the default mode is
+ FRM_MODE_DYN. */
+int
+get_frm_mode (rtx operand)
+{
+ gcc_assert (CONST_INT_P (operand));
+
+ switch (INTVAL (operand))
+ {
+ case FRM_RNE:
+ return FRM_MODE_RNE;
+ case FRM_RTZ:
+ return FRM_MODE_RTZ;
+ case FRM_RDN:
+ return FRM_MODE_RDN;
+ case FRM_RUP:
+ return FRM_MODE_RUP;
+ case FRM_RMM:
+ return FRM_MODE_RMM;
+ case FRM_DYN:
+ return FRM_MODE_DYN;
+ default:
+ return FRM_MODE_DYN;
+ }
+
+ gcc_unreachable ();
+}
+
/* Expand a pre-RA RVV data move from SRC to DEST.
It expands move for RVV fractional vector modes. */
bool
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 528dca7ae85..abab06c00ed 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)
}
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
- add_input_operand (argno);
+ {
+ if (base->has_rounding_mode_operand_p ()
+ && argno == call_expr_nargs (exp) - 2)
+ {
+ /* Since the rounding mode argument position is not consistent with
+ the instruction pattern, we need to skip rounding mode argument
+ here. */
+ continue;
+ }
+ add_input_operand (argno);
+ }
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
- /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
- We add default rounding mode for the intrinsics that didn't model rounding
- mode yet. */
+ if (base->has_rounding_mode_operand_p ())
+ add_input_operand (call_expr_nargs (exp) - 2);
+
+ /* The RVV floating-point only support dynamic rounding mode in the
+ FRM register. */
if (opno != insn_data[icode].n_generator_args)
- add_input_operand (Pmode, const0_rtx);
+ add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
return generate_insn (icode);
}
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 750b2de8df9..db3ee105ef4 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -867,26 +867,8 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
;; Defines rounding mode of an floating-point operation.
(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
- (cond
- [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
- (const_string "rne")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ")
- (const_string "rtz")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN")
- (const_string "rdn")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP")
- (const_string "rup")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM")
- (const_string "rmm")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN")
- (const_string "dyn")]
- (const_string "none"))]
- (const_string "none")))
+ (const_string "dyn")]
+ (const_string "none")))
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
@@ -6147,7 +6129,9 @@ (define_insn "@pred_<optab><mode>"
"TARGET_VECTOR"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6190,7 +6174,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6234,7 +6220,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_reverse_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6257,7 +6245,9 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
"TARGET_VECTOR"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<copysign><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6408,7 +6398,9 @@ (define_insn "*pred_<madd_msub><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6441,7 +6433,9 @@ (define_insn "*pred_<macc_msac><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6478,7 +6472,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6535,7 +6531,9 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6569,7 +6567,9 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6606,7 +6606,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand")
@@ -6668,7 +6670,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6702,7 +6706,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6740,7 +6746,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6799,7 +6807,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6834,7 +6844,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6872,7 +6884,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point unary operations
@@ -6908,7 +6922,9 @@ (define_insn "@pred_<optab><mode>"
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -7002,7 +7018,9 @@ (define_insn "@pred_dual_widen_<optab><mode>"
"TARGET_VECTOR"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_dual_widen_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7027,7 +7045,9 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_add<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7050,7 +7070,9 @@ (define_insn "@pred_single_widen_add<mode>"
"TARGET_VECTOR"
"vfwadd.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_sub<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7073,7 +7095,9 @@ (define_insn "@pred_single_widen_sub<mode>"
"TARGET_VECTOR"
"vfwsub.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7097,7 +7121,9 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated widen floating-point ternary operations
@@ -7130,7 +7156,9 @@ (define_insn "@pred_widen_mul_<optab><mode>"
"TARGET_VECTOR"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7157,7 +7185,9 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7184,7 +7214,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7212,7 +7244,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point comparison operations
@@ -7522,7 +7556,9 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<fix_cvt><mode>"
[(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
@@ -7562,7 +7598,9 @@ (define_insn "@pred_<float_cvt><mode>"
"TARGET_VECTOR"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point widen conversions
@@ -7590,7 +7628,9 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_widen_<fix_cvt><mode>"
[(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
@@ -7675,7 +7715,9 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_narrow_<fix_cvt><mode>"
[(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7715,7 +7757,9 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
"TARGET_VECTOR"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7736,7 +7780,9 @@ (define_insn "@pred_trunc<mode>"
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -8016,7 +8062,9 @@ (define_insn "@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for SF
(define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
@@ -8042,7 +8090,9 @@ (define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for DF
(define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
@@ -8068,7 +8118,9 @@ (define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VDF:MODE>")])
+ (set_attr "mode" "<VDF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for HF, aka SF = HF op SF
(define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
@@ -8090,7 +8142,9 @@ (define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for SF, aka DF = SF * DF
(define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
@@ -8112,7 +8166,9 @@ (define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated permutation operations
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-07 1:34 ` Li, Pan2
@ 2023-08-07 3:26 ` Kito Cheng
2023-08-07 3:45 ` Li, Pan2
0 siblings, 1 reply; 17+ messages in thread
From: Kito Cheng @ 2023-08-07 3:26 UTC (permalink / raw)
To: Li, Pan2; +Cc: juzhe.zhong, gcc-patches, Wang, Yanzhang
What about using similar way as vlmul?
# NOTE: diff is based on your patch.
[kitoc@hsinchu02 riscv]$ git diff
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 33f7cb1d670..3cb5c23cb09 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -345,6 +345,7 @@ enum floating_point_rounding_mode
FRM_DYN = 7, /* Aka 0b111. */
FRM_STATIC_MIN = FRM_RNE,
FRM_STATIC_MAX = FRM_RMM,
+ FRM_NONE = 8,
};
opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index d5fb8611d6e..3d5dc0c11be 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -112,6 +112,7 @@ public:
{
m_has_fp_rounding_mode_p = true;
m_fp_rounding_mode = mode;
+ gcc_assert (mode != FRM_NONE);
}
void add_output_operand (rtx x, machine_mode mode)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index f966f1ba769..c1a7650fe85 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -865,9 +865,9 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
(const_string "none")))
;; Defines rounding mode of an floating-point operation.
-(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
+(define_attr "frm_mode" ""
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfdiv,vfwmul")
- (const_string "dyn")]
+ (const_string "FRM_DYN")]
(const_string "none")))
;; -----------------------------------------------------------------
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-07 3:26 ` Kito Cheng
@ 2023-08-07 3:45 ` Li, Pan2
2023-08-07 6:35 ` Kito Cheng
0 siblings, 1 reply; 17+ messages in thread
From: Li, Pan2 @ 2023-08-07 3:45 UTC (permalink / raw)
To: Kito Cheng; +Cc: juzhe.zhong, gcc-patches, Wang, Yanzhang
I am not quite sure if I understand it correctly, but I bet below enums are required by RISC-V mode switching, like FRM_MODE_DYN in entry, or FRM_MODE_CALL/EXIT in emit.
> ;; Defines rounding mode of an floating-point operation.
> -(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
> +(define_attr "frm_mode" ""
> (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfdiv,vfwmul")
> - (const_string "dyn")]
> + (const_string "FRM_DYN")]
> (const_string "none")))
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Monday, August 7, 2023 11:27 AM
To: Li, Pan2 <pan2.li@intel.com>
Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
What about using similar way as vlmul?
# NOTE: diff is based on your patch.
[kitoc@hsinchu02 riscv]$ git diff
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 33f7cb1d670..3cb5c23cb09 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -345,6 +345,7 @@ enum floating_point_rounding_mode
FRM_DYN = 7, /* Aka 0b111. */
FRM_STATIC_MIN = FRM_RNE,
FRM_STATIC_MAX = FRM_RMM,
+ FRM_NONE = 8,
};
opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index d5fb8611d6e..3d5dc0c11be 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -112,6 +112,7 @@ public:
{
m_has_fp_rounding_mode_p = true;
m_fp_rounding_mode = mode;
+ gcc_assert (mode != FRM_NONE);
}
void add_output_operand (rtx x, machine_mode mode)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index f966f1ba769..c1a7650fe85 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -865,9 +865,9 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
(const_string "none")))
;; Defines rounding mode of an floating-point operation.
-(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
+(define_attr "frm_mode" ""
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfdiv,vfwmul")
- (const_string "dyn")]
+ (const_string "FRM_DYN")]
(const_string "none")))
;; -----------------------------------------------------------------
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-07 3:45 ` Li, Pan2
@ 2023-08-07 6:35 ` Kito Cheng
2023-08-07 13:13 ` Li, Pan2
0 siblings, 1 reply; 17+ messages in thread
From: Kito Cheng @ 2023-08-07 6:35 UTC (permalink / raw)
To: Li, Pan2; +Cc: juzhe.zhong, gcc-patches, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 2782 bytes --]
A build-able patch attached, again, it's based on your patch :)
On Mon, Aug 7, 2023 at 11:46 AM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> I am not quite sure if I understand it correctly, but I bet below enums are required by RISC-V mode switching, like FRM_MODE_DYN in entry, or FRM_MODE_CALL/EXIT in emit.
>
> > ;; Defines rounding mode of an floating-point operation.
> > -(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
> > +(define_attr "frm_mode" ""
> > (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfdiv,vfwmul")
> > - (const_string "dyn")]
> > + (const_string "FRM_DYN")]
> > (const_string "none")))
>
> Pan
>
> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com>
> Sent: Monday, August 7, 2023 11:27 AM
> To: Li, Pan2 <pan2.li@intel.com>
> Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: Re: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
>
> What about using similar way as vlmul?
>
>
> # NOTE: diff is based on your patch.
> [kitoc@hsinchu02 riscv]$ git diff
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 33f7cb1d670..3cb5c23cb09 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -345,6 +345,7 @@ enum floating_point_rounding_mode
> FRM_DYN = 7, /* Aka 0b111. */
> FRM_STATIC_MIN = FRM_RNE,
> FRM_STATIC_MAX = FRM_RMM,
> + FRM_NONE = 8,
> };
>
> opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index d5fb8611d6e..3d5dc0c11be 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -112,6 +112,7 @@ public:
> {
> m_has_fp_rounding_mode_p = true;
> m_fp_rounding_mode = mode;
> + gcc_assert (mode != FRM_NONE);
> }
>
> void add_output_operand (rtx x, machine_mode mode)
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index f966f1ba769..c1a7650fe85 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -865,9 +865,9 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
> (const_string "none")))
>
> ;; Defines rounding mode of an floating-point operation.
> -(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
> +(define_attr "frm_mode" ""
> (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfdiv,vfwmul")
> - (const_string "dyn")]
> + (const_string "FRM_DYN")]
> (const_string "none")))
>
> ;; -----------------------------------------------------------------
[-- Attachment #2: 0001-f.patch --]
[-- Type: text/x-patch, Size: 25441 bytes --]
From 29bfcda510cd86f6b4804e0ea2178b2ce8e6671d Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng@sifive.com>
Date: Mon, 7 Aug 2023 14:34:12 +0800
Subject: [PATCH] f
---
gcc/config/riscv/riscv-protos.h | 5 ++-
gcc/config/riscv/riscv-v.cc | 19 ++++----
gcc/config/riscv/riscv.cc | 38 ++++++++--------
gcc/config/riscv/riscv.h | 2 +-
gcc/config/riscv/vector.md | 80 ++++++++++++++++-----------------
5 files changed, 74 insertions(+), 70 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 33f7cb1d670..395f056f8d2 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -236,7 +236,6 @@ bool check_builtin_call (location_t, vec<location_t>, unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
bool legitimize_move (rtx, rtx);
-int get_frm_mode (rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);
@@ -345,8 +344,12 @@ enum floating_point_rounding_mode
FRM_DYN = 7, /* Aka 0b111. */
FRM_STATIC_MIN = FRM_RNE,
FRM_STATIC_MAX = FRM_RMM,
+ FRM_NONE = 8,
+ FRM_DYN_EXIT = 9,
+ FRM_DYN_CALL = 10,
};
+enum floating_point_rounding_mode get_frm_mode (rtx);
opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
poly_uint64);
unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index d5fb8611d6e..9ab6ae17d33 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -112,6 +112,7 @@ public:
{
m_has_fp_rounding_mode_p = true;
m_fp_rounding_mode = mode;
+ gcc_assert (mode <= FRM_DYN);
}
void add_output_operand (rtx x, machine_mode mode)
@@ -1514,8 +1515,8 @@ expand_const_vector (rtx target, rtx src)
}
/* Get the frm mode with given CONST_INT rtx, the default mode is
- FRM_MODE_DYN. */
-int
+ FRM_DYN. */
+enum floating_point_rounding_mode
get_frm_mode (rtx operand)
{
gcc_assert (CONST_INT_P (operand));
@@ -1523,19 +1524,19 @@ get_frm_mode (rtx operand)
switch (INTVAL (operand))
{
case FRM_RNE:
- return FRM_MODE_RNE;
+ return FRM_RNE;
case FRM_RTZ:
- return FRM_MODE_RTZ;
+ return FRM_RTZ;
case FRM_RDN:
- return FRM_MODE_RDN;
+ return FRM_RDN;
case FRM_RUP:
- return FRM_MODE_RUP;
+ return FRM_RUP;
case FRM_RMM:
- return FRM_MODE_RMM;
+ return FRM_RMM;
case FRM_DYN:
- return FRM_MODE_DYN;
+ return FRM_DYN;
default:
- return FRM_MODE_DYN;
+ return FRM_DYN;
}
gcc_unreachable ();
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 75646811019..966aecd4ab4 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7811,11 +7811,11 @@ riscv_static_frm_mode_p (int mode)
{
switch (mode)
{
- case FRM_MODE_RDN:
- case FRM_MODE_RUP:
- case FRM_MODE_RTZ:
- case FRM_MODE_RMM:
- case FRM_MODE_RNE:
+ case riscv_vector::FRM_RDN:
+ case riscv_vector::FRM_RUP:
+ case riscv_vector::FRM_RTZ:
+ case riscv_vector::FRM_RMM:
+ case riscv_vector::FRM_RNE:
return true;
default:
return false;
@@ -7831,12 +7831,12 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
{
rtx backup_reg = DYNAMIC_FRM_RTL (cfun);
- if (prev_mode == FRM_MODE_DYN_CALL)
+ if (prev_mode == riscv_vector::FRM_DYN_CALL)
emit_insn (gen_frrmsi (backup_reg)); /* Backup frm when DYN_CALL. */
if (mode != prev_mode)
{
- /* TODO: By design, FRM_MODE_xxx used by mode switch which is
+ /* TODO: By design, FRM_xxx used by mode switch which is
different from the FRM value like FRM_RTZ defined in
riscv-protos.h. When mode switching we actually need a conversion
function to convert the mode of mode switching to the actual
@@ -7845,14 +7845,14 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
and then we leverage this assumption when emit. */
rtx frm = gen_int_mode (mode, SImode);
- if (mode == FRM_MODE_DYN_CALL && prev_mode != FRM_MODE_DYN)
+ if (mode == riscv_vector::FRM_DYN_CALL && prev_mode != riscv_vector::FRM_DYN)
/* No need to emit when prev mode is DYN already. */
emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
- else if (mode == FRM_MODE_DYN_EXIT && STATIC_FRM_P (cfun)
- && prev_mode != FRM_MODE_DYN && prev_mode != FRM_MODE_DYN_CALL)
+ else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun)
+ && prev_mode != riscv_vector::FRM_DYN && prev_mode != riscv_vector::FRM_DYN_CALL)
/* No need to emit when prev mode is DYN or DYN_CALL already. */
emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
- else if (mode == FRM_MODE_DYN && prev_mode != FRM_MODE_DYN_CALL)
+ else if (mode == riscv_vector::FRM_DYN && prev_mode != riscv_vector::FRM_DYN_CALL)
/* Restore frm value from backup when switch to DYN mode. */
emit_insn (gen_fsrmsi_restore (backup_reg));
else if (riscv_static_frm_mode_p (mode))
@@ -7881,7 +7881,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
}
}
-/* Adjust the FRM_MODE_NONE insn after a call to FRM_MODE_DYN for the
+/* Adjust the FRM_NONE insn after a call to FRM_DYN for the
underlying emit. */
static int
@@ -7890,7 +7890,7 @@ riscv_frm_adjust_mode_after_call (rtx_insn *cur_insn, int mode)
rtx_insn *insn = prev_nonnote_nondebug_insn_bb (cur_insn);
if (insn && CALL_P (insn))
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
return mode;
}
@@ -7941,12 +7941,12 @@ riscv_frm_mode_needed (rtx_insn *cur_insn, int code)
if (!insn)
riscv_frm_emit_after_bb_end (cur_insn);
- return FRM_MODE_DYN_CALL;
+ return riscv_vector::FRM_DYN_CALL;
}
- int mode = code >= 0 ? get_attr_frm_mode (cur_insn) : FRM_MODE_NONE;
+ int mode = code >= 0 ? get_attr_frm_mode (cur_insn) : riscv_vector::FRM_NONE;
- if (mode == FRM_MODE_NONE)
+ if (mode == riscv_vector::FRM_NONE)
/* After meet a call, we need to backup the frm because it may be
updated during the call. Here, for each insn, we will check if
the previous insn is a call or not. When previous insn is call,
@@ -8054,7 +8054,7 @@ riscv_frm_mode_after (rtx_insn *insn, int mode)
return mode;
if (frm_unknown_dynamic_p (insn))
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
if (recog_memoized (insn) < 0)
return mode;
@@ -8096,7 +8096,7 @@ riscv_mode_entry (int entity)
/* According to RVV 1.0 spec, all vector floating-point operations use
the dynamic rounding mode in the frm register. Likewise in other
similar places. */
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
}
default:
gcc_unreachable ();
@@ -8114,7 +8114,7 @@ riscv_mode_exit (int entity)
case RISCV_VXRM:
return VXRM_MODE_NONE;
case RISCV_FRM:
- return FRM_MODE_DYN_EXIT;
+ return riscv_vector::FRM_DYN_EXIT;
default:
gcc_unreachable ();
}
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 0a19adc1329..e18a0081297 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1120,6 +1120,6 @@ extern void riscv_remove_unneeded_save_restore_calls (void);
/* Mode switching (Lazy code motion) for RVV rounding mode instructions. */
#define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
-#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, FRM_MODE_NONE}
+#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
#endif /* ! GCC_RISCV_H */
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index f966f1ba769..343dc5a83ae 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -865,10 +865,10 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
(const_string "none")))
;; Defines rounding mode of an floating-point operation.
-(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
+(define_attr "frm_mode" ""
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfdiv,vfwmul")
- (const_string "dyn")]
- (const_string "none")))
+ (symbol_ref "riscv_vector::FRM_DYN")]
+ (symbol_ref "riscv_vector::FRM_NONE")))
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
@@ -6131,7 +6131,7 @@ (define_insn "@pred_<optab><mode>"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6176,7 +6176,7 @@ (define_insn "@pred_<optab><mode>_scalar"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6222,7 +6222,7 @@ (define_insn "@pred_<optab><mode>_scalar"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_reverse_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6247,7 +6247,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<copysign><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6400,7 +6400,7 @@ (define_insn "*pred_<madd_msub><mode>"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6435,7 +6435,7 @@ (define_insn "*pred_<macc_msac><mode>"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6474,7 +6474,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6533,7 +6533,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6569,7 +6569,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6608,7 +6608,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand")
@@ -6672,7 +6672,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6708,7 +6708,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6748,7 +6748,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6809,7 +6809,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6846,7 +6846,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6886,7 +6886,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point unary operations
@@ -6924,7 +6924,7 @@ (define_insn "@pred_<optab><mode>"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -7020,7 +7020,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_dual_widen_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7047,7 +7047,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_add<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7072,7 +7072,7 @@ (define_insn "@pred_single_widen_add<mode>"
[(set_attr "type" "vfwalu")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_sub<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7097,7 +7097,7 @@ (define_insn "@pred_single_widen_sub<mode>"
[(set_attr "type" "vfwalu")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7123,7 +7123,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated widen floating-point ternary operations
@@ -7158,7 +7158,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7187,7 +7187,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7216,7 +7216,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7246,7 +7246,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point comparison operations
@@ -7558,7 +7558,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
[(set_attr "type" "vfcvtftoi")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<fix_cvt><mode>"
[(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
@@ -7600,7 +7600,7 @@ (define_insn "@pred_<float_cvt><mode>"
[(set_attr "type" "vfcvtitof")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point widen conversions
@@ -7630,7 +7630,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_widen_<fix_cvt><mode>"
[(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
@@ -7717,7 +7717,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_narrow_<fix_cvt><mode>"
[(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7759,7 +7759,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
[(set_attr "type" "vfncvtitof")
(set_attr "mode" "<VNCONVERT>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7782,7 +7782,7 @@ (define_insn "@pred_trunc<mode>"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -8064,7 +8064,7 @@ (define_insn "@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<VHF:MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for SF
(define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
@@ -8092,7 +8092,7 @@ (define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<VSF:MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for DF
(define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
@@ -8120,7 +8120,7 @@ (define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<VDF:MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for HF, aka SF = HF op SF
(define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
@@ -8144,7 +8144,7 @@ (define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<VHF:MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for SF, aka DF = SF * DF
(define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
@@ -8168,7 +8168,7 @@ (define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<VSF:MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated permutation operations
--
2.40.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-07 6:35 ` Kito Cheng
@ 2023-08-07 13:13 ` Li, Pan2
0 siblings, 0 replies; 17+ messages in thread
From: Li, Pan2 @ 2023-08-07 13:13 UTC (permalink / raw)
To: Kito Cheng; +Cc: juzhe.zhong, gcc-patches, Wang, Yanzhang
Got you point, thanks kito and will send patch v2 after test.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Monday, August 7, 2023 2:35 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
A build-able patch attached, again, it's based on your patch :)
On Mon, Aug 7, 2023 at 11:46 AM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> I am not quite sure if I understand it correctly, but I bet below enums are required by RISC-V mode switching, like FRM_MODE_DYN in entry, or FRM_MODE_CALL/EXIT in emit.
>
> > ;; Defines rounding mode of an floating-point operation.
> > -(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
> > +(define_attr "frm_mode" ""
> > (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfdiv,vfwmul")
> > - (const_string "dyn")]
> > + (const_string "FRM_DYN")]
> > (const_string "none")))
>
> Pan
>
> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com>
> Sent: Monday, August 7, 2023 11:27 AM
> To: Li, Pan2 <pan2.li@intel.com>
> Cc: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: Re: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
>
> What about using similar way as vlmul?
>
>
> # NOTE: diff is based on your patch.
> [kitoc@hsinchu02 riscv]$ git diff
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 33f7cb1d670..3cb5c23cb09 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -345,6 +345,7 @@ enum floating_point_rounding_mode
> FRM_DYN = 7, /* Aka 0b111. */
> FRM_STATIC_MIN = FRM_RNE,
> FRM_STATIC_MAX = FRM_RMM,
> + FRM_NONE = 8,
> };
>
> opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index d5fb8611d6e..3d5dc0c11be 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -112,6 +112,7 @@ public:
> {
> m_has_fp_rounding_mode_p = true;
> m_fp_rounding_mode = mode;
> + gcc_assert (mode != FRM_NONE);
> }
>
> void add_output_operand (rtx x, machine_mode mode)
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index f966f1ba769..c1a7650fe85 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -865,9 +865,9 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
> (const_string "none")))
>
> ;; Defines rounding mode of an floating-point operation.
> -(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
> +(define_attr "frm_mode" ""
> (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfdiv,vfwmul")
> - (const_string "dyn")]
> + (const_string "FRM_DYN")]
> (const_string "none")))
>
> ;; -----------------------------------------------------------------
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-06 3:36 [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic pan2.li
2023-08-07 0:45 ` juzhe.zhong
@ 2023-08-08 5:25 ` pan2.li
2023-08-10 2:11 ` Kito Cheng
2023-08-10 3:12 ` [PATCH v3] " pan2.li
2 siblings, 1 reply; 17+ messages in thread
From: pan2.li @ 2023-08-08 5:25 UTC (permalink / raw)
To: gcc-patches
Cc: juzhe.zhong, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng, Kito Cheng
From: Pan Li <pan2.li@intel.com>
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the define insn has frm operands.
This patch would like to refactor frm and eliminate the above
assumptions, as well as unblock the underlying rounding mode intrinsic
API support.
After refactor, the default frm will be none, and the selected insn type
will be dyn. For the floating point which honors the frm, we will
set the frm_mode attr explicitly in define_insn.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-by: Kito Cheng <kito.cheng@sifive.com>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_frm_mode): Remove operand
assumptions.
* config/riscv/riscv-v.cc (get_frm_mode): New function.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn):
* config/riscv/vector.md: Set frm_mode attr explicitly.
gcc/ChangeLog:
* config/riscv/riscv-protos.h
(enum floating_point_rounding_mode): Add NONE, DYN_EXIT and DYN_CALL.
(get_frm_mode): New declaration.
* config/riscv/riscv-v.cc (get_frm_mode): New function to get frm mode.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn): Take care of frm reg.
* config/riscv/riscv.cc (riscv_static_frm_mode_p): Migrate to FRM_XXX.
(riscv_emit_frm_mode_set): Ditto.
(riscv_emit_mode_set): Ditto.
(riscv_frm_adjust_mode_after_call): Ditto.
(riscv_frm_mode_needed): Ditto.
(riscv_frm_mode_after): Ditto.
(riscv_mode_entry): Ditto.
(riscv_mode_exit): Ditto.
* config/riscv/riscv.h (NUM_MODES_FOR_MODE_SWITCHING): Ditto.
* config/riscv/vector.md
(rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none): Removed
(symbol_ref): * config/riscv/vector.md: Set frm_mode attr explicitly.
---
gcc/config/riscv/riscv-protos.h | 4 +
gcc/config/riscv/riscv-v.cc | 29 ++++
gcc/config/riscv/riscv-vector-builtins.cc | 22 ++-
gcc/config/riscv/riscv.cc | 46 +++---
gcc/config/riscv/riscv.h | 2 +-
gcc/config/riscv/vector.md | 172 ++++++++++++++--------
6 files changed, 186 insertions(+), 89 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 324991e2619..f45653848de 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -344,8 +344,12 @@ enum floating_point_rounding_mode
FRM_DYN = 7, /* Aka 0b111. */
FRM_STATIC_MIN = FRM_RNE,
FRM_STATIC_MAX = FRM_RMM,
+ FRM_DYN_EXIT = 8,
+ FRM_DYN_CALL = 9,
+ FRM_NONE = 10,
};
+enum floating_point_rounding_mode get_frm_mode (rtx);
opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
poly_uint64);
unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 278452b9e05..9ab6ae17d33 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -112,6 +112,7 @@ public:
{
m_has_fp_rounding_mode_p = true;
m_fp_rounding_mode = mode;
+ gcc_assert (mode <= FRM_DYN);
}
void add_output_operand (rtx x, machine_mode mode)
@@ -1513,6 +1514,34 @@ expand_const_vector (rtx target, rtx src)
gcc_unreachable ();
}
+/* Get the frm mode with given CONST_INT rtx, the default mode is
+ FRM_DYN. */
+enum floating_point_rounding_mode
+get_frm_mode (rtx operand)
+{
+ gcc_assert (CONST_INT_P (operand));
+
+ switch (INTVAL (operand))
+ {
+ case FRM_RNE:
+ return FRM_RNE;
+ case FRM_RTZ:
+ return FRM_RTZ;
+ case FRM_RDN:
+ return FRM_RDN;
+ case FRM_RUP:
+ return FRM_RUP;
+ case FRM_RMM:
+ return FRM_RMM;
+ case FRM_DYN:
+ return FRM_DYN;
+ default:
+ return FRM_DYN;
+ }
+
+ gcc_unreachable ();
+}
+
/* Expand a pre-RA RVV data move from SRC to DEST.
It expands move for RVV fractional vector modes. */
bool
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 528dca7ae85..abab06c00ed 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)
}
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
- add_input_operand (argno);
+ {
+ if (base->has_rounding_mode_operand_p ()
+ && argno == call_expr_nargs (exp) - 2)
+ {
+ /* Since the rounding mode argument position is not consistent with
+ the instruction pattern, we need to skip rounding mode argument
+ here. */
+ continue;
+ }
+ add_input_operand (argno);
+ }
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
- /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
- We add default rounding mode for the intrinsics that didn't model rounding
- mode yet. */
+ if (base->has_rounding_mode_operand_p ())
+ add_input_operand (call_expr_nargs (exp) - 2);
+
+ /* The RVV floating-point only support dynamic rounding mode in the
+ FRM register. */
if (opno != insn_data[icode].n_generator_args)
- add_input_operand (Pmode, const0_rtx);
+ add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
return generate_insn (icode);
}
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 7728cd34569..c6ffd74905a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7947,11 +7947,11 @@ riscv_static_frm_mode_p (int mode)
{
switch (mode)
{
- case FRM_MODE_RDN:
- case FRM_MODE_RUP:
- case FRM_MODE_RTZ:
- case FRM_MODE_RMM:
- case FRM_MODE_RNE:
+ case riscv_vector::FRM_RDN:
+ case riscv_vector::FRM_RUP:
+ case riscv_vector::FRM_RTZ:
+ case riscv_vector::FRM_RMM:
+ case riscv_vector::FRM_RNE:
return true;
default:
return false;
@@ -7967,28 +7967,24 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
{
rtx backup_reg = DYNAMIC_FRM_RTL (cfun);
- if (prev_mode == FRM_MODE_DYN_CALL)
+ if (prev_mode == riscv_vector::FRM_DYN_CALL)
emit_insn (gen_frrmsi (backup_reg)); /* Backup frm when DYN_CALL. */
if (mode != prev_mode)
{
- /* TODO: By design, FRM_MODE_xxx used by mode switch which is
- different from the FRM value like FRM_RTZ defined in
- riscv-protos.h. When mode switching we actually need a conversion
- function to convert the mode of mode switching to the actual
- FRM value like FRM_RTZ. For now, the value between the mode of
- mode swith and the FRM value in riscv-protos.h take the same value,
- and then we leverage this assumption when emit. */
rtx frm = gen_int_mode (mode, SImode);
- if (mode == FRM_MODE_DYN_CALL && prev_mode != FRM_MODE_DYN)
+ if (mode == riscv_vector::FRM_DYN_CALL
+ && prev_mode != riscv_vector::FRM_DYN)
/* No need to emit when prev mode is DYN already. */
emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
- else if (mode == FRM_MODE_DYN_EXIT && STATIC_FRM_P (cfun)
- && prev_mode != FRM_MODE_DYN && prev_mode != FRM_MODE_DYN_CALL)
+ else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun)
+ && prev_mode != riscv_vector::FRM_DYN
+ && prev_mode != riscv_vector::FRM_DYN_CALL)
/* No need to emit when prev mode is DYN or DYN_CALL already. */
emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
- else if (mode == FRM_MODE_DYN && prev_mode != FRM_MODE_DYN_CALL)
+ else if (mode == riscv_vector::FRM_DYN
+ && prev_mode != riscv_vector::FRM_DYN_CALL)
/* Restore frm value from backup when switch to DYN mode. */
emit_insn (gen_fsrmsi_restore (backup_reg));
else if (riscv_static_frm_mode_p (mode))
@@ -8017,7 +8013,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
}
}
-/* Adjust the FRM_MODE_NONE insn after a call to FRM_MODE_DYN for the
+/* Adjust the FRM_NONE insn after a call to FRM_DYN for the
underlying emit. */
static int
@@ -8026,7 +8022,7 @@ riscv_frm_adjust_mode_after_call (rtx_insn *cur_insn, int mode)
rtx_insn *insn = prev_nonnote_nondebug_insn_bb (cur_insn);
if (insn && CALL_P (insn))
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
return mode;
}
@@ -8077,12 +8073,12 @@ riscv_frm_mode_needed (rtx_insn *cur_insn, int code)
if (!insn)
riscv_frm_emit_after_bb_end (cur_insn);
- return FRM_MODE_DYN_CALL;
+ return riscv_vector::FRM_DYN_CALL;
}
- int mode = code >= 0 ? get_attr_frm_mode (cur_insn) : FRM_MODE_NONE;
+ int mode = code >= 0 ? get_attr_frm_mode (cur_insn) : riscv_vector::FRM_NONE;
- if (mode == FRM_MODE_NONE)
+ if (mode == riscv_vector::FRM_NONE)
/* After meet a call, we need to backup the frm because it may be
updated during the call. Here, for each insn, we will check if
the previous insn is a call or not. When previous insn is call,
@@ -8190,7 +8186,7 @@ riscv_frm_mode_after (rtx_insn *insn, int mode)
return mode;
if (frm_unknown_dynamic_p (insn))
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
if (recog_memoized (insn) < 0)
return mode;
@@ -8232,7 +8228,7 @@ riscv_mode_entry (int entity)
/* According to RVV 1.0 spec, all vector floating-point operations use
the dynamic rounding mode in the frm register. Likewise in other
similar places. */
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
}
default:
gcc_unreachable ();
@@ -8250,7 +8246,7 @@ riscv_mode_exit (int entity)
case RISCV_VXRM:
return VXRM_MODE_NONE;
case RISCV_FRM:
- return FRM_MODE_DYN_EXIT;
+ return riscv_vector::FRM_DYN_EXIT;
default:
gcc_unreachable ();
}
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 643e7ea7330..746101ea933 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1120,6 +1120,6 @@ extern void riscv_remove_unneeded_save_restore_calls (void);
/* Mode switching (Lazy code motion) for RVV rounding mode instructions. */
#define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
-#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, FRM_MODE_NONE}
+#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
#endif /* ! GCC_RISCV_H */
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 750b2de8df9..6cdda609a5a 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -865,28 +865,10 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
(const_string "none")))
;; Defines rounding mode of an floating-point operation.
-(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
+(define_attr "frm_mode" ""
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
- (cond
- [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
- (const_string "rne")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ")
- (const_string "rtz")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN")
- (const_string "rdn")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP")
- (const_string "rup")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM")
- (const_string "rmm")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN")
- (const_string "dyn")]
- (const_string "none"))]
- (const_string "none")))
+ (symbol_ref "riscv_vector::FRM_DYN")]
+ (symbol_ref "riscv_vector::FRM_NONE")))
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
@@ -6147,7 +6129,9 @@ (define_insn "@pred_<optab><mode>"
"TARGET_VECTOR"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6190,7 +6174,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6234,7 +6220,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_reverse_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6257,7 +6245,9 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
"TARGET_VECTOR"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<copysign><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6408,7 +6398,9 @@ (define_insn "*pred_<madd_msub><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6441,7 +6433,9 @@ (define_insn "*pred_<macc_msac><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6478,7 +6472,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6535,7 +6531,9 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6569,7 +6567,9 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6606,7 +6606,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand")
@@ -6668,7 +6670,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6702,7 +6706,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6740,7 +6746,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6799,7 +6807,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6834,7 +6844,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6872,7 +6884,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
operands[5] = operands[4] = operands[0];
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point unary operations
@@ -6908,7 +6922,9 @@ (define_insn "@pred_<optab><mode>"
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -7002,7 +7018,9 @@ (define_insn "@pred_dual_widen_<optab><mode>"
"TARGET_VECTOR"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_dual_widen_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7027,7 +7045,9 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_add<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7050,7 +7070,9 @@ (define_insn "@pred_single_widen_add<mode>"
"TARGET_VECTOR"
"vfwadd.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_sub<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7073,7 +7095,9 @@ (define_insn "@pred_single_widen_sub<mode>"
"TARGET_VECTOR"
"vfwsub.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7097,7 +7121,9 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated widen floating-point ternary operations
@@ -7130,7 +7156,9 @@ (define_insn "@pred_widen_mul_<optab><mode>"
"TARGET_VECTOR"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7157,7 +7185,9 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7184,7 +7214,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7212,7 +7244,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point comparison operations
@@ -7522,7 +7556,9 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<fix_cvt><mode>"
[(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
@@ -7562,7 +7598,9 @@ (define_insn "@pred_<float_cvt><mode>"
"TARGET_VECTOR"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point widen conversions
@@ -7590,7 +7628,9 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_widen_<fix_cvt><mode>"
[(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
@@ -7675,7 +7715,9 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_narrow_<fix_cvt><mode>"
[(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7715,7 +7757,9 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
"TARGET_VECTOR"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7736,7 +7780,9 @@ (define_insn "@pred_trunc<mode>"
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -8016,7 +8062,9 @@ (define_insn "@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for SF
(define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
@@ -8042,7 +8090,9 @@ (define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for DF
(define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
@@ -8068,7 +8118,9 @@ (define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VDF:MODE>")])
+ (set_attr "mode" "<VDF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for HF, aka SF = HF op SF
(define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
@@ -8090,7 +8142,9 @@ (define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for SF, aka DF = SF * DF
(define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
@@ -8112,7 +8166,9 @@ (define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated permutation operations
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-08 5:25 ` [PATCH v2] " pan2.li
@ 2023-08-10 2:11 ` Kito Cheng
2023-08-10 2:16 ` Li, Pan2
0 siblings, 1 reply; 17+ messages in thread
From: Kito Cheng @ 2023-08-10 2:11 UTC (permalink / raw)
To: pan2.li; +Cc: gcc-patches, juzhe.zhong, jeffreyalaw, yanzhang.wang, Kito Cheng
> +/* Get the frm mode with given CONST_INT rtx, the default mode is
> + FRM_DYN. */
> +enum floating_point_rounding_mode
> +get_frm_mode (rtx operand)
> +{
> + gcc_assert (CONST_INT_P (operand));
> +
> + switch (INTVAL (operand))
> + {
> + case FRM_RNE:
> + return FRM_RNE;
> + case FRM_RTZ:
> + return FRM_RTZ;
> + case FRM_RDN:
> + return FRM_RDN;
> + case FRM_RUP:
> + return FRM_RUP;
> + case FRM_RMM:
> + return FRM_RMM;
> + case FRM_DYN:
> + return FRM_DYN;
> + default:
> + return FRM_DYN;
Should we put a gcc_unreachable or gcc_assert here? I am not sure if
another value is valid when it appeared for this operand?
> + }
> +
> + gcc_unreachable ();
> +}
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v2] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-10 2:11 ` Kito Cheng
@ 2023-08-10 2:16 ` Li, Pan2
2023-08-10 2:20 ` Kito Cheng
0 siblings, 1 reply; 17+ messages in thread
From: Li, Pan2 @ 2023-08-10 2:16 UTC (permalink / raw)
To: Kito Cheng
Cc: gcc-patches, juzhe.zhong, jeffreyalaw, Wang, Yanzhang, Kito Cheng
Thanks kito. It makes sense, should not reach default, may I prepare v3(add gcc_unreachable to default) if no more comments?
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Thursday, August 10, 2023 10:12 AM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; jeffreyalaw@gmail.com; Wang, Yanzhang <yanzhang.wang@intel.com>; Kito Cheng <kito.cheng@sifive.com>
Subject: Re: [PATCH v2] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
> +/* Get the frm mode with given CONST_INT rtx, the default mode is
> + FRM_DYN. */
> +enum floating_point_rounding_mode
> +get_frm_mode (rtx operand)
> +{
> + gcc_assert (CONST_INT_P (operand));
> +
> + switch (INTVAL (operand))
> + {
> + case FRM_RNE:
> + return FRM_RNE;
> + case FRM_RTZ:
> + return FRM_RTZ;
> + case FRM_RDN:
> + return FRM_RDN;
> + case FRM_RUP:
> + return FRM_RUP;
> + case FRM_RMM:
> + return FRM_RMM;
> + case FRM_DYN:
> + return FRM_DYN;
> + default:
> + return FRM_DYN;
Should we put a gcc_unreachable or gcc_assert here? I am not sure if
another value is valid when it appeared for this operand?
> + }
> +
> + gcc_unreachable ();
> +}
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-10 2:16 ` Li, Pan2
@ 2023-08-10 2:20 ` Kito Cheng
2023-08-10 3:13 ` Li, Pan2
0 siblings, 1 reply; 17+ messages in thread
From: Kito Cheng @ 2023-08-10 2:20 UTC (permalink / raw)
To: Li, Pan2
Cc: Kito Cheng, gcc-patches, juzhe.zhong, jeffreyalaw, Wang, Yanzhang
Yeah, no further comment from me :)
On Thu, Aug 10, 2023 at 10:16 AM Li, Pan2 <pan2.li@intel.com> wrote:
>
> Thanks kito. It makes sense, should not reach default, may I prepare v3(add gcc_unreachable to default) if no more comments?
>
> Pan
>
> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com>
> Sent: Thursday, August 10, 2023 10:12 AM
> To: Li, Pan2 <pan2.li@intel.com>
> Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; jeffreyalaw@gmail.com; Wang, Yanzhang <yanzhang.wang@intel.com>; Kito Cheng <kito.cheng@sifive.com>
> Subject: Re: [PATCH v2] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
>
> > +/* Get the frm mode with given CONST_INT rtx, the default mode is
> > + FRM_DYN. */
> > +enum floating_point_rounding_mode
> > +get_frm_mode (rtx operand)
> > +{
> > + gcc_assert (CONST_INT_P (operand));
> > +
> > + switch (INTVAL (operand))
> > + {
> > + case FRM_RNE:
> > + return FRM_RNE;
> > + case FRM_RTZ:
> > + return FRM_RTZ;
> > + case FRM_RDN:
> > + return FRM_RDN;
> > + case FRM_RUP:
> > + return FRM_RUP;
> > + case FRM_RMM:
> > + return FRM_RMM;
> > + case FRM_DYN:
> > + return FRM_DYN;
> > + default:
> > + return FRM_DYN;
>
> Should we put a gcc_unreachable or gcc_assert here? I am not sure if
> another value is valid when it appeared for this operand?
>
> > + }
> > +
> > + gcc_unreachable ();
> > +}
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-06 3:36 [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic pan2.li
2023-08-07 0:45 ` juzhe.zhong
2023-08-08 5:25 ` [PATCH v2] " pan2.li
@ 2023-08-10 3:12 ` pan2.li
2023-08-10 3:13 ` Kito Cheng
2 siblings, 1 reply; 17+ messages in thread
From: pan2.li @ 2023-08-10 3:12 UTC (permalink / raw)
To: gcc-patches
Cc: juzhe.zhong, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng, Kito Cheng
From: Pan Li <pan2.li@intel.com>
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the define insn has frm operands.
This patch would like to refactor frm and eliminate the above
assumptions, as well as unblock the underlying rounding mode intrinsic
API support.
After refactor, the default frm will be none, and the selected insn type
will be dyn. For the floating point which honors the frm, we will
set the frm_mode attr explicitly in define_insn.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-by: Kito Cheng <kito.cheng@sifive.com>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_frm_mode): Remove operand
assumptions.
* config/riscv/riscv-v.cc (get_frm_mode): New function.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn):
* config/riscv/vector.md: Set frm_mode attr explicitly.
gcc/ChangeLog:
* config/riscv/riscv-protos.h
(enum floating_point_rounding_mode): Add NONE, DYN_EXIT and DYN_CALL.
(get_frm_mode): New declaration.
* config/riscv/riscv-v.cc (get_frm_mode): New function to get frm mode.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn): Take care of frm reg.
* config/riscv/riscv.cc (riscv_static_frm_mode_p): Migrate to FRM_XXX.
(riscv_emit_frm_mode_set): Ditto.
(riscv_emit_mode_set): Ditto.
(riscv_frm_adjust_mode_after_call): Ditto.
(riscv_frm_mode_needed): Ditto.
(riscv_frm_mode_after): Ditto.
(riscv_mode_entry): Ditto.
(riscv_mode_exit): Ditto.
* config/riscv/riscv.h (NUM_MODES_FOR_MODE_SWITCHING): Ditto.
* config/riscv/vector.md
(rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none): Removed
(symbol_ref): * config/riscv/vector.md: Set frm_mode attr explicitly.
---
gcc/config/riscv/riscv-protos.h | 4 +
gcc/config/riscv/riscv-v.cc | 29 ++++
gcc/config/riscv/riscv-vector-builtins.cc | 22 ++-
gcc/config/riscv/riscv.cc | 46 +++---
gcc/config/riscv/riscv.h | 2 +-
gcc/config/riscv/vector.md | 172 ++++++++++++++--------
6 files changed, 186 insertions(+), 89 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index ac9c4b02f17..2fbed04ff84 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -349,8 +349,12 @@ enum floating_point_rounding_mode
FRM_DYN = 7, /* Aka 0b111. */
FRM_STATIC_MIN = FRM_RNE,
FRM_STATIC_MAX = FRM_RMM,
+ FRM_DYN_EXIT = 8,
+ FRM_DYN_CALL = 9,
+ FRM_NONE = 10,
};
+enum floating_point_rounding_mode get_frm_mode (rtx);
opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
poly_uint64);
unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 0bea04c1967..c9f0a4a9e7b 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -112,6 +112,7 @@ public:
{
m_has_fp_rounding_mode_p = true;
m_fp_rounding_mode = mode;
+ gcc_assert (mode <= FRM_DYN);
}
void add_output_operand (rtx x, machine_mode mode)
@@ -1590,6 +1591,34 @@ expand_const_vector (rtx target, rtx src)
gcc_unreachable ();
}
+/* Get the frm mode with given CONST_INT rtx, the default mode is
+ FRM_DYN. */
+enum floating_point_rounding_mode
+get_frm_mode (rtx operand)
+{
+ gcc_assert (CONST_INT_P (operand));
+
+ switch (INTVAL (operand))
+ {
+ case FRM_RNE:
+ return FRM_RNE;
+ case FRM_RTZ:
+ return FRM_RTZ;
+ case FRM_RDN:
+ return FRM_RDN;
+ case FRM_RUP:
+ return FRM_RUP;
+ case FRM_RMM:
+ return FRM_RMM;
+ case FRM_DYN:
+ return FRM_DYN;
+ default:
+ gcc_unreachable ();
+ }
+
+ gcc_unreachable ();
+}
+
/* Expand a pre-RA RVV data move from SRC to DEST.
It expands move for RVV fractional vector modes. */
bool
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 528dca7ae85..abab06c00ed 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)
}
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
- add_input_operand (argno);
+ {
+ if (base->has_rounding_mode_operand_p ()
+ && argno == call_expr_nargs (exp) - 2)
+ {
+ /* Since the rounding mode argument position is not consistent with
+ the instruction pattern, we need to skip rounding mode argument
+ here. */
+ continue;
+ }
+ add_input_operand (argno);
+ }
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
- /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
- We add default rounding mode for the intrinsics that didn't model rounding
- mode yet. */
+ if (base->has_rounding_mode_operand_p ())
+ add_input_operand (call_expr_nargs (exp) - 2);
+
+ /* The RVV floating-point only support dynamic rounding mode in the
+ FRM register. */
if (opno != insn_data[icode].n_generator_args)
- add_input_operand (Pmode, const0_rtx);
+ add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
return generate_insn (icode);
}
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index dfb519ab9a8..bb9815a01d7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8054,11 +8054,11 @@ riscv_static_frm_mode_p (int mode)
{
switch (mode)
{
- case FRM_MODE_RDN:
- case FRM_MODE_RUP:
- case FRM_MODE_RTZ:
- case FRM_MODE_RMM:
- case FRM_MODE_RNE:
+ case riscv_vector::FRM_RDN:
+ case riscv_vector::FRM_RUP:
+ case riscv_vector::FRM_RTZ:
+ case riscv_vector::FRM_RMM:
+ case riscv_vector::FRM_RNE:
return true;
default:
return false;
@@ -8074,28 +8074,24 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
{
rtx backup_reg = DYNAMIC_FRM_RTL (cfun);
- if (prev_mode == FRM_MODE_DYN_CALL)
+ if (prev_mode == riscv_vector::FRM_DYN_CALL)
emit_insn (gen_frrmsi (backup_reg)); /* Backup frm when DYN_CALL. */
if (mode != prev_mode)
{
- /* TODO: By design, FRM_MODE_xxx used by mode switch which is
- different from the FRM value like FRM_RTZ defined in
- riscv-protos.h. When mode switching we actually need a conversion
- function to convert the mode of mode switching to the actual
- FRM value like FRM_RTZ. For now, the value between the mode of
- mode swith and the FRM value in riscv-protos.h take the same value,
- and then we leverage this assumption when emit. */
rtx frm = gen_int_mode (mode, SImode);
- if (mode == FRM_MODE_DYN_CALL && prev_mode != FRM_MODE_DYN)
+ if (mode == riscv_vector::FRM_DYN_CALL
+ && prev_mode != riscv_vector::FRM_DYN)
/* No need to emit when prev mode is DYN already. */
emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
- else if (mode == FRM_MODE_DYN_EXIT && STATIC_FRM_P (cfun)
- && prev_mode != FRM_MODE_DYN && prev_mode != FRM_MODE_DYN_CALL)
+ else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun)
+ && prev_mode != riscv_vector::FRM_DYN
+ && prev_mode != riscv_vector::FRM_DYN_CALL)
/* No need to emit when prev mode is DYN or DYN_CALL already. */
emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
- else if (mode == FRM_MODE_DYN && prev_mode != FRM_MODE_DYN_CALL)
+ else if (mode == riscv_vector::FRM_DYN
+ && prev_mode != riscv_vector::FRM_DYN_CALL)
/* Restore frm value from backup when switch to DYN mode. */
emit_insn (gen_fsrmsi_restore (backup_reg));
else if (riscv_static_frm_mode_p (mode))
@@ -8124,7 +8120,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
}
}
-/* Adjust the FRM_MODE_NONE insn after a call to FRM_MODE_DYN for the
+/* Adjust the FRM_NONE insn after a call to FRM_DYN for the
underlying emit. */
static int
@@ -8133,7 +8129,7 @@ riscv_frm_adjust_mode_after_call (rtx_insn *cur_insn, int mode)
rtx_insn *insn = prev_nonnote_nondebug_insn_bb (cur_insn);
if (insn && CALL_P (insn))
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
return mode;
}
@@ -8184,12 +8180,12 @@ riscv_frm_mode_needed (rtx_insn *cur_insn, int code)
if (!insn)
riscv_frm_emit_after_bb_end (cur_insn);
- return FRM_MODE_DYN_CALL;
+ return riscv_vector::FRM_DYN_CALL;
}
- int mode = code >= 0 ? get_attr_frm_mode (cur_insn) : FRM_MODE_NONE;
+ int mode = code >= 0 ? get_attr_frm_mode (cur_insn) : riscv_vector::FRM_NONE;
- if (mode == FRM_MODE_NONE)
+ if (mode == riscv_vector::FRM_NONE)
/* After meet a call, we need to backup the frm because it may be
updated during the call. Here, for each insn, we will check if
the previous insn is a call or not. When previous insn is call,
@@ -8297,7 +8293,7 @@ riscv_frm_mode_after (rtx_insn *insn, int mode)
return mode;
if (frm_unknown_dynamic_p (insn))
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
if (recog_memoized (insn) < 0)
return mode;
@@ -8339,7 +8335,7 @@ riscv_mode_entry (int entity)
/* According to RVV 1.0 spec, all vector floating-point operations use
the dynamic rounding mode in the frm register. Likewise in other
similar places. */
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
}
default:
gcc_unreachable ();
@@ -8357,7 +8353,7 @@ riscv_mode_exit (int entity)
case RISCV_VXRM:
return VXRM_MODE_NONE;
case RISCV_FRM:
- return FRM_MODE_DYN_EXIT;
+ return riscv_vector::FRM_DYN_EXIT;
default:
gcc_unreachable ();
}
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 643e7ea7330..746101ea933 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1120,6 +1120,6 @@ extern void riscv_remove_unneeded_save_restore_calls (void);
/* Mode switching (Lazy code motion) for RVV rounding mode instructions. */
#define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
-#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, FRM_MODE_NONE}
+#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
#endif /* ! GCC_RISCV_H */
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 65b5fe456ed..cf37b472930 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -865,28 +865,10 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
(const_string "none")))
;; Defines rounding mode of an floating-point operation.
-(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
+(define_attr "frm_mode" ""
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
- (cond
- [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
- (const_string "rne")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ")
- (const_string "rtz")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN")
- (const_string "rdn")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP")
- (const_string "rup")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM")
- (const_string "rmm")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN")
- (const_string "dyn")]
- (const_string "none"))]
- (const_string "none")))
+ (symbol_ref "riscv_vector::FRM_DYN")]
+ (symbol_ref "riscv_vector::FRM_NONE")))
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
@@ -6021,7 +6003,9 @@ (define_insn "@pred_<optab><mode>"
"TARGET_VECTOR"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6064,7 +6048,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6108,7 +6094,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_reverse_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6131,7 +6119,9 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
"TARGET_VECTOR"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<copysign><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6279,7 +6269,9 @@ (define_insn "*pred_<madd_msub><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6312,7 +6304,9 @@ (define_insn "*pred_<macc_msac><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr")
@@ -6343,7 +6337,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
riscv_vector::prepare_ternary_operands (operands, true);
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6400,7 +6396,9 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6434,7 +6432,9 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr")
@@ -6465,7 +6465,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
riscv_vector::prepare_ternary_operands (operands, true);
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand")
@@ -6524,7 +6526,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6558,7 +6562,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr")
@@ -6590,7 +6596,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
riscv_vector::prepare_ternary_operands (operands, true);
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6649,7 +6657,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6684,7 +6694,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr")
@@ -6716,7 +6728,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
riscv_vector::prepare_ternary_operands (operands, true);
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point unary operations
@@ -6752,7 +6766,9 @@ (define_insn "@pred_<optab><mode>"
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6846,7 +6862,9 @@ (define_insn "@pred_dual_widen_<optab><mode>"
"TARGET_VECTOR"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_dual_widen_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -6871,7 +6889,9 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_add<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -6894,7 +6914,9 @@ (define_insn "@pred_single_widen_add<mode>"
"TARGET_VECTOR"
"vfwadd.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_sub<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -6917,7 +6939,9 @@ (define_insn "@pred_single_widen_sub<mode>"
"TARGET_VECTOR"
"vfwsub.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -6941,7 +6965,9 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated widen floating-point ternary operations
@@ -6974,7 +7000,9 @@ (define_insn "@pred_widen_mul_<optab><mode>"
"TARGET_VECTOR"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7001,7 +7029,9 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7028,7 +7058,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7056,7 +7088,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point comparison operations
@@ -7366,7 +7400,9 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<fix_cvt><mode>"
[(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
@@ -7406,7 +7442,9 @@ (define_insn "@pred_<float_cvt><mode>"
"TARGET_VECTOR"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point widen conversions
@@ -7434,7 +7472,9 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_widen_<fix_cvt><mode>"
[(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
@@ -7519,7 +7559,9 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_narrow_<fix_cvt><mode>"
[(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7559,7 +7601,9 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
"TARGET_VECTOR"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7580,7 +7624,9 @@ (define_insn "@pred_trunc<mode>"
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7860,7 +7906,9 @@ (define_insn "@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for SF
(define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
@@ -7886,7 +7934,9 @@ (define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for DF
(define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
@@ -7912,7 +7962,9 @@ (define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VDF:MODE>")])
+ (set_attr "mode" "<VDF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for HF, aka SF = HF op SF
(define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
@@ -7934,7 +7986,9 @@ (define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for SF, aka DF = SF * DF
(define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
@@ -7956,7 +8010,9 @@ (define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated permutation operations
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v2] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-10 2:20 ` Kito Cheng
@ 2023-08-10 3:13 ` Li, Pan2
0 siblings, 0 replies; 17+ messages in thread
From: Li, Pan2 @ 2023-08-10 3:13 UTC (permalink / raw)
To: Kito Cheng
Cc: Kito Cheng, gcc-patches, juzhe.zhong, jeffreyalaw, Wang, Yanzhang
Thanks Kito, update it in PATCH v3, and passed riscv/rvv.exp already.
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/626918.html
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@sifive.com>
Sent: Thursday, August 10, 2023 10:21 AM
To: Li, Pan2 <pan2.li@intel.com>
Cc: Kito Cheng <kito.cheng@gmail.com>; gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; jeffreyalaw@gmail.com; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v2] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
Yeah, no further comment from me :)
On Thu, Aug 10, 2023 at 10:16 AM Li, Pan2 <pan2.li@intel.com> wrote:
>
> Thanks kito. It makes sense, should not reach default, may I prepare v3(add gcc_unreachable to default) if no more comments?
>
> Pan
>
> -----Original Message-----
> From: Kito Cheng <kito.cheng@gmail.com>
> Sent: Thursday, August 10, 2023 10:12 AM
> To: Li, Pan2 <pan2.li@intel.com>
> Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; jeffreyalaw@gmail.com; Wang, Yanzhang <yanzhang.wang@intel.com>; Kito Cheng <kito.cheng@sifive.com>
> Subject: Re: [PATCH v2] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
>
> > +/* Get the frm mode with given CONST_INT rtx, the default mode is
> > + FRM_DYN. */
> > +enum floating_point_rounding_mode
> > +get_frm_mode (rtx operand)
> > +{
> > + gcc_assert (CONST_INT_P (operand));
> > +
> > + switch (INTVAL (operand))
> > + {
> > + case FRM_RNE:
> > + return FRM_RNE;
> > + case FRM_RTZ:
> > + return FRM_RTZ;
> > + case FRM_RDN:
> > + return FRM_RDN;
> > + case FRM_RUP:
> > + return FRM_RUP;
> > + case FRM_RMM:
> > + return FRM_RMM;
> > + case FRM_DYN:
> > + return FRM_DYN;
> > + default:
> > + return FRM_DYN;
>
> Should we put a gcc_unreachable or gcc_assert here? I am not sure if
> another value is valid when it appeared for this operand?
>
> > + }
> > +
> > + gcc_unreachable ();
> > +}
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-10 3:12 ` [PATCH v3] " pan2.li
@ 2023-08-10 3:13 ` Kito Cheng
2023-08-10 4:37 ` Li, Pan2
0 siblings, 1 reply; 17+ messages in thread
From: Kito Cheng @ 2023-08-10 3:13 UTC (permalink / raw)
To: Li, Pan2
Cc: GCC Patches, 钟居哲,
Jeff Law, Wang, Yanzhang, Kito Cheng
[-- Attachment #1: Type: text/plain, Size: 32822 bytes --]
LGTM
<pan2.li@intel.com> 於 2023年8月10日 週四 11:12 寫道：
> From: Pan Li <pan2.li@intel.com>
>
> The frm_mode attr has some assumptions for each define insn as below.
>
> 1. The define insn has at least 9 operands.
> 2. The operands[9] must be frm reg.
> 3. The operands[9] must be const int.
>
> Actually, the frm operand can be operands[8], operands[9] or
> operands[10], and not all the define insn has frm operands.
>
> This patch would like to refactor frm and eliminate the above
> assumptions, as well as unblock the underlying rounding mode intrinsic
> API support.
>
> After refactor, the default frm will be none, and the selected insn type
> will be dyn. For the floating point which honors the frm, we will
> set the frm_mode attr explicitly in define_insn.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> Co-Authored-by: Kito Cheng <kito.cheng@sifive.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (get_frm_mode): Remove operand
> assumptions.
> * config/riscv/riscv-v.cc (get_frm_mode): New function.
> * config/riscv/riscv-vector-builtins.cc
> (function_expander::use_ternop_insn):
> * config/riscv/vector.md: Set frm_mode attr explicitly.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h
> (enum floating_point_rounding_mode): Add NONE, DYN_EXIT and
> DYN_CALL.
> (get_frm_mode): New declaration.
> * config/riscv/riscv-v.cc (get_frm_mode): New function to get frm
> mode.
> * config/riscv/riscv-vector-builtins.cc
> (function_expander::use_ternop_insn): Take care of frm reg.
> * config/riscv/riscv.cc (riscv_static_frm_mode_p): Migrate to
> FRM_XXX.
> (riscv_emit_frm_mode_set): Ditto.
> (riscv_emit_mode_set): Ditto.
> (riscv_frm_adjust_mode_after_call): Ditto.
> (riscv_frm_mode_needed): Ditto.
> (riscv_frm_mode_after): Ditto.
> (riscv_mode_entry): Ditto.
> (riscv_mode_exit): Ditto.
> * config/riscv/riscv.h (NUM_MODES_FOR_MODE_SWITCHING): Ditto.
> * config/riscv/vector.md
> (rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none): Removed
> (symbol_ref): * config/riscv/vector.md: Set frm_mode attr
> explicitly.
> ---
> gcc/config/riscv/riscv-protos.h | 4 +
> gcc/config/riscv/riscv-v.cc | 29 ++++
> gcc/config/riscv/riscv-vector-builtins.cc | 22 ++-
> gcc/config/riscv/riscv.cc | 46 +++---
> gcc/config/riscv/riscv.h | 2 +-
> gcc/config/riscv/vector.md | 172 ++++++++++++++--------
> 6 files changed, 186 insertions(+), 89 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h
> b/gcc/config/riscv/riscv-protos.h
> index ac9c4b02f17..2fbed04ff84 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -349,8 +349,12 @@ enum floating_point_rounding_mode
> FRM_DYN = 7, /* Aka 0b111. */
> FRM_STATIC_MIN = FRM_RNE,
> FRM_STATIC_MAX = FRM_RMM,
> + FRM_DYN_EXIT = 8,
> + FRM_DYN_CALL = 9,
> + FRM_NONE = 10,
> };
>
> +enum floating_point_rounding_mode get_frm_mode (rtx);
> opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
> poly_uint64);
> unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool);
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 0bea04c1967..c9f0a4a9e7b 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -112,6 +112,7 @@ public:
> {
> m_has_fp_rounding_mode_p = true;
> m_fp_rounding_mode = mode;
> + gcc_assert (mode <= FRM_DYN);
> }
>
> void add_output_operand (rtx x, machine_mode mode)
> @@ -1590,6 +1591,34 @@ expand_const_vector (rtx target, rtx src)
> gcc_unreachable ();
> }
>
> +/* Get the frm mode with given CONST_INT rtx, the default mode is
> + FRM_DYN. */
> +enum floating_point_rounding_mode
> +get_frm_mode (rtx operand)
> +{
> + gcc_assert (CONST_INT_P (operand));
> +
> + switch (INTVAL (operand))
> + {
> + case FRM_RNE:
> + return FRM_RNE;
> + case FRM_RTZ:
> + return FRM_RTZ;
> + case FRM_RDN:
> + return FRM_RDN;
> + case FRM_RUP:
> + return FRM_RUP;
> + case FRM_RMM:
> + return FRM_RMM;
> + case FRM_DYN:
> + return FRM_DYN;
> + default:
> + gcc_unreachable ();
> + }
> +
> + gcc_unreachable ();
> +}
> +
> /* Expand a pre-RA RVV data move from SRC to DEST.
> It expands move for RVV fractional vector modes. */
> bool
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
> b/gcc/config/riscv/riscv-vector-builtins.cc
> index 528dca7ae85..abab06c00ed 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool
> vd_accum_p, insn_code icode)
> }
>
> for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
> - add_input_operand (argno);
> + {
> + if (base->has_rounding_mode_operand_p ()
> + && argno == call_expr_nargs (exp) - 2)
> + {
> + /* Since the rounding mode argument position is not consistent
> with
> + the instruction pattern, we need to skip rounding mode
> argument
> + here. */
> + continue;
> + }
> + add_input_operand (argno);
> + }
>
> add_input_operand (Pmode, get_tail_policy_for_pred (pred));
> add_input_operand (Pmode, get_mask_policy_for_pred (pred));
> add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
>
> - /* TODO: Currently, we don't support intrinsic that is modeling
> rounding mode.
> - We add default rounding mode for the intrinsics that didn't model
> rounding
> - mode yet. */
> + if (base->has_rounding_mode_operand_p ())
> + add_input_operand (call_expr_nargs (exp) - 2);
> +
> + /* The RVV floating-point only support dynamic rounding mode in the
> + FRM register. */
> if (opno != insn_data[icode].n_generator_args)
> - add_input_operand (Pmode, const0_rtx);
> + add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN,
> Pmode));
>
> return generate_insn (icode);
> }
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index dfb519ab9a8..bb9815a01d7 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -8054,11 +8054,11 @@ riscv_static_frm_mode_p (int mode)
> {
> switch (mode)
> {
> - case FRM_MODE_RDN:
> - case FRM_MODE_RUP:
> - case FRM_MODE_RTZ:
> - case FRM_MODE_RMM:
> - case FRM_MODE_RNE:
> + case riscv_vector::FRM_RDN:
> + case riscv_vector::FRM_RUP:
> + case riscv_vector::FRM_RTZ:
> + case riscv_vector::FRM_RMM:
> + case riscv_vector::FRM_RNE:
> return true;
> default:
> return false;
> @@ -8074,28 +8074,24 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
> {
> rtx backup_reg = DYNAMIC_FRM_RTL (cfun);
>
> - if (prev_mode == FRM_MODE_DYN_CALL)
> + if (prev_mode == riscv_vector::FRM_DYN_CALL)
> emit_insn (gen_frrmsi (backup_reg)); /* Backup frm when DYN_CALL. */
>
> if (mode != prev_mode)
> {
> - /* TODO: By design, FRM_MODE_xxx used by mode switch which is
> - different from the FRM value like FRM_RTZ defined in
> - riscv-protos.h. When mode switching we actually need a conversion
> - function to convert the mode of mode switching to the actual
> - FRM value like FRM_RTZ. For now, the value between the mode of
> - mode swith and the FRM value in riscv-protos.h take the same
> value,
> - and then we leverage this assumption when emit. */
> rtx frm = gen_int_mode (mode, SImode);
>
> - if (mode == FRM_MODE_DYN_CALL && prev_mode != FRM_MODE_DYN)
> + if (mode == riscv_vector::FRM_DYN_CALL
> + && prev_mode != riscv_vector::FRM_DYN)
> /* No need to emit when prev mode is DYN already. */
> emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
> - else if (mode == FRM_MODE_DYN_EXIT && STATIC_FRM_P (cfun)
> - && prev_mode != FRM_MODE_DYN && prev_mode != FRM_MODE_DYN_CALL)
> + else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun)
> + && prev_mode != riscv_vector::FRM_DYN
> + && prev_mode != riscv_vector::FRM_DYN_CALL)
> /* No need to emit when prev mode is DYN or DYN_CALL already. */
> emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
> - else if (mode == FRM_MODE_DYN && prev_mode != FRM_MODE_DYN_CALL)
> + else if (mode == riscv_vector::FRM_DYN
> + && prev_mode != riscv_vector::FRM_DYN_CALL)
> /* Restore frm value from backup when switch to DYN mode. */
> emit_insn (gen_fsrmsi_restore (backup_reg));
> else if (riscv_static_frm_mode_p (mode))
> @@ -8124,7 +8120,7 @@ riscv_emit_mode_set (int entity, int mode, int
> prev_mode,
> }
> }
>
> -/* Adjust the FRM_MODE_NONE insn after a call to FRM_MODE_DYN for the
> +/* Adjust the FRM_NONE insn after a call to FRM_DYN for the
> underlying emit. */
>
> static int
> @@ -8133,7 +8129,7 @@ riscv_frm_adjust_mode_after_call (rtx_insn
> *cur_insn, int mode)
> rtx_insn *insn = prev_nonnote_nondebug_insn_bb (cur_insn);
>
> if (insn && CALL_P (insn))
> - return FRM_MODE_DYN;
> + return riscv_vector::FRM_DYN;
>
> return mode;
> }
> @@ -8184,12 +8180,12 @@ riscv_frm_mode_needed (rtx_insn *cur_insn, int
> code)
> if (!insn)
> riscv_frm_emit_after_bb_end (cur_insn);
>
> - return FRM_MODE_DYN_CALL;
> + return riscv_vector::FRM_DYN_CALL;
> }
>
> - int mode = code >= 0 ? get_attr_frm_mode (cur_insn) : FRM_MODE_NONE;
> + int mode = code >= 0 ? get_attr_frm_mode (cur_insn) :
> riscv_vector::FRM_NONE;
>
> - if (mode == FRM_MODE_NONE)
> + if (mode == riscv_vector::FRM_NONE)
> /* After meet a call, we need to backup the frm because it may be
> updated during the call. Here, for each insn, we will check if
> the previous insn is a call or not. When previous insn is call,
> @@ -8297,7 +8293,7 @@ riscv_frm_mode_after (rtx_insn *insn, int mode)
> return mode;
>
> if (frm_unknown_dynamic_p (insn))
> - return FRM_MODE_DYN;
> + return riscv_vector::FRM_DYN;
>
> if (recog_memoized (insn) < 0)
> return mode;
> @@ -8339,7 +8335,7 @@ riscv_mode_entry (int entity)
> /* According to RVV 1.0 spec, all vector floating-point
> operations use
> the dynamic rounding mode in the frm register. Likewise in
> other
> similar places. */
> - return FRM_MODE_DYN;
> + return riscv_vector::FRM_DYN;
> }
> default:
> gcc_unreachable ();
> @@ -8357,7 +8353,7 @@ riscv_mode_exit (int entity)
> case RISCV_VXRM:
> return VXRM_MODE_NONE;
> case RISCV_FRM:
> - return FRM_MODE_DYN_EXIT;
> + return riscv_vector::FRM_DYN_EXIT;
> default:
> gcc_unreachable ();
> }
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index 643e7ea7330..746101ea933 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -1120,6 +1120,6 @@ extern void riscv_remove_unneeded_save_restore_calls
> (void);
>
> /* Mode switching (Lazy code motion) for RVV rounding mode instructions.
> */
> #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
> -#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, FRM_MODE_NONE}
> +#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE,
> riscv_vector::FRM_NONE}
>
> #endif /* ! GCC_RISCV_H */
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 65b5fe456ed..cf37b472930 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -865,28 +865,10 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
> (const_string "none")))
>
> ;; Defines rounding mode of an floating-point operation.
> -(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
> +(define_attr "frm_mode" ""
> (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
> - (cond
> - [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
> - (const_string "rne")
> -
> - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ")
> - (const_string "rtz")
> -
> - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN")
> - (const_string "rdn")
> -
> - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP")
> - (const_string "rup")
> -
> - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM")
> - (const_string "rmm")
> -
> - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN")
> - (const_string "dyn")]
> - (const_string "none"))]
> - (const_string "none")))
> + (symbol_ref "riscv_vector::FRM_DYN")]
> + (symbol_ref "riscv_vector::FRM_NONE")))
>
> ;; -----------------------------------------------------------------
> ;; ---- Miscellaneous Operations
> @@ -6021,7 +6003,9 @@ (define_insn "@pred_<optab><mode>"
> "TARGET_VECTOR"
> "vf<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> - (set_attr "mode" "<MODE>")])
> + (set_attr "mode" "<MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "@pred_<optab><mode>"
> [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr,
> vr")
> @@ -6064,7 +6048,9 @@ (define_insn "@pred_<optab><mode>_scalar"
> "TARGET_VECTOR"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> - (set_attr "mode" "<MODE>")])
> + (set_attr "mode" "<MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "@pred_<optab><mode>_scalar"
> [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr,
> vr")
> @@ -6108,7 +6094,9 @@ (define_insn "@pred_<optab><mode>_scalar"
> "TARGET_VECTOR"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> - (set_attr "mode" "<MODE>")])
> + (set_attr "mode" "<MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "@pred_<optab><mode>_reverse_scalar"
> [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr,
> vr")
> @@ -6131,7 +6119,9 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
> "TARGET_VECTOR"
> "vfr<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> - (set_attr "mode" "<MODE>")])
> + (set_attr "mode" "<MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "@pred_<copysign><mode>"
> [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr,
> vr")
> @@ -6279,7 +6269,9 @@ (define_insn "*pred_<madd_msub><mode>"
> (set_attr "vl_op_idx" "5")
> (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
> (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
> - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
> + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "*pred_<macc_msac><mode>"
> [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr,
> ?&vr")
> @@ -6312,7 +6304,9 @@ (define_insn "*pred_<macc_msac><mode>"
> (set_attr "vl_op_idx" "5")
> (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
> (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
> - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
> + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn_and_rewrite "*pred_mul_<optab><mode>"
> [(set (match_operand:VF 0 "register_operand" "=&vr")
> @@ -6343,7 +6337,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
> riscv_vector::prepare_ternary_operands (operands, true);
> }
> [(set_attr "type" "vfmuladd")
> - (set_attr "mode" "<MODE>")])
> + (set_attr "mode" "<MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
>
> (define_expand "@pred_mul_<optab><mode>_scalar"
> [(set (match_operand:VF 0 "register_operand")
> @@ -6400,7 +6396,9 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
> (set_attr "vl_op_idx" "5")
> (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
> (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
> - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
> + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "*pred_<macc_msac><mode>_scalar"
> [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr,
> ?&vr")
> @@ -6434,7 +6432,9 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
> (set_attr "vl_op_idx" "5")
> (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
> (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
> - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
> + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
> [(set (match_operand:VF 0 "register_operand" "=&vr")
> @@ -6465,7 +6465,9 @@ (define_insn_and_rewrite
> "*pred_mul_<optab><mode>_scalar"
> riscv_vector::prepare_ternary_operands (operands, true);
> }
> [(set_attr "type" "vfmuladd")
> - (set_attr "mode" "<MODE>")])
> + (set_attr "mode" "<MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
>
> (define_expand "@pred_mul_neg_<optab><mode>"
> [(set (match_operand:VF 0 "register_operand")
> @@ -6524,7 +6526,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
> (set_attr "vl_op_idx" "5")
> (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
> (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
> - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
> + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "*pred_<nmsac_nmacc><mode>"
> [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr,
> ?&vr")
> @@ -6558,7 +6562,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
> (set_attr "vl_op_idx" "5")
> (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
> (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
> - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
> + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
> [(set (match_operand:VF 0 "register_operand" "=&vr")
> @@ -6590,7 +6596,9 @@ (define_insn_and_rewrite
> "*pred_mul_neg_<optab><mode>"
> riscv_vector::prepare_ternary_operands (operands, true);
> }
> [(set_attr "type" "vfmuladd")
> - (set_attr "mode" "<MODE>")])
> + (set_attr "mode" "<MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
>
> (define_expand "@pred_mul_neg_<optab><mode>_scalar"
> [(set (match_operand:VF 0 "register_operand")
> @@ -6649,7 +6657,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
> (set_attr "vl_op_idx" "5")
> (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
> (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
> - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
> + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
> [(set (match_operand:VF 0 "register_operand" "=vd, ?&vd,
> vr, ?&vr")
> @@ -6684,7 +6694,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
> (set_attr "vl_op_idx" "5")
> (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
> (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
> - (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
> + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
> [(set (match_operand:VF 0 "register_operand" "=&vr")
> @@ -6716,7 +6728,9 @@ (define_insn_and_rewrite
> "*pred_mul_neg_<optab><mode>_scalar"
> riscv_vector::prepare_ternary_operands (operands, true);
> }
> [(set_attr "type" "vfmuladd")
> - (set_attr "mode" "<MODE>")])
> + (set_attr "mode" "<MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
>
> ;;
> -------------------------------------------------------------------------------
> ;; ---- Predicated floating-point unary operations
> @@ -6752,7 +6766,9 @@ (define_insn "@pred_<optab><mode>"
> (set_attr "vl_op_idx" "4")
> (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
> (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
> - (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
> + (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> (define_insn "@pred_<optab><mode>"
> [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr,
> vr")
> @@ -6846,7 +6862,9 @@ (define_insn "@pred_dual_widen_<optab><mode>"
> "TARGET_VECTOR"
> "vfw<insn>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> - (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> + (set_attr "mode" "<V_DOUBLE_TRUNC>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "@pred_dual_widen_<optab><mode>_scalar"
> [(set (match_operand:VWEXTF 0 "register_operand"
> "=&vr, &vr")
> @@ -6871,7 +6889,9 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
> "TARGET_VECTOR"
> "vfw<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> - (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> + (set_attr "mode" "<V_DOUBLE_TRUNC>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "@pred_single_widen_add<mode>"
> [(set (match_operand:VWEXTF 0 "register_operand"
> "=&vr, &vr")
> @@ -6894,7 +6914,9 @@ (define_insn "@pred_single_widen_add<mode>"
> "TARGET_VECTOR"
> "vfwadd.wv\t%0,%3,%4%p1"
> [(set_attr "type" "vfwalu")
> - (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> + (set_attr "mode" "<V_DOUBLE_TRUNC>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "@pred_single_widen_sub<mode>"
> [(set (match_operand:VWEXTF 0 "register_operand"
> "=&vr, &vr")
> @@ -6917,7 +6939,9 @@ (define_insn "@pred_single_widen_sub<mode>"
> "TARGET_VECTOR"
> "vfwsub.wv\t%0,%3,%4%p1"
> [(set_attr "type" "vfwalu")
> - (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> + (set_attr "mode" "<V_DOUBLE_TRUNC>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
> [(set (match_operand:VWEXTF 0 "register_operand"
> "=&vr, &vr")
> @@ -6941,7 +6965,9 @@ (define_insn
> "@pred_single_widen_<plus_minus:optab><mode>_scalar"
> "TARGET_VECTOR"
> "vfw<insn>.wf\t%0,%3,%4%p1"
> [(set_attr "type" "vf<widen_binop_insn_type>")
> - (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> + (set_attr "mode" "<V_DOUBLE_TRUNC>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> ;;
> -------------------------------------------------------------------------------
> ;; ---- Predicated widen floating-point ternary operations
> @@ -6974,7 +7000,9 @@ (define_insn "@pred_widen_mul_<optab><mode>"
> "TARGET_VECTOR"
> "vfw<macc_msac>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> - (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> + (set_attr "mode" "<V_DOUBLE_TRUNC>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "@pred_widen_mul_<optab><mode>_scalar"
> [(set (match_operand:VWEXTF 0 "register_operand"
> "=&vr")
> @@ -7001,7 +7029,9 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
> "TARGET_VECTOR"
> "vfw<macc_msac>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> - (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> + (set_attr "mode" "<V_DOUBLE_TRUNC>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "@pred_widen_mul_neg_<optab><mode>"
> [(set (match_operand:VWEXTF 0 "register_operand"
> "=&vr")
> @@ -7028,7 +7058,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
> "TARGET_VECTOR"
> "vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> - (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> + (set_attr "mode" "<V_DOUBLE_TRUNC>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
> [(set (match_operand:VWEXTF 0 "register_operand"
> "=&vr")
> @@ -7056,7 +7088,9 @@ (define_insn
> "@pred_widen_mul_neg_<optab><mode>_scalar"
> "TARGET_VECTOR"
> "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "vfwmuladd")
> - (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> + (set_attr "mode" "<V_DOUBLE_TRUNC>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> ;;
> -------------------------------------------------------------------------------
> ;; ---- Predicated floating-point comparison operations
> @@ -7366,7 +7400,9 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
> "TARGET_VECTOR"
> "vfcvt.x<v_su>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtftoi")
> - (set_attr "mode" "<MODE>")])
> + (set_attr "mode" "<MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> (define_insn "@pred_<fix_cvt><mode>"
> [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd,
> vr, vr")
> @@ -7406,7 +7442,9 @@ (define_insn "@pred_<float_cvt><mode>"
> "TARGET_VECTOR"
> "vfcvt.f.x<u>.v\t%0,%3%p1"
> [(set_attr "type" "vfcvtitof")
> - (set_attr "mode" "<MODE>")])
> + (set_attr "mode" "<MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> ;;
> -------------------------------------------------------------------------------
> ;; ---- Predicated floating-point widen conversions
> @@ -7434,7 +7472,9 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
> "TARGET_VECTOR"
> "vfwcvt.x<v_su>.f.v\t%0,%3%p1"
> [(set_attr "type" "vfwcvtftoi")
> - (set_attr "mode" "<VNCONVERT>")])
> + (set_attr "mode" "<VNCONVERT>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> (define_insn "@pred_widen_<fix_cvt><mode>"
> [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr,
> &vr")
> @@ -7519,7 +7559,9 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
> "TARGET_VECTOR"
> "vfncvt.x<v_su>.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftoi")
> - (set_attr "mode" "<VNCONVERT>")])
> + (set_attr "mode" "<VNCONVERT>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> (define_insn "@pred_narrow_<fix_cvt><mode>"
> [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd,
> vr, vr, &vr, &vr")
> @@ -7559,7 +7601,9 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
> "TARGET_VECTOR"
> "vfncvt.f.x<u>.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtitof")
> - (set_attr "mode" "<VNCONVERT>")])
> + (set_attr "mode" "<VNCONVERT>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> (define_insn "@pred_trunc<mode>"
> [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd,
> vd, vr, vr, &vr, &vr")
> @@ -7580,7 +7624,9 @@ (define_insn "@pred_trunc<mode>"
> "TARGET_VECTOR"
> "vfncvt.f.f.w\t%0,%3%p1"
> [(set_attr "type" "vfncvtftof")
> - (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> + (set_attr "mode" "<V_DOUBLE_TRUNC>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> (define_insn "@pred_rod_trunc<mode>"
> [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd,
> vd, vr, vr, &vr, &vr")
> @@ -7860,7 +7906,9 @@ (define_insn
> "@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>"
> "TARGET_VECTOR"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> - (set_attr "mode" "<VHF:MODE>")])
> + (set_attr "mode" "<VHF:MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> ;; Float Ordered Reduction Sum for SF
> (define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
> @@ -7886,7 +7934,9 @@ (define_insn
> "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
> "TARGET_VECTOR"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> - (set_attr "mode" "<VSF:MODE>")])
> + (set_attr "mode" "<VSF:MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> ;; Float Ordered Reduction Sum for DF
> (define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
> @@ -7912,7 +7962,9 @@ (define_insn
> "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
> "TARGET_VECTOR"
> "vfred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfred<order>")
> - (set_attr "mode" "<VDF:MODE>")])
> + (set_attr "mode" "<VDF:MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> ;; Float Widen Reduction for HF, aka SF = HF op SF
> (define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
> @@ -7934,7 +7986,9 @@ (define_insn
> "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
> "TARGET_VECTOR"
> "vfwred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfwred<order>")
> - (set_attr "mode" "<VHF:MODE>")])
> + (set_attr "mode" "<VHF:MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> ;; Float Widen Reduction for SF, aka DF = SF * DF
> (define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
> @@ -7956,7 +8010,9 @@ (define_insn
> "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
> "TARGET_VECTOR"
> "vfwred<order>sum.vs\t%0,%3,%4%p1"
> [(set_attr "type" "vfwred<order>")
> - (set_attr "mode" "<VSF:MODE>")])
> + (set_attr "mode" "<VSF:MODE>")
> + (set (attr "frm_mode")
> + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> ;;
> -------------------------------------------------------------------------------
> ;; ---- Predicated permutation operations
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v3] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
2023-08-10 3:13 ` Kito Cheng
@ 2023-08-10 4:37 ` Li, Pan2
0 siblings, 0 replies; 17+ messages in thread
From: Li, Pan2 @ 2023-08-10 4:37 UTC (permalink / raw)
To: Kito Cheng
Cc: GCC Patches, 钟居哲,
Jeff Law, Wang, Yanzhang, Kito Cheng
[-- Attachment #1: Type: text/plain, Size: 31934 bytes --]
Committed with some cleanup in change log, thanks Kito.
Pan
From: Kito Cheng <kito.cheng@sifive.com>
Sent: Thursday, August 10, 2023 11:14 AM
To: Li, Pan2 <pan2.li@intel.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>; 钟居哲 <juzhe.zhong@rivai.ai>; Jeff Law <jeffreyalaw@gmail.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; Kito Cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v3] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
LGTM
<pan2.li@intel.com<mailto:pan2.li@intel.com>> 於 2023年8月10日 週四 11:12 寫道：
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the define insn has frm operands.
This patch would like to refactor frm and eliminate the above
assumptions, as well as unblock the underlying rounding mode intrinsic
API support.
After refactor, the default frm will be none, and the selected insn type
will be dyn. For the floating point which honors the frm, we will
set the frm_mode attr explicitly in define_insn.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
Co-Authored-by: Kito Cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_frm_mode): Remove operand
assumptions.
* config/riscv/riscv-v.cc (get_frm_mode): New function.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn):
* config/riscv/vector.md: Set frm_mode attr explicitly.
gcc/ChangeLog:
* config/riscv/riscv-protos.h
(enum floating_point_rounding_mode): Add NONE, DYN_EXIT and DYN_CALL.
(get_frm_mode): New declaration.
* config/riscv/riscv-v.cc (get_frm_mode): New function to get frm mode.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn): Take care of frm reg.
* config/riscv/riscv.cc (riscv_static_frm_mode_p): Migrate to FRM_XXX.
(riscv_emit_frm_mode_set): Ditto.
(riscv_emit_mode_set): Ditto.
(riscv_frm_adjust_mode_after_call): Ditto.
(riscv_frm_mode_needed): Ditto.
(riscv_frm_mode_after): Ditto.
(riscv_mode_entry): Ditto.
(riscv_mode_exit): Ditto.
* config/riscv/riscv.h (NUM_MODES_FOR_MODE_SWITCHING): Ditto.
* config/riscv/vector.md
(rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none): Removed
(symbol_ref): * config/riscv/vector.md: Set frm_mode attr explicitly.
---
gcc/config/riscv/riscv-protos.h | 4 +
gcc/config/riscv/riscv-v.cc | 29 ++++
gcc/config/riscv/riscv-vector-builtins.cc | 22 ++-
gcc/config/riscv/riscv.cc | 46 +++---
gcc/config/riscv/riscv.h | 2 +-
gcc/config/riscv/vector.md | 172 ++++++++++++++--------
6 files changed, 186 insertions(+), 89 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index ac9c4b02f17..2fbed04ff84 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -349,8 +349,12 @@ enum floating_point_rounding_mode
FRM_DYN = 7, /* Aka 0b111. */
FRM_STATIC_MIN = FRM_RNE,
FRM_STATIC_MAX = FRM_RMM,
+ FRM_DYN_EXIT = 8,
+ FRM_DYN_CALL = 9,
+ FRM_NONE = 10,
};
+enum floating_point_rounding_mode get_frm_mode (rtx);
opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
poly_uint64);
unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 0bea04c1967..c9f0a4a9e7b 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -112,6 +112,7 @@ public:
{
m_has_fp_rounding_mode_p = true;
m_fp_rounding_mode = mode;
+ gcc_assert (mode <= FRM_DYN);
}
void add_output_operand (rtx x, machine_mode mode)
@@ -1590,6 +1591,34 @@ expand_const_vector (rtx target, rtx src)
gcc_unreachable ();
}
+/* Get the frm mode with given CONST_INT rtx, the default mode is
+ FRM_DYN. */
+enum floating_point_rounding_mode
+get_frm_mode (rtx operand)
+{
+ gcc_assert (CONST_INT_P (operand));
+
+ switch (INTVAL (operand))
+ {
+ case FRM_RNE:
+ return FRM_RNE;
+ case FRM_RTZ:
+ return FRM_RTZ;
+ case FRM_RDN:
+ return FRM_RDN;
+ case FRM_RUP:
+ return FRM_RUP;
+ case FRM_RMM:
+ return FRM_RMM;
+ case FRM_DYN:
+ return FRM_DYN;
+ default:
+ gcc_unreachable ();
+ }
+
+ gcc_unreachable ();
+}
+
/* Expand a pre-RA RVV data move from SRC to DEST.
It expands move for RVV fractional vector modes. */
bool
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 528dca7ae85..abab06c00ed 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)
}
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
- add_input_operand (argno);
+ {
+ if (base->has_rounding_mode_operand_p ()
+ && argno == call_expr_nargs (exp) - 2)
+ {
+ /* Since the rounding mode argument position is not consistent with
+ the instruction pattern, we need to skip rounding mode argument
+ here. */
+ continue;
+ }
+ add_input_operand (argno);
+ }
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
- /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
- We add default rounding mode for the intrinsics that didn't model rounding
- mode yet. */
+ if (base->has_rounding_mode_operand_p ())
+ add_input_operand (call_expr_nargs (exp) - 2);
+
+ /* The RVV floating-point only support dynamic rounding mode in the
+ FRM register. */
if (opno != insn_data[icode].n_generator_args)
- add_input_operand (Pmode, const0_rtx);
+ add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
return generate_insn (icode);
}
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index dfb519ab9a8..bb9815a01d7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8054,11 +8054,11 @@ riscv_static_frm_mode_p (int mode)
{
switch (mode)
{
- case FRM_MODE_RDN:
- case FRM_MODE_RUP:
- case FRM_MODE_RTZ:
- case FRM_MODE_RMM:
- case FRM_MODE_RNE:
+ case riscv_vector::FRM_RDN:
+ case riscv_vector::FRM_RUP:
+ case riscv_vector::FRM_RTZ:
+ case riscv_vector::FRM_RMM:
+ case riscv_vector::FRM_RNE:
return true;
default:
return false;
@@ -8074,28 +8074,24 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
{
rtx backup_reg = DYNAMIC_FRM_RTL (cfun);
- if (prev_mode == FRM_MODE_DYN_CALL)
+ if (prev_mode == riscv_vector::FRM_DYN_CALL)
emit_insn (gen_frrmsi (backup_reg)); /* Backup frm when DYN_CALL. */
if (mode != prev_mode)
{
- /* TODO: By design, FRM_MODE_xxx used by mode switch which is
- different from the FRM value like FRM_RTZ defined in
- riscv-protos.h. When mode switching we actually need a conversion
- function to convert the mode of mode switching to the actual
- FRM value like FRM_RTZ. For now, the value between the mode of
- mode swith and the FRM value in riscv-protos.h take the same value,
- and then we leverage this assumption when emit. */
rtx frm = gen_int_mode (mode, SImode);
- if (mode == FRM_MODE_DYN_CALL && prev_mode != FRM_MODE_DYN)
+ if (mode == riscv_vector::FRM_DYN_CALL
+ && prev_mode != riscv_vector::FRM_DYN)
/* No need to emit when prev mode is DYN already. */
emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
- else if (mode == FRM_MODE_DYN_EXIT && STATIC_FRM_P (cfun)
- && prev_mode != FRM_MODE_DYN && prev_mode != FRM_MODE_DYN_CALL)
+ else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun)
+ && prev_mode != riscv_vector::FRM_DYN
+ && prev_mode != riscv_vector::FRM_DYN_CALL)
/* No need to emit when prev mode is DYN or DYN_CALL already. */
emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
- else if (mode == FRM_MODE_DYN && prev_mode != FRM_MODE_DYN_CALL)
+ else if (mode == riscv_vector::FRM_DYN
+ && prev_mode != riscv_vector::FRM_DYN_CALL)
/* Restore frm value from backup when switch to DYN mode. */
emit_insn (gen_fsrmsi_restore (backup_reg));
else if (riscv_static_frm_mode_p (mode))
@@ -8124,7 +8120,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
}
}
-/* Adjust the FRM_MODE_NONE insn after a call to FRM_MODE_DYN for the
+/* Adjust the FRM_NONE insn after a call to FRM_DYN for the
underlying emit. */
static int
@@ -8133,7 +8129,7 @@ riscv_frm_adjust_mode_after_call (rtx_insn *cur_insn, int mode)
rtx_insn *insn = prev_nonnote_nondebug_insn_bb (cur_insn);
if (insn && CALL_P (insn))
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
return mode;
}
@@ -8184,12 +8180,12 @@ riscv_frm_mode_needed (rtx_insn *cur_insn, int code)
if (!insn)
riscv_frm_emit_after_bb_end (cur_insn);
- return FRM_MODE_DYN_CALL;
+ return riscv_vector::FRM_DYN_CALL;
}
- int mode = code >= 0 ? get_attr_frm_mode (cur_insn) : FRM_MODE_NONE;
+ int mode = code >= 0 ? get_attr_frm_mode (cur_insn) : riscv_vector::FRM_NONE;
- if (mode == FRM_MODE_NONE)
+ if (mode == riscv_vector::FRM_NONE)
/* After meet a call, we need to backup the frm because it may be
updated during the call. Here, for each insn, we will check if
the previous insn is a call or not. When previous insn is call,
@@ -8297,7 +8293,7 @@ riscv_frm_mode_after (rtx_insn *insn, int mode)
return mode;
if (frm_unknown_dynamic_p (insn))
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
if (recog_memoized (insn) < 0)
return mode;
@@ -8339,7 +8335,7 @@ riscv_mode_entry (int entity)
/* According to RVV 1.0 spec, all vector floating-point operations use
the dynamic rounding mode in the frm register. Likewise in other
similar places. */
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
}
default:
gcc_unreachable ();
@@ -8357,7 +8353,7 @@ riscv_mode_exit (int entity)
case RISCV_VXRM:
return VXRM_MODE_NONE;
case RISCV_FRM:
- return FRM_MODE_DYN_EXIT;
+ return riscv_vector::FRM_DYN_EXIT;
default:
gcc_unreachable ();
}
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 643e7ea7330..746101ea933 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1120,6 +1120,6 @@ extern void riscv_remove_unneeded_save_restore_calls (void);
/* Mode switching (Lazy code motion) for RVV rounding mode instructions. */
#define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
-#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, FRM_MODE_NONE}
+#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
#endif /* ! GCC_RISCV_H */
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 65b5fe456ed..cf37b472930 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -865,28 +865,10 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
(const_string "none")))
;; Defines rounding mode of an floating-point operation.
-(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
+(define_attr "frm_mode" ""
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
- (cond
- [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
- (const_string "rne")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ")
- (const_string "rtz")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN")
- (const_string "rdn")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP")
- (const_string "rup")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM")
- (const_string "rmm")
-
- (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN")
- (const_string "dyn")]
- (const_string "none"))]
- (const_string "none")))
+ (symbol_ref "riscv_vector::FRM_DYN")]
+ (symbol_ref "riscv_vector::FRM_NONE")))
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
@@ -6021,7 +6003,9 @@ (define_insn "@pred_<optab><mode>"
"TARGET_VECTOR"
"vf<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6064,7 +6048,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6108,7 +6094,9 @@ (define_insn "@pred_<optab><mode>_scalar"
"TARGET_VECTOR"
"vf<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_reverse_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6131,7 +6119,9 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
"TARGET_VECTOR"
"vfr<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "<float_insn_type>")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<copysign><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6279,7 +6269,9 @@ (define_insn "*pred_<madd_msub><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6312,7 +6304,9 @@ (define_insn "*pred_<macc_msac><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr")
@@ -6343,7 +6337,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
riscv_vector::prepare_ternary_operands (operands, true);
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6400,7 +6396,9 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6434,7 +6432,9 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr")
@@ -6465,7 +6465,9 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
riscv_vector::prepare_ternary_operands (operands, true);
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand")
@@ -6524,7 +6526,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6558,7 +6562,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr")
@@ -6590,7 +6596,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
riscv_vector::prepare_ternary_operands (operands, true);
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6649,7 +6657,9 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6684,7 +6694,9 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(set_attr "vl_op_idx" "5")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr")
@@ -6716,7 +6728,9 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
riscv_vector::prepare_ternary_operands (operands, true);
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point unary operations
@@ -6752,7 +6766,9 @@ (define_insn "@pred_<optab><mode>"
(set_attr "vl_op_idx" "4")
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
+ (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6846,7 +6862,9 @@ (define_insn "@pred_dual_widen_<optab><mode>"
"TARGET_VECTOR"
"vfw<insn>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_dual_widen_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -6871,7 +6889,9 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_add<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -6894,7 +6914,9 @@ (define_insn "@pred_single_widen_add<mode>"
"TARGET_VECTOR"
"vfwadd.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_sub<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -6917,7 +6939,9 @@ (define_insn "@pred_single_widen_sub<mode>"
"TARGET_VECTOR"
"vfwsub.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -6941,7 +6965,9 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated widen floating-point ternary operations
@@ -6974,7 +7000,9 @@ (define_insn "@pred_widen_mul_<optab><mode>"
"TARGET_VECTOR"
"vfw<macc_msac>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7001,7 +7029,9 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7028,7 +7058,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7056,7 +7088,9 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point comparison operations
@@ -7366,7 +7400,9 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfcvtftoi")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<fix_cvt><mode>"
[(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
@@ -7406,7 +7442,9 @@ (define_insn "@pred_<float_cvt><mode>"
"TARGET_VECTOR"
"vfcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfcvtitof")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point widen conversions
@@ -7434,7 +7472,9 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_widen_<fix_cvt><mode>"
[(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
@@ -7519,7 +7559,9 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
"TARGET_VECTOR"
"vfncvt.x<v_su>.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_narrow_<fix_cvt><mode>"
[(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7559,7 +7601,9 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
"TARGET_VECTOR"
"vfncvt.f.x<u>.w\t%0,%3%p1"
[(set_attr "type" "vfncvtitof")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7580,7 +7624,9 @@ (define_insn "@pred_trunc<mode>"
"TARGET_VECTOR"
"vfncvt.f.f.w\t%0,%3%p1"
[(set_attr "type" "vfncvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7860,7 +7906,9 @@ (define_insn "@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for SF
(define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
@@ -7886,7 +7934,9 @@ (define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for DF
(define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
@@ -7912,7 +7962,9 @@ (define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfred<order>")
- (set_attr "mode" "<VDF:MODE>")])
+ (set_attr "mode" "<VDF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for HF, aka SF = HF op SF
(define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
@@ -7934,7 +7986,9 @@ (define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VHF:MODE>")])
+ (set_attr "mode" "<VHF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for SF, aka DF = SF * DF
(define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
@@ -7956,7 +8010,9 @@ (define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
"TARGET_VECTOR"
"vfwred<order>sum.vs\t%0,%3,%4%p1"
[(set_attr "type" "vfwred<order>")
- (set_attr "mode" "<VSF:MODE>")])
+ (set_attr "mode" "<VSF:MODE>")
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated permutation operations
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2023-08-10 4:37 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-08-06 3:36 [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic pan2.li
2023-08-07 0:45 ` juzhe.zhong
2023-08-07 1:22 ` Li, Pan2
2023-08-07 1:30 ` juzhe.zhong
2023-08-07 1:34 ` Li, Pan2
2023-08-07 3:26 ` Kito Cheng
2023-08-07 3:45 ` Li, Pan2
2023-08-07 6:35 ` Kito Cheng
2023-08-07 13:13 ` Li, Pan2
2023-08-08 5:25 ` [PATCH v2] " pan2.li
2023-08-10 2:11 ` Kito Cheng
2023-08-10 2:16 ` Li, Pan2
2023-08-10 2:20 ` Kito Cheng
2023-08-10 3:13 ` Li, Pan2
2023-08-10 3:12 ` [PATCH v3] " pan2.li
2023-08-10 3:13 ` Kito Cheng
2023-08-10 4:37 ` Li, Pan2
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