From: Richard Sandiford <richard.sandiford@arm.com>
To: jlaw@ventanamicro.com, vmakarov@redhat.com, gcc-patches@gcc.gnu.org
Cc: Richard Sandiford <richard.sandiford@arm.com>
Subject: [PATCH 3/5] lra: Handle register filters
Date: Sun, 12 Nov 2023 14:52:27 +0000 [thread overview]
Message-ID: <20231112145229.2924713-4-richard.sandiford@arm.com> (raw)
In-Reply-To: <20231112145229.2924713-1-richard.sandiford@arm.com>
This patch makes LRA apply register filters. This plus the recog
change is enough for correct code generation, but a follow-on IRA
patch improves the allocation.
All the new code should be optimised away on targets that don't
use register filters. That's because get_register_filter just
wraps "return nullptr" on those targets.
gcc/
* lra-constraints.cc (process_alt_operands): Check register filters.
---
gcc/lra-constraints.cc | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index 0607c8be7cb..9b6a2af5b75 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -2149,6 +2149,7 @@ process_alt_operands (int only_alternative)
int reload_nregs, reload_sum;
bool costly_p;
enum reg_class cl;
+ const HARD_REG_SET *cl_filter;
/* Calculate some data common for all alternatives to speed up the
function. */
@@ -2514,6 +2515,7 @@ process_alt_operands (int only_alternative)
|| spilled_pseudo_p (op))
win = true;
cl = GENERAL_REGS;
+ cl_filter = nullptr;
goto reg;
default:
@@ -2523,7 +2525,10 @@ process_alt_operands (int only_alternative)
case CT_REGISTER:
cl = reg_class_for_constraint (cn);
if (cl != NO_REGS)
- goto reg;
+ {
+ cl_filter = get_register_filter (cn);
+ goto reg;
+ }
break;
case CT_CONST_INT:
@@ -2567,6 +2572,7 @@ process_alt_operands (int only_alternative)
win = true;
cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
ADDRESS, SCRATCH);
+ cl_filter = nullptr;
badop = false;
goto reg;
@@ -2600,6 +2606,8 @@ process_alt_operands (int only_alternative)
this_alternative_exclude_start_hard_regs
|= ira_exclude_class_mode_regs[cl][mode];
this_alternative_set |= reg_class_contents[cl];
+ if (cl_filter)
+ this_alternative_exclude_start_hard_regs |= ~*cl_filter;
if (costly_p)
{
this_costly_alternative
@@ -2613,6 +2621,9 @@ process_alt_operands (int only_alternative)
if (hard_regno[nop] >= 0
&& in_hard_reg_set_p (this_alternative_set,
mode, hard_regno[nop])
+ && (!cl_filter
+ || TEST_HARD_REG_BIT (*cl_filter,
+ hard_regno[nop]))
&& ((REG_ATTRS (op) && (decl = REG_EXPR (op)) != NULL
&& VAR_P (decl) && DECL_HARD_REGISTER (decl))
|| !(TEST_HARD_REG_BIT
--
2.25.1
next prev parent reply other threads:[~2023-11-12 14:53 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-12 14:52 [PATCH 0/5] Add support for operand-specific alignment requirements Richard Sandiford
2023-11-12 14:52 ` [PATCH 1/5] Add register filter operand to define_register_constraint Richard Sandiford
2023-11-19 21:49 ` Jeff Law
2023-11-12 14:52 ` [PATCH 2/5] recog: Handle register filters Richard Sandiford
2023-11-19 21:51 ` Jeff Law
2023-11-12 14:52 ` Richard Sandiford [this message]
2023-11-12 14:52 ` [PATCH 4/5] ira: " Richard Sandiford
2023-11-12 14:52 ` [PATCH 5/5] Add an aligned_register_operand predicate Richard Sandiford
2023-11-19 21:52 ` Jeff Law
2023-11-14 0:01 ` [PATCH 0/5] Add support for operand-specific alignment requirements Vladimir Makarov
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