* [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
@ 2024-02-07 9:27 pan2.li
2024-02-07 10:21 ` juzhe.zhong
0 siblings, 1 reply; 5+ messages in thread
From: pan2.li @ 2024-02-07 9:27 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
There is another corn case when similar as below example:
void test (void)
{
__riscv_vaadd ();
}
We report error when overloaded function with empty args. For example:
test.c: In function 'foo':
test.c:8:3: error: no matching function call to '__riscv_vaadd' with empty args
8 | __riscv_vaadd ();
| ^~~~~~~~~~~~~~~~~~~~
Unfortunately, it will meet another ICE similar to below after above
message. The underlying build function checker will have zero args
and break some assumption of the function checker. For example, the
count of args is not less than 2.
ice.c: In function ‘foo’:
ice.c:8:3: internal compiler error: in require_immediate, at
config/riscv/riscv-vector-builtins.cc:4252
8 | __riscv_vaadd ();
| ^~~~~~~~~~~~~
0x20b36ac riscv_vector::function_checker::require_immediate(unsigned
int, long, long) const
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4252
0x20b890c riscv_vector::alu_def::check(riscv_vector::function_checker&) const
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins-shapes.cc:387
0x20b38d7 riscv_vector::function_checker::check()
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4315
0x20b4876 riscv_vector::check_builtin_call(unsigned int, vec<unsigned int, va_heap, vl_ptr>,
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4605
0x2069393 riscv_check_builtin_call
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-c.cc:227
Below test are passed for this patch.
* The riscv regression tests.
PR target/113766
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
sure the c.arg_num is >= 2 before checking.
(struct build_frm_base): Ditto.
(struct narrow_alu_def): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr113766-1.c: Add new cases.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../riscv/riscv-vector-builtins-shapes.cc | 17 +++++++++++++----
.../gcc.target/riscv/rvv/base/pr113766-1.c | 16 ++++++++++++++++
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 8e90b17a94b..c5ffcc1f2c4 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -383,7 +383,10 @@ struct alu_def : public build_base
/* Check whether rounding mode argument is a valid immediate. */
if (c.base->has_rounding_mode_operand_p ())
{
- if (!c.any_type_float_p ())
+ /* Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (!c.any_type_float_p () && c.arg_num () >= 2)
return c.require_immediate (c.arg_num () - 2, VXRM_RNU, VXRM_ROD);
/* TODO: We will support floating-point intrinsic modeling
rounding mode in the future. */
@@ -411,8 +414,11 @@ struct build_frm_base : public build_base
{
gcc_assert (c.any_type_float_p ());
- /* Check whether rounding mode argument is a valid immediate. */
- if (c.base->has_rounding_mode_operand_p ())
+ /* Check whether rounding mode argument is a valid immediate.
+ Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (c.base->has_rounding_mode_operand_p () && c.arg_num () >= 2)
{
unsigned int frm_num = c.arg_num () - 2;
@@ -679,7 +685,10 @@ struct narrow_alu_def : public build_base
/* Check whether rounding mode argument is a valid immediate. */
if (c.base->has_rounding_mode_operand_p ())
{
- if (!c.any_type_float_p ())
+ /* Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (!c.any_type_float_p () && c.arg_num () >= 2)
return c.require_immediate (c.arg_num () - 2, VXRM_RNU, VXRM_ROD);
/* TODO: We will support floating-point intrinsic modeling
rounding mode in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
index bd4943b0b7e..fd674a8895c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
@@ -82,4 +82,20 @@ test ()
__riscv_vfredosum (); /* { dg-error {no matching function call to '__riscv_vfredosum' with empty args} } */
__riscv_vfredosum_tu (); /* { dg-error {no matching function call to '__riscv_vfredosum_tu' with empty args} } */
+
+ __riscv_vaadd (); /* { dg-error {no matching function call to '__riscv_vaadd' with empty args} } */
+
+ __riscv_vaaddu (); /* { dg-error {no matching function call to '__riscv_vaaddu' with empty args} } */
+
+ __riscv_vadc (); /* { dg-error {no matching function call to '__riscv_vadc' with empty args} } */
+
+ __riscv_vnmsac (); /* { dg-error {no matching function call to '__riscv_vnmsac' with empty args} } */
+
+ __riscv_vnsrl (); /* { dg-error {no matching function call to '__riscv_vnsrl' with empty args} } */
+
+ __riscv_vfnmadd (); /* { dg-error {no matching function call to '__riscv_vfnmadd' with empty args} } */
+
+ __riscv_vfwsub_vv (); /* { dg-error {no matching function call to '__riscv_vfwsub_vv' with empty args} } */
+
+ __riscv_vfwredosum (); /* { dg-error {no matching function call to '__riscv_vfwredosum' with empty args} } */
}
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
2024-02-07 9:27 [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker pan2.li
@ 2024-02-07 10:21 ` juzhe.zhong
2024-02-08 1:41 ` Li, Pan2
0 siblings, 1 reply; 5+ messages in thread
From: juzhe.zhong @ 2024-02-07 10:21 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: pan2.li, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 6170 bytes --]
Why is it 2 not 1 or other value ?
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-02-07 17:27
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
From: Pan Li <pan2.li@intel.com>
There is another corn case when similar as below example:
void test (void)
{
__riscv_vaadd ();
}
We report error when overloaded function with empty args. For example:
test.c: In function 'foo':
test.c:8:3: error: no matching function call to '__riscv_vaadd' with empty args
8 | __riscv_vaadd ();
| ^~~~~~~~~~~~~~~~~~~~
Unfortunately, it will meet another ICE similar to below after above
message. The underlying build function checker will have zero args
and break some assumption of the function checker. For example, the
count of args is not less than 2.
ice.c: In function ‘foo’:
ice.c:8:3: internal compiler error: in require_immediate, at
config/riscv/riscv-vector-builtins.cc:4252
8 | __riscv_vaadd ();
| ^~~~~~~~~~~~~
0x20b36ac riscv_vector::function_checker::require_immediate(unsigned
int, long, long) const
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4252
0x20b890c riscv_vector::alu_def::check(riscv_vector::function_checker&) const
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins-shapes.cc:387
0x20b38d7 riscv_vector::function_checker::check()
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4315
0x20b4876 riscv_vector::check_builtin_call(unsigned int, vec<unsigned int, va_heap, vl_ptr>,
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4605
0x2069393 riscv_check_builtin_call
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-c.cc:227
Below test are passed for this patch.
* The riscv regression tests.
PR target/113766
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
sure the c.arg_num is >= 2 before checking.
(struct build_frm_base): Ditto.
(struct narrow_alu_def): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr113766-1.c: Add new cases.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../riscv/riscv-vector-builtins-shapes.cc | 17 +++++++++++++----
.../gcc.target/riscv/rvv/base/pr113766-1.c | 16 ++++++++++++++++
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 8e90b17a94b..c5ffcc1f2c4 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -383,7 +383,10 @@ struct alu_def : public build_base
/* Check whether rounding mode argument is a valid immediate. */
if (c.base->has_rounding_mode_operand_p ())
{
- if (!c.any_type_float_p ())
+ /* Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (!c.any_type_float_p () && c.arg_num () >= 2)
return c.require_immediate (c.arg_num () - 2, VXRM_RNU, VXRM_ROD);
/* TODO: We will support floating-point intrinsic modeling
rounding mode in the future. */
@@ -411,8 +414,11 @@ struct build_frm_base : public build_base
{
gcc_assert (c.any_type_float_p ());
- /* Check whether rounding mode argument is a valid immediate. */
- if (c.base->has_rounding_mode_operand_p ())
+ /* Check whether rounding mode argument is a valid immediate.
+ Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (c.base->has_rounding_mode_operand_p () && c.arg_num () >= 2)
{
unsigned int frm_num = c.arg_num () - 2;
@@ -679,7 +685,10 @@ struct narrow_alu_def : public build_base
/* Check whether rounding mode argument is a valid immediate. */
if (c.base->has_rounding_mode_operand_p ())
{
- if (!c.any_type_float_p ())
+ /* Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (!c.any_type_float_p () && c.arg_num () >= 2)
return c.require_immediate (c.arg_num () - 2, VXRM_RNU, VXRM_ROD);
/* TODO: We will support floating-point intrinsic modeling
rounding mode in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
index bd4943b0b7e..fd674a8895c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
@@ -82,4 +82,20 @@ test ()
__riscv_vfredosum (); /* { dg-error {no matching function call to '__riscv_vfredosum' with empty args} } */
__riscv_vfredosum_tu (); /* { dg-error {no matching function call to '__riscv_vfredosum_tu' with empty args} } */
+
+ __riscv_vaadd (); /* { dg-error {no matching function call to '__riscv_vaadd' with empty args} } */
+
+ __riscv_vaaddu (); /* { dg-error {no matching function call to '__riscv_vaaddu' with empty args} } */
+
+ __riscv_vadc (); /* { dg-error {no matching function call to '__riscv_vadc' with empty args} } */
+
+ __riscv_vnmsac (); /* { dg-error {no matching function call to '__riscv_vnmsac' with empty args} } */
+
+ __riscv_vnsrl (); /* { dg-error {no matching function call to '__riscv_vnsrl' with empty args} } */
+
+ __riscv_vfnmadd (); /* { dg-error {no matching function call to '__riscv_vfnmadd' with empty args} } */
+
+ __riscv_vfwsub_vv (); /* { dg-error {no matching function call to '__riscv_vfwsub_vv' with empty args} } */
+
+ __riscv_vfwredosum (); /* { dg-error {no matching function call to '__riscv_vfwredosum' with empty args} } */
}
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
2024-02-07 10:21 ` juzhe.zhong
@ 2024-02-08 1:41 ` Li, Pan2
2024-02-08 6:43 ` juzhe.zhong
0 siblings, 1 reply; 5+ messages in thread
From: Li, Pan2 @ 2024-02-08 1:41 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Wang, Yanzhang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 7146 bytes --]
I think it relates to the location of frm args. For example, we use below to get the operand index. And then pass to function_checker.
unsigned int frm_num = c.arg_num () - 2;
Unfortunately, the function checker treat argno as unsigned, thus we need to ensure that c.arg_num () is not less than 2
for avoiding overflow.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Wednesday, February 7, 2024 6:21 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
Why is it 2 not 1 or other value ?
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2024-02-07 17:27
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
There is another corn case when similar as below example:
void test (void)
{
__riscv_vaadd ();
}
We report error when overloaded function with empty args. For example:
test.c: In function 'foo':
test.c:8:3: error: no matching function call to '__riscv_vaadd' with empty args
8 | __riscv_vaadd ();
| ^~~~~~~~~~~~~~~~~~~~
Unfortunately, it will meet another ICE similar to below after above
message. The underlying build function checker will have zero args
and break some assumption of the function checker. For example, the
count of args is not less than 2.
ice.c: In function 'foo':
ice.c:8:3: internal compiler error: in require_immediate, at
config/riscv/riscv-vector-builtins.cc:4252
8 | __riscv_vaadd ();
| ^~~~~~~~~~~~~
0x20b36ac riscv_vector::function_checker::require_immediate(unsigned
int, long, long) const
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4252
0x20b890c riscv_vector::alu_def::check(riscv_vector::function_checker&) const
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins-shapes.cc:387
0x20b38d7 riscv_vector::function_checker::check()
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4315
0x20b4876 riscv_vector::check_builtin_call(unsigned int, vec<unsigned int, va_heap, vl_ptr>,
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4605
0x2069393 riscv_check_builtin_call
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-c.cc:227
Below test are passed for this patch.
* The riscv regression tests.
PR target/113766
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
sure the c.arg_num is >= 2 before checking.
(struct build_frm_base): Ditto.
(struct narrow_alu_def): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr113766-1.c: Add new cases.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
---
.../riscv/riscv-vector-builtins-shapes.cc | 17 +++++++++++++----
.../gcc.target/riscv/rvv/base/pr113766-1.c | 16 ++++++++++++++++
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 8e90b17a94b..c5ffcc1f2c4 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -383,7 +383,10 @@ struct alu_def : public build_base
/* Check whether rounding mode argument is a valid immediate. */
if (c.base->has_rounding_mode_operand_p ())
{
- if (!c.any_type_float_p ())
+ /* Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (!c.any_type_float_p () && c.arg_num () >= 2)
return c.require_immediate (c.arg_num () - 2, VXRM_RNU, VXRM_ROD);
/* TODO: We will support floating-point intrinsic modeling
rounding mode in the future. */
@@ -411,8 +414,11 @@ struct build_frm_base : public build_base
{
gcc_assert (c.any_type_float_p ());
- /* Check whether rounding mode argument is a valid immediate. */
- if (c.base->has_rounding_mode_operand_p ())
+ /* Check whether rounding mode argument is a valid immediate.
+ Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (c.base->has_rounding_mode_operand_p () && c.arg_num () >= 2)
{
unsigned int frm_num = c.arg_num () - 2;
@@ -679,7 +685,10 @@ struct narrow_alu_def : public build_base
/* Check whether rounding mode argument is a valid immediate. */
if (c.base->has_rounding_mode_operand_p ())
{
- if (!c.any_type_float_p ())
+ /* Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (!c.any_type_float_p () && c.arg_num () >= 2)
return c.require_immediate (c.arg_num () - 2, VXRM_RNU, VXRM_ROD);
/* TODO: We will support floating-point intrinsic modeling
rounding mode in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
index bd4943b0b7e..fd674a8895c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
@@ -82,4 +82,20 @@ test ()
__riscv_vfredosum (); /* { dg-error {no matching function call to '__riscv_vfredosum' with empty args} } */
__riscv_vfredosum_tu (); /* { dg-error {no matching function call to '__riscv_vfredosum_tu' with empty args} } */
+
+ __riscv_vaadd (); /* { dg-error {no matching function call to '__riscv_vaadd' with empty args} } */
+
+ __riscv_vaaddu (); /* { dg-error {no matching function call to '__riscv_vaaddu' with empty args} } */
+
+ __riscv_vadc (); /* { dg-error {no matching function call to '__riscv_vadc' with empty args} } */
+
+ __riscv_vnmsac (); /* { dg-error {no matching function call to '__riscv_vnmsac' with empty args} } */
+
+ __riscv_vnsrl (); /* { dg-error {no matching function call to '__riscv_vnsrl' with empty args} } */
+
+ __riscv_vfnmadd (); /* { dg-error {no matching function call to '__riscv_vfnmadd' with empty args} } */
+
+ __riscv_vfwsub_vv (); /* { dg-error {no matching function call to '__riscv_vfwsub_vv' with empty args} } */
+
+ __riscv_vfwredosum (); /* { dg-error {no matching function call to '__riscv_vfwredosum' with empty args} } */
}
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: RE: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
2024-02-08 1:41 ` Li, Pan2
@ 2024-02-08 6:43 ` juzhe.zhong
2024-02-08 6:52 ` Li, Pan2
0 siblings, 1 reply; 5+ messages in thread
From: juzhe.zhong @ 2024-02-08 6:43 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 7133 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: Li, Pan2
Date: 2024-02-08 09:41
To: juzhe.zhong@rivai.ai; gcc-patches
CC: Wang, Yanzhang; kito.cheng
Subject: RE: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
I think it relates to the location of frm args. For example, we use below to get the operand index. And then pass to function_checker.
unsigned int frm_num = c.arg_num () - 2;
Unfortunately, the function checker treat argno as unsigned, thus we need to ensure that c.arg_num () is not less than 2
for avoiding overflow.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Wednesday, February 7, 2024 6:21 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
Why is it 2 not 1 or other value ?
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-02-07 17:27
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
From: Pan Li <pan2.li@intel.com>
There is another corn case when similar as below example:
void test (void)
{
__riscv_vaadd ();
}
We report error when overloaded function with empty args. For example:
test.c: In function 'foo':
test.c:8:3: error: no matching function call to '__riscv_vaadd' with empty args
8 | __riscv_vaadd ();
| ^~~~~~~~~~~~~~~~~~~~
Unfortunately, it will meet another ICE similar to below after above
message. The underlying build function checker will have zero args
and break some assumption of the function checker. For example, the
count of args is not less than 2.
ice.c: In function ‘foo’:
ice.c:8:3: internal compiler error: in require_immediate, at
config/riscv/riscv-vector-builtins.cc:4252
8 | __riscv_vaadd ();
| ^~~~~~~~~~~~~
0x20b36ac riscv_vector::function_checker::require_immediate(unsigned
int, long, long) const
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4252
0x20b890c riscv_vector::alu_def::check(riscv_vector::function_checker&) const
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins-shapes.cc:387
0x20b38d7 riscv_vector::function_checker::check()
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4315
0x20b4876 riscv_vector::check_builtin_call(unsigned int, vec<unsigned int, va_heap, vl_ptr>,
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4605
0x2069393 riscv_check_builtin_call
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-c.cc:227
Below test are passed for this patch.
* The riscv regression tests.
PR target/113766
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
sure the c.arg_num is >= 2 before checking.
(struct build_frm_base): Ditto.
(struct narrow_alu_def): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr113766-1.c: Add new cases.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../riscv/riscv-vector-builtins-shapes.cc | 17 +++++++++++++----
.../gcc.target/riscv/rvv/base/pr113766-1.c | 16 ++++++++++++++++
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 8e90b17a94b..c5ffcc1f2c4 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -383,7 +383,10 @@ struct alu_def : public build_base
/* Check whether rounding mode argument is a valid immediate. */
if (c.base->has_rounding_mode_operand_p ())
{
- if (!c.any_type_float_p ())
+ /* Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (!c.any_type_float_p () && c.arg_num () >= 2)
return c.require_immediate (c.arg_num () - 2, VXRM_RNU, VXRM_ROD);
/* TODO: We will support floating-point intrinsic modeling
rounding mode in the future. */
@@ -411,8 +414,11 @@ struct build_frm_base : public build_base
{
gcc_assert (c.any_type_float_p ());
- /* Check whether rounding mode argument is a valid immediate. */
- if (c.base->has_rounding_mode_operand_p ())
+ /* Check whether rounding mode argument is a valid immediate.
+ Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (c.base->has_rounding_mode_operand_p () && c.arg_num () >= 2)
{
unsigned int frm_num = c.arg_num () - 2;
@@ -679,7 +685,10 @@ struct narrow_alu_def : public build_base
/* Check whether rounding mode argument is a valid immediate. */
if (c.base->has_rounding_mode_operand_p ())
{
- if (!c.any_type_float_p ())
+ /* Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (!c.any_type_float_p () && c.arg_num () >= 2)
return c.require_immediate (c.arg_num () - 2, VXRM_RNU, VXRM_ROD);
/* TODO: We will support floating-point intrinsic modeling
rounding mode in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
index bd4943b0b7e..fd674a8895c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
@@ -82,4 +82,20 @@ test ()
__riscv_vfredosum (); /* { dg-error {no matching function call to '__riscv_vfredosum' with empty args} } */
__riscv_vfredosum_tu (); /* { dg-error {no matching function call to '__riscv_vfredosum_tu' with empty args} } */
+
+ __riscv_vaadd (); /* { dg-error {no matching function call to '__riscv_vaadd' with empty args} } */
+
+ __riscv_vaaddu (); /* { dg-error {no matching function call to '__riscv_vaaddu' with empty args} } */
+
+ __riscv_vadc (); /* { dg-error {no matching function call to '__riscv_vadc' with empty args} } */
+
+ __riscv_vnmsac (); /* { dg-error {no matching function call to '__riscv_vnmsac' with empty args} } */
+
+ __riscv_vnsrl (); /* { dg-error {no matching function call to '__riscv_vnsrl' with empty args} } */
+
+ __riscv_vfnmadd (); /* { dg-error {no matching function call to '__riscv_vfnmadd' with empty args} } */
+
+ __riscv_vfwsub_vv (); /* { dg-error {no matching function call to '__riscv_vfwsub_vv' with empty args} } */
+
+ __riscv_vfwredosum (); /* { dg-error {no matching function call to '__riscv_vfwredosum' with empty args} } */
}
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: RE: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
2024-02-08 6:43 ` juzhe.zhong
@ 2024-02-08 6:52 ` Li, Pan2
0 siblings, 0 replies; 5+ messages in thread
From: Li, Pan2 @ 2024-02-08 6:52 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Wang, Yanzhang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 8181 bytes --]
Committed, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Thursday, February 8, 2024 2:43 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: RE: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
LGTM
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: Li, Pan2<mailto:pan2.li@intel.com>
Date: 2024-02-08 09:41
To: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>; gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: Wang, Yanzhang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: RE: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
I think it relates to the location of frm args. For example, we use below to get the operand index. And then pass to function_checker.
unsigned int frm_num = c.arg_num () - 2;
Unfortunately, the function checker treat argno as unsigned, thus we need to ensure that c.arg_num () is not less than 2
for avoiding overflow.
Pan
From: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai> <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Sent: Wednesday, February 7, 2024 6:21 PM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>; kito.cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>
Subject: Re: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
Why is it 2 not 1 or other value ?
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2024-02-07 17:27
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
There is another corn case when similar as below example:
void test (void)
{
__riscv_vaadd ();
}
We report error when overloaded function with empty args. For example:
test.c: In function 'foo':
test.c:8:3: error: no matching function call to '__riscv_vaadd' with empty args
8 | __riscv_vaadd ();
| ^~~~~~~~~~~~~~~~~~~~
Unfortunately, it will meet another ICE similar to below after above
message. The underlying build function checker will have zero args
and break some assumption of the function checker. For example, the
count of args is not less than 2.
ice.c: In function ‘foo’:
ice.c:8:3: internal compiler error: in require_immediate, at
config/riscv/riscv-vector-builtins.cc:4252
8 | __riscv_vaadd ();
| ^~~~~~~~~~~~~
0x20b36ac riscv_vector::function_checker::require_immediate(unsigned
int, long, long) const
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4252
0x20b890c riscv_vector::alu_def::check(riscv_vector::function_checker&) const
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins-shapes.cc:387
0x20b38d7 riscv_vector::function_checker::check()
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4315
0x20b4876 riscv_vector::check_builtin_call(unsigned int, vec<unsigned int, va_heap, vl_ptr>,
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-vector-builtins.cc:4605
0x2069393 riscv_check_builtin_call
.../__RISC-V_BUILD__/../gcc/config/riscv/riscv-c.cc:227
Below test are passed for this patch.
* The riscv regression tests.
PR target/113766
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
sure the c.arg_num is >= 2 before checking.
(struct build_frm_base): Ditto.
(struct narrow_alu_def): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr113766-1.c: Add new cases.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
---
.../riscv/riscv-vector-builtins-shapes.cc | 17 +++++++++++++----
.../gcc.target/riscv/rvv/base/pr113766-1.c | 16 ++++++++++++++++
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 8e90b17a94b..c5ffcc1f2c4 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -383,7 +383,10 @@ struct alu_def : public build_base
/* Check whether rounding mode argument is a valid immediate. */
if (c.base->has_rounding_mode_operand_p ())
{
- if (!c.any_type_float_p ())
+ /* Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (!c.any_type_float_p () && c.arg_num () >= 2)
return c.require_immediate (c.arg_num () - 2, VXRM_RNU, VXRM_ROD);
/* TODO: We will support floating-point intrinsic modeling
rounding mode in the future. */
@@ -411,8 +414,11 @@ struct build_frm_base : public build_base
{
gcc_assert (c.any_type_float_p ());
- /* Check whether rounding mode argument is a valid immediate. */
- if (c.base->has_rounding_mode_operand_p ())
+ /* Check whether rounding mode argument is a valid immediate.
+ Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (c.base->has_rounding_mode_operand_p () && c.arg_num () >= 2)
{
unsigned int frm_num = c.arg_num () - 2;
@@ -679,7 +685,10 @@ struct narrow_alu_def : public build_base
/* Check whether rounding mode argument is a valid immediate. */
if (c.base->has_rounding_mode_operand_p ())
{
- if (!c.any_type_float_p ())
+ /* Some invalid overload intrinsic like below will have zero for
+ c.arg_num (). Thus, make sure arg_num is big enough here.
+ __riscv_vaadd () will make c.arg_num () == 0. */
+ if (!c.any_type_float_p () && c.arg_num () >= 2)
return c.require_immediate (c.arg_num () - 2, VXRM_RNU, VXRM_ROD);
/* TODO: We will support floating-point intrinsic modeling
rounding mode in the future. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
index bd4943b0b7e..fd674a8895c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113766-1.c
@@ -82,4 +82,20 @@ test ()
__riscv_vfredosum (); /* { dg-error {no matching function call to '__riscv_vfredosum' with empty args} } */
__riscv_vfredosum_tu (); /* { dg-error {no matching function call to '__riscv_vfredosum_tu' with empty args} } */
+
+ __riscv_vaadd (); /* { dg-error {no matching function call to '__riscv_vaadd' with empty args} } */
+
+ __riscv_vaaddu (); /* { dg-error {no matching function call to '__riscv_vaaddu' with empty args} } */
+
+ __riscv_vadc (); /* { dg-error {no matching function call to '__riscv_vadc' with empty args} } */
+
+ __riscv_vnmsac (); /* { dg-error {no matching function call to '__riscv_vnmsac' with empty args} } */
+
+ __riscv_vnsrl (); /* { dg-error {no matching function call to '__riscv_vnsrl' with empty args} } */
+
+ __riscv_vfnmadd (); /* { dg-error {no matching function call to '__riscv_vfnmadd' with empty args} } */
+
+ __riscv_vfwsub_vv (); /* { dg-error {no matching function call to '__riscv_vfwsub_vv' with empty args} } */
+
+ __riscv_vfwredosum (); /* { dg-error {no matching function call to '__riscv_vfwredosum' with empty args} } */
}
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
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2024-02-07 9:27 [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker pan2.li
2024-02-07 10:21 ` juzhe.zhong
2024-02-08 1:41 ` Li, Pan2
2024-02-08 6:43 ` juzhe.zhong
2024-02-08 6:52 ` Li, Pan2
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