* [PATCH] OPTABS: Extend the number of expanding instructions pattern.
@ 2023-05-15 12:22 juzhe.zhong
2023-05-15 12:22 ` [PATCH] RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions juzhe.zhong
2023-05-15 12:51 ` [PATCH] OPTABS: Extend the number of expanding instructions pattern Richard Biener
0 siblings, 2 replies; 6+ messages in thread
From: juzhe.zhong @ 2023-05-15 12:22 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.guenther, rguenther, Juzhe-Zhong
From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Hi, Richi.
We (RVV) is going to add a rounding mode operand into floating-point instructions
which have 11 operands.
Since we are going have intrinsic that is adding rounding mode argument:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
This is the patch that is adding rounding mode operand in RISC-V port:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618573.html
You can see there are 11 operands in these patterns.
Is it Ok for trunk ?
Thanks
gcc/ChangeLog:
* optabs.cc (maybe_gen_insn): Add case to generate instruction that has 11 operands.
---
gcc/optabs.cc | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/gcc/optabs.cc b/gcc/optabs.cc
index c8e39c82d57..a12333c7169 100644
--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
@@ -8139,6 +8139,11 @@ maybe_gen_insn (enum insn_code icode, unsigned int nops,
ops[3].value, ops[4].value, ops[5].value,
ops[6].value, ops[7].value, ops[8].value,
ops[9].value);
+ case 11:
+ return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value,
+ ops[3].value, ops[4].value, ops[5].value,
+ ops[6].value, ops[7].value, ops[8].value,
+ ops[9].value, ops[10].value);
}
gcc_unreachable ();
}
--
2.36.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions
2023-05-15 12:22 [PATCH] OPTABS: Extend the number of expanding instructions pattern juzhe.zhong
@ 2023-05-15 12:22 ` juzhe.zhong
2023-05-15 13:43 ` Jeff Law
2023-05-15 12:51 ` [PATCH] OPTABS: Extend the number of expanding instructions pattern Richard Biener
1 sibling, 1 reply; 6+ messages in thread
From: juzhe.zhong @ 2023-05-15 12:22 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.guenther, rguenther, Juzhe-Zhong
From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
This patch is adding FRM and rounding mode into floating-point ternary instructions.
This patch should be merged after optabs.cc patch.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (function_expander::use_ternop_insn): Add default rounding mode.
* config/riscv/vector.md: Add rounding mode operand and FRM_REGNUM.
---
gcc/config/riscv/riscv-vector-builtins.cc | 7 +++
gcc/config/riscv/vector.md | 64 +++++++++++++++++------
2 files changed, 55 insertions(+), 16 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index f10f38f6425..b7458aaace6 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3460,6 +3460,13 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
+
+ /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
+ We add default rounding mode for the intrinsics that didn't model rounding
+ mode yet. */
+ if (opno != insn_data[icode].n_generator_args)
+ add_input_operand (Pmode, const0_rtx);
+
return generate_insn (icode);
}
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 0929d19d5ec..80f9ba9bd28 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -5902,8 +5902,10 @@
(match_operand 7 "const_int_operand")
(match_operand 8 "const_int_operand")
(match_operand 9 "const_int_operand")
+ (match_operand 10 "const_int_operand")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(match_operand:VF 2 "register_operand")
@@ -5927,8 +5929,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(match_operand:VF 2 "register_operand" " 0, vr, 0, vr")
@@ -5958,8 +5962,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(match_operand:VF 2 "register_operand" " vr, vr, vr, vr")
@@ -5989,8 +5995,10 @@
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
(match_operand 9 "const_int_operand" " i, i")
+ (match_operand 10 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(match_operand:VF 2 "register_operand" " vr, vr")
@@ -6024,8 +6032,10 @@
(match_operand 7 "const_int_operand")
(match_operand 8 "const_int_operand")
(match_operand 9 "const_int_operand")
+ (match_operand 10 "const_int_operand")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(vec_duplicate:VF
@@ -6045,8 +6055,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(vec_duplicate:VF
@@ -6077,8 +6089,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(vec_duplicate:VF
@@ -6109,8 +6123,10 @@
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
(match_operand 9 "const_int_operand" " i, i")
+ (match_operand 10 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(vec_duplicate:VF
@@ -6144,8 +6160,10 @@
(match_operand 7 "const_int_operand")
(match_operand 8 "const_int_operand")
(match_operand 9 "const_int_operand")
+ (match_operand 10 "const_int_operand")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
@@ -6170,8 +6188,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
@@ -6202,8 +6222,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
@@ -6234,8 +6256,10 @@
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
(match_operand 9 "const_int_operand" " i, i")
+ (match_operand 10 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
@@ -6270,8 +6294,10 @@
(match_operand 7 "const_int_operand")
(match_operand 8 "const_int_operand")
(match_operand 9 "const_int_operand")
+ (match_operand 10 "const_int_operand")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
@@ -6292,8 +6318,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
@@ -6325,8 +6353,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
@@ -6358,8 +6388,10 @@
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
(match_operand 9 "const_int_operand" " i, i")
+ (match_operand 10 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
--
2.36.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] OPTABS: Extend the number of expanding instructions pattern.
2023-05-15 12:22 [PATCH] OPTABS: Extend the number of expanding instructions pattern juzhe.zhong
2023-05-15 12:22 ` [PATCH] RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions juzhe.zhong
@ 2023-05-15 12:51 ` Richard Biener
2023-05-15 14:14 ` Li, Pan2
1 sibling, 1 reply; 6+ messages in thread
From: Richard Biener @ 2023-05-15 12:51 UTC (permalink / raw)
To: Juzhe-Zhong; +Cc: gcc-patches, richard.guenther
On Mon, 15 May 2023, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> Hi, Richi.
>
> We (RVV) is going to add a rounding mode operand into floating-point instructions
> which have 11 operands.
>
> Since we are going have intrinsic that is adding rounding mode argument:
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
>
> This is the patch that is adding rounding mode operand in RISC-V port:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618573.html
> You can see there are 11 operands in these patterns.
>
> Is it Ok for trunk ?
OK.
Richard.
> Thanks
>
> gcc/ChangeLog:
>
> * optabs.cc (maybe_gen_insn): Add case to generate instruction that has 11 operands.
>
> ---
> gcc/optabs.cc | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/gcc/optabs.cc b/gcc/optabs.cc
> index c8e39c82d57..a12333c7169 100644
> --- a/gcc/optabs.cc
> +++ b/gcc/optabs.cc
> @@ -8139,6 +8139,11 @@ maybe_gen_insn (enum insn_code icode, unsigned int nops,
> ops[3].value, ops[4].value, ops[5].value,
> ops[6].value, ops[7].value, ops[8].value,
> ops[9].value);
> + case 11:
> + return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value,
> + ops[3].value, ops[4].value, ops[5].value,
> + ops[6].value, ops[7].value, ops[8].value,
> + ops[9].value, ops[10].value);
> }
> gcc_unreachable ();
> }
>
--
Richard Biener <rguenther@suse.de>
SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg,
Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman;
HRB 36809 (AG Nuernberg)
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions
2023-05-15 12:22 ` [PATCH] RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions juzhe.zhong
@ 2023-05-15 13:43 ` Jeff Law
0 siblings, 0 replies; 6+ messages in thread
From: Jeff Law @ 2023-05-15 13:43 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: richard.guenther, rguenther
On 5/15/23 06:22, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> This patch is adding FRM and rounding mode into floating-point ternary instructions.
> This patch should be merged after optabs.cc patch.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc (function_expander::use_ternop_insn): Add default rounding mode.
> * config/riscv/vector.md: Add rounding mode operand and FRM_REGNUM.
OK
jeff
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH] OPTABS: Extend the number of expanding instructions pattern.
2023-05-15 12:51 ` [PATCH] OPTABS: Extend the number of expanding instructions pattern Richard Biener
@ 2023-05-15 14:14 ` Li, Pan2
0 siblings, 0 replies; 6+ messages in thread
From: Li, Pan2 @ 2023-05-15 14:14 UTC (permalink / raw)
To: Richard Biener, Juzhe-Zhong; +Cc: gcc-patches, richard.guenther
Committed, thanks Richard.
Pan
-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Richard Biener via Gcc-patches
Sent: Monday, May 15, 2023 8:52 PM
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Cc: gcc-patches@gcc.gnu.org; richard.guenther@gmail.com
Subject: Re: [PATCH] OPTABS: Extend the number of expanding instructions pattern.
On Mon, 15 May 2023, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> Hi, Richi.
>
> We (RVV) is going to add a rounding mode operand into floating-point
> instructions which have 11 operands.
>
> Since we are going have intrinsic that is adding rounding mode argument:
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
>
> This is the patch that is adding rounding mode operand in RISC-V port:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618573.html
> You can see there are 11 operands in these patterns.
>
> Is it Ok for trunk ?
OK.
Richard.
> Thanks
>
> gcc/ChangeLog:
>
> * optabs.cc (maybe_gen_insn): Add case to generate instruction that has 11 operands.
>
> ---
> gcc/optabs.cc | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/gcc/optabs.cc b/gcc/optabs.cc index
> c8e39c82d57..a12333c7169 100644
> --- a/gcc/optabs.cc
> +++ b/gcc/optabs.cc
> @@ -8139,6 +8139,11 @@ maybe_gen_insn (enum insn_code icode, unsigned int nops,
> ops[3].value, ops[4].value, ops[5].value,
> ops[6].value, ops[7].value, ops[8].value,
> ops[9].value);
> + case 11:
> + return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value,
> + ops[3].value, ops[4].value, ops[5].value,
> + ops[6].value, ops[7].value, ops[8].value,
> + ops[9].value, ops[10].value);
> }
> gcc_unreachable ();
> }
>
--
Richard Biener <rguenther@suse.de>
SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg, Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman; HRB 36809 (AG Nuernberg)
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions
@ 2023-05-15 12:16 juzhe.zhong
0 siblings, 0 replies; 6+ messages in thread
From: juzhe.zhong @ 2023-05-15 12:16 UTC (permalink / raw)
To: gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer, jeffreyalaw, rdapp.gcc,
Juzhe-Zhong
From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
This patch is adding FRM and rounding mode into floating-point ternary instructions.
This patch should be merged after optabs.cc patch.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (function_expander::use_ternop_insn): Add default rounding mode.
* config/riscv/vector.md: Add rounding mode operand and FRM_REGNUM.
---
gcc/config/riscv/riscv-vector-builtins.cc | 7 +++
gcc/config/riscv/vector.md | 64 +++++++++++++++++------
2 files changed, 55 insertions(+), 16 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index f10f38f6425..b7458aaace6 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3460,6 +3460,13 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
+
+ /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
+ We add default rounding mode for the intrinsics that didn't model rounding
+ mode yet. */
+ if (opno != insn_data[icode].n_generator_args)
+ add_input_operand (Pmode, const0_rtx);
+
return generate_insn (icode);
}
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 0929d19d5ec..80f9ba9bd28 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -5902,8 +5902,10 @@
(match_operand 7 "const_int_operand")
(match_operand 8 "const_int_operand")
(match_operand 9 "const_int_operand")
+ (match_operand 10 "const_int_operand")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(match_operand:VF 2 "register_operand")
@@ -5927,8 +5929,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(match_operand:VF 2 "register_operand" " 0, vr, 0, vr")
@@ -5958,8 +5962,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(match_operand:VF 2 "register_operand" " vr, vr, vr, vr")
@@ -5989,8 +5995,10 @@
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
(match_operand 9 "const_int_operand" " i, i")
+ (match_operand 10 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(match_operand:VF 2 "register_operand" " vr, vr")
@@ -6024,8 +6032,10 @@
(match_operand 7 "const_int_operand")
(match_operand 8 "const_int_operand")
(match_operand 9 "const_int_operand")
+ (match_operand 10 "const_int_operand")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(vec_duplicate:VF
@@ -6045,8 +6055,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(vec_duplicate:VF
@@ -6077,8 +6089,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(vec_duplicate:VF
@@ -6109,8 +6123,10 @@
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
(match_operand 9 "const_int_operand" " i, i")
+ (match_operand 10 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(mult:VF
(vec_duplicate:VF
@@ -6144,8 +6160,10 @@
(match_operand 7 "const_int_operand")
(match_operand 8 "const_int_operand")
(match_operand 9 "const_int_operand")
+ (match_operand 10 "const_int_operand")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
@@ -6170,8 +6188,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
@@ -6202,8 +6222,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
@@ -6234,8 +6256,10 @@
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
(match_operand 9 "const_int_operand" " i, i")
+ (match_operand 10 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
@@ -6270,8 +6294,10 @@
(match_operand 7 "const_int_operand")
(match_operand 8 "const_int_operand")
(match_operand 9 "const_int_operand")
+ (match_operand 10 "const_int_operand")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
@@ -6292,8 +6318,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
@@ -6325,8 +6353,10 @@
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
@@ -6358,8 +6388,10 @@
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
(match_operand 9 "const_int_operand" " i, i")
+ (match_operand 10 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VF
(neg:VF
(mult:VF
--
2.36.1
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-05-15 14:14 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2023-05-15 12:22 [PATCH] OPTABS: Extend the number of expanding instructions pattern juzhe.zhong
2023-05-15 12:22 ` [PATCH] RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions juzhe.zhong
2023-05-15 13:43 ` Jeff Law
2023-05-15 12:51 ` [PATCH] OPTABS: Extend the number of expanding instructions pattern Richard Biener
2023-05-15 14:14 ` Li, Pan2
-- strict thread matches above, loose matches on Subject: below --
2023-05-15 12:16 [PATCH] RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions juzhe.zhong
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