* [PATCH v6, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions
@ 2022-12-19 6:27 HAO CHEN GUI
2022-12-20 18:03 ` Segher Boessenkool
0 siblings, 1 reply; 2+ messages in thread
From: HAO CHEN GUI @ 2022-12-19 6:27 UTC (permalink / raw)
To: gcc-patches; +Cc: Segher Boessenkool, David, Kewen.Lin, Peter Bergner
Hi,
This patch fixes several problems:
1. The exponent of double-precision can be put into a SImode register.
So "xsxexpdp" doesn't require 64-bit environment. Also "xsxsigdp",
"xsiexpdp" and "xsiexpdpf" can put exponent into a GPR register.
2. "TARGET_64BIT" check in insn conditions should be replaced with
"TARGET_POWERPC64" check.
3. "lp64" check in test cases should be replaced with "has_arch_ppc64"
check. "ilp32" check should be replaced with "dg-skip-if has_arch_ppc64".
This patch keeps outer interfaces of these builtins unchanged.
Bootstrapped and tested on powerpc64-linux BE and LE with no regressions.
Is this okay for trunk? Any recommendations? Thanks a lot.
ChangeLog
2022-12-19 Haochen Gui <guihaoc@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtins.def
(__builtin_vsx_scalar_extract_exp): Set return type to const unsigned
int and set its bif-pattern to xsxexpdp_si, move it from power9-64 to
power9 catalog.
(__builtin_vsx_scalar_extract_sig): Set return type to const unsigned
long long.
(__builtin_vsx_scalar_insert_exp): Set its bif-pattern to xsiexpdp_di
unsigned int.
(__builtin_vsx_scalar_insert_exp_dp): Set its bif-pattern to
xsiexpdpf_di.
* config/rs6000/vsx.md (xsxexpdp): Rename to ...
(xsxexpdp_<mode>): ..., set mode of operand 0 to GPR and remove
TARGET_64BIT check.
(xsxsigdp): Change insn condition from TARGET_64BIT to TARGET_POWERPC64.
(xsiexpdp): Rename to ...
(xsiexpdp_<mode>): ..., set mode of operand 2 to GPR and change insn
condition from TARGET_64BIT to TARGET_POWERPC64.
(xsiexpdpf): Rename to ...
(xsiexpdpf_<mode>): ..., set mode of operand 2 to GPR and change insn
condition from TARGET_64BIT to TARGET_POWERPC64.
* doc/extend.texi (scalar_extract_exp): Remove 64-bit environment
requirement when it has a 64-bit argument.
gcc/testsuite/
* gcc.target/powerpc/bfp/scalar-extract-exp-0.c: Remove lp64 check.
* gcc.target/powerpc/bfp/scalar-extract-exp-1.c: Likewise.
* gcc.target/powerpc/bfp/scalar-extract-exp-2.c: Deleted as the case is
invalid now.
* gcc.target/powerpc/bfp/scalar-extract-exp-6.c: Remove lp64 check.
* gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Replace lp64 check
with has_arch_ppc64.
* gcc.target/powerpc/bfp/scalar-extract-sig-1.c: Likewise.
* gcc.target/powerpc/bfp/scalar-extract-sig-2.c: Replace ilp32 check
with dg skip has_arch_ppc64.
* gcc.target/powerpc/bfp/scalar-extract-sig-6.c: Replace lp64 check
with has_arch_ppc64.
* gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Likewise.
* gcc.target/powerpc/bfp/scalar-insert-exp-1.c: Likewise.
* gcc.target/powerpc/bfp/scalar-insert-exp-12.c: Likewise.
* gcc.target/powerpc/bfp/scalar-insert-exp-13.c: Likewise.
* gcc.target/powerpc/bfp/scalar-insert-exp-2.c: Replace ilp32 check
with dg skip has_arch_ppc64.
* gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Replace lp64 check
with has_arch_ppc64.
* gcc.target/powerpc/bfp/scalar-insert-exp-4.c: Likewise.
* gcc.target/powerpc/bfp/scalar-insert-exp-5.c: Replace ilp32 check
with dg-skip-if has_arch_ppc64.
patch.diff
diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index f76f54793d7..b1b5002d7d9 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -2833,6 +2833,8 @@
const signed int __builtin_dtstsfi_ov_td (const int<6>, _Decimal128);
TSTSFI_OV_TD dfptstsfi_unordered_td {}
+ const signed int __builtin_vsx_scalar_extract_exp (double);
+ VSEEDP xsxexpdp_si {}
[power9-64]
void __builtin_altivec_xst_len_r (vsc, void *, long);
@@ -2847,18 +2849,15 @@
pure vsc __builtin_vsx_lxvl (const void *, signed long);
LXVL lxvl {}
- const signed long __builtin_vsx_scalar_extract_exp (double);
- VSEEDP xsxexpdp {}
-
- const signed long __builtin_vsx_scalar_extract_sig (double);
+ const signed long long __builtin_vsx_scalar_extract_sig (double);
VSESDP xsxsigdp {}
const double __builtin_vsx_scalar_insert_exp (unsigned long long, \
unsigned long long);
- VSIEDP xsiexpdp {}
+ VSIEDP xsiexpdp_di {}
const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned long long);
- VSIEDPF xsiexpdpf {}
+ VSIEDPF xsiexpdpf_di {}
pure vsc __builtin_vsx_xl_len_r (void *, signed long);
XL_LEN_R xl_len_r {}
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index fb5cf04147e..e1c905a3f91 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5089,11 +5089,11 @@ (define_insn "xsxexpqp_<mode>"
[(set_attr "type" "vecmove")])
;; VSX Scalar Extract Exponent Double-Precision
-(define_insn "xsxexpdp"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")]
+(define_insn "xsxexpdp_<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (unspec:GPR [(match_operand:DF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_SXEXPDP))]
- "TARGET_P9_VECTOR && TARGET_64BIT"
+ "TARGET_P9_VECTOR"
"xsxexpdp %0,%x1"
[(set_attr "type" "integer")])
@@ -5111,7 +5111,7 @@ (define_insn "xsxsigdp"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_SXSIG))]
- "TARGET_P9_VECTOR && TARGET_64BIT"
+ "TARGET_P9_VECTOR && TARGET_POWERPC64"
"xsxsigdp %0,%x1"
[(set_attr "type" "integer")])
@@ -5137,22 +5137,22 @@ (define_insn "xsiexpqp_<mode>"
[(set_attr "type" "vecmove")])
;; VSX Scalar Insert Exponent Double-Precision
-(define_insn "xsiexpdp"
+(define_insn "xsiexpdp_<mode>"
[(set (match_operand:DF 0 "vsx_register_operand" "=wa")
(unspec:DF [(match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "register_operand" "r")]
+ (match_operand:GPR 2 "register_operand" "r")]
UNSPEC_VSX_SIEXPDP))]
- "TARGET_P9_VECTOR && TARGET_64BIT"
+ "TARGET_P9_VECTOR && TARGET_POWERPC64"
"xsiexpdp %x0,%1,%2"
[(set_attr "type" "fpsimple")])
;; VSX Scalar Insert Exponent Double-Precision Floating Point Argument
-(define_insn "xsiexpdpf"
+(define_insn "xsiexpdpf_<mode>"
[(set (match_operand:DF 0 "vsx_register_operand" "=wa")
(unspec:DF [(match_operand:DF 1 "register_operand" "r")
- (match_operand:DI 2 "register_operand" "r")]
+ (match_operand:GPR 2 "register_operand" "r")]
UNSPEC_VSX_SIEXPDP))]
- "TARGET_P9_VECTOR && TARGET_64BIT"
+ "TARGET_P9_VECTOR && TARGET_POWERPC64"
"xsiexpdp %x0,%1,%2"
[(set_attr "type" "fpsimple")])
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index b1dd39e64b8..773e45022a3 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -19598,7 +19598,10 @@ bool scalar_test_neg (double source);
bool scalar_test_neg (__ieee128 source);
@end smallexample
-The @code{scalar_extract_exp} and @code{scalar_extract_sig}
+The @code{scalar_extract_exp} with a 64-bit source argument
+functions requires an environment supporting ISA 3.0 or later.
+The @code{scalar_extract_exp} with a 128-bit source argument
+and @code{scalar_extract_sig}
functions require a 64-bit environment supporting ISA 3.0 or later.
The @code{scalar_extract_exp} and @code{scalar_extract_sig} built-in
functions return the significand and the biased exponent value
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c
index 35bf1b240f3..d971833748e 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c
@@ -1,9 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power9" } */
-/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
unsigned int
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-1.c
index 9737762c1d4..1cb438f9b70 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-1.c
@@ -1,9 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power8" } */
-/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
unsigned int
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-2.c
deleted file mode 100644
index 53b67c95cf9..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-2.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target ilp32 } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9" } */
-
-/* This test only runs on 32-bit configurations, where a compiler error
- should be issued because this builtin is not available on
- 32-bit configurations. */
-
-#include <altivec.h>
-
-unsigned int
-get_exponent (double *p)
-{
- double source = *p;
-
- return scalar_extract_exp (source); /* { dg-error "'__builtin_vsx_scalar_extract_exp' requires the" } */
-}
-
-
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c
index b9dd7d61aae..e0581cd3dee 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c
@@ -1,9 +1,7 @@
/* { dg-do run { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target p9vector_hw } */
/* { dg-options "-mdejagnu-cpu=power9" } */
-/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
#include <stdlib.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
index 637080652b7..d22f7d1b274 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-1.c
index f12eed3d9d5..64747d73a51 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-1.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power8" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c
index 39ee74c94dc..148b5fbd9fa 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target ilp32 } */
+/* { dg-skip-if "" { has_arch_ppc64 } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power9" } */
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
index c85072da138..561be53fb9b 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target p9vector_hw } */
/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
index d8243258a67..88d77564158 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c
index 8260b107178..2f219ddc83a 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power8" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
index 384fc9cc675..9eade34d9ad 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target p9vector_hw } */
/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
index 0e004224277..674fba951ae 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target p9vector_hw } */
/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c
index efd69725905..956c1183beb 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target ilp32 } */
+/* { dg-skip-if "" { has_arch_ppc64 } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power9" } */
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
index 3ecbe3318e8..afa2b83f2d2 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c
index 1699c67a2f1..6dc06dd34ea 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power8" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c
index f85966a6fdf..9a7949fb89a 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target ilp32 } */
+/* { dg-skip-if "" { has_arch_ppc64 } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power9" } */
^ permalink raw reply [flat|nested] 2+ messages in thread* Re: [PATCH v6, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions
2022-12-19 6:27 [PATCH v6, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions HAO CHEN GUI
@ 2022-12-20 18:03 ` Segher Boessenkool
0 siblings, 0 replies; 2+ messages in thread
From: Segher Boessenkool @ 2022-12-20 18:03 UTC (permalink / raw)
To: HAO CHEN GUI; +Cc: gcc-patches, David, Kewen.Lin, Peter Bergner
Hi!
On Mon, Dec 19, 2022 at 02:27:57PM +0800, HAO CHEN GUI wrote:
> This patch fixes several problems:
> 1. The exponent of double-precision can be put into a SImode register.
> So "xsxexpdp" doesn't require 64-bit environment. Also "xsxsigdp",
> "xsiexpdp" and "xsiexpdpf" can put exponent into a GPR register.
>
> 2. "TARGET_64BIT" check in insn conditions should be replaced with
> "TARGET_POWERPC64" check.
>
> 3. "lp64" check in test cases should be replaced with "has_arch_ppc64"
> check. "ilp32" check should be replaced with "dg-skip-if has_arch_ppc64".
These things are independent. Please do independent patches (a series
is fine and even preferred, of course). Not only is this much harder to
review the way it is, it was harder to write as well, write changelog
for, etc. Often when you prepare patches it becomes apparent that you
should have structured things a bit differently. That is a good time to
do exactly so :-)
> This patch keeps outer interfaces of these builtins unchanged.
Of course. This patch doesn't edit any builtins, it changes only the
machine description. "Of the corresponding builtins" :-)
Segher
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2022-12-20 18:04 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-19 6:27 [PATCH v6, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions HAO CHEN GUI
2022-12-20 18:03 ` Segher Boessenkool
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).