* [PATCH] RISC-V: Fix annotation
@ 2022-12-14 8:39 juzhe.zhong
2022-12-16 19:53 ` Jeff Law
0 siblings, 1 reply; 5+ messages in thread
From: juzhe.zhong @ 2022-12-14 8:39 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc: Fix annotation.
---
gcc/config/riscv/riscv-vsetvl.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index c602426b542..3ca3fc15e5a 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -35,7 +35,7 @@ along with GCC; see the file COPYING3. If not see
- Each avl operand is either an immediate (must be in range 0 ~ 31) or reg.
- This pass consists of 3 phases:
+ This pass consists of 5 phases:
- Phase 1 - compute VL/VTYPE demanded information within each block
by backward data-flow analysis.
--
2.36.3
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH] RISC-V: Fix annotation
@ 2022-08-30 2:57 juzhe.zhong
2022-09-01 2:05 ` Kito Cheng
0 siblings, 1 reply; 5+ messages in thread
From: juzhe.zhong @ 2022-08-30 2:57 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, zhongjuzhe
From: zhongjuzhe <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv.h (enum reg_class): Change vype to vtype.
---
gcc/config/riscv/riscv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 29582f7c545..3ee5a93ce6a 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -462,7 +462,7 @@ enum reg_class
FP_REGS, /* floating-point registers */
FRAME_REGS, /* arg pointer and frame pointer */
VL_REGS, /* vl register */
- VTYPE_REGS, /* vype register */
+ VTYPE_REGS, /* vtype register */
VM_REGS, /* v0.t registers */
VD_REGS, /* vector registers except v0.t */
V_REGS, /* vector registers */
--
2.36.1
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] RISC-V: Fix annotation
2022-08-30 2:57 juzhe.zhong
@ 2022-09-01 2:05 ` Kito Cheng
0 siblings, 0 replies; 5+ messages in thread
From: Kito Cheng @ 2022-09-01 2:05 UTC (permalink / raw)
To: juzhe.zhong; +Cc: GCC Patches
Thanks, pushed to trunk.
On Tue, Aug 30, 2022 at 10:58 AM <juzhe.zhong@rivai.ai> wrote:
>
> From: zhongjuzhe <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.h (enum reg_class): Change vype to vtype.
>
> ---
> gcc/config/riscv/riscv.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index 29582f7c545..3ee5a93ce6a 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -462,7 +462,7 @@ enum reg_class
> FP_REGS, /* floating-point registers */
> FRAME_REGS, /* arg pointer and frame pointer */
> VL_REGS, /* vl register */
> - VTYPE_REGS, /* vype register */
> + VTYPE_REGS, /* vtype register */
> VM_REGS, /* v0.t registers */
> VD_REGS, /* vector registers except v0.t */
> V_REGS, /* vector registers */
> --
> 2.36.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-12-19 15:07 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2022-12-14 8:39 [PATCH] RISC-V: Fix annotation juzhe.zhong
2022-12-16 19:53 ` Jeff Law
2022-12-19 15:07 ` Kito Cheng
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2022-08-30 2:57 juzhe.zhong
2022-09-01 2:05 ` Kito Cheng
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