Re: [PATCH 0/7] ira/lra: Support subreg coalesce

[Jeff Law <jeffreyalaw@gmail.com>]

On 11/11/23 08:33, Richard Sandiford wrote:

>> Joern's code is a bit of a mess, but Jivan and I are slowly untangling
>> it from a correctness standpoint.  It'll also need the usual cleanups.
> 
> Ah, nice!  How configurable are the bit ranges?  We might be able to use
> something similar to track lanes in a vector operation, to detect the
> dead code in:
> 
>     ins v0.b[4], w0
>     ...
>     ins v0.b[4], w1
> 
> It sounds like the bit ranges you have now would do that for some
> common/useful cases, even if it doesn't handle the general case.
It could probably be extended to handle more cases.  Right now the 
regions tracked are static.  Bits 0..7, 8..16, 16..31 and 32..64.  I 
don't think extending it to additional regions would be terribly hard.

> 
> Maybe dead lanes are better tracked at the gimple level though, not sure.
> (But AArch64 might need to lower lane operations more than it does now if
> we want gimple to handle it.)
I'd think the best place depends on what you want to do with the dead 
lane information.  THe more complex the transformation you want to make 
the more likely gimple is the right spot.  If you're looking to do 
something simplistic like Joern's code does when it finds dead chunks 
RTL seems like the natural choice.

jeff