Re: [PATCH 0/7] ira/lra: Support subreg coalesce

[Lehua Ding <lehua.ding@rivai.ai>]

Hi Dimitar,

On 2023/11/11 0:00, Dimitar Dimitrov wrote:
> On Fri, Nov 10, 2023 at 04:53:57PM +0800, Lehua Ding wrote:
>>>> The divide by zero error above is interesting. I'm not sure why
>>>> ira_reg_class_max_nregs[] yields 0 for the pseudo register 168 in
>>>> the following rtx:
>>>> (debug_insn 168 167 169 19 (var_location:SI encoding (reg/v:SI 168 [
>>>> encoding ])) -1
>>>>        (nil))
>>>
>>> I just cross compiled an arm-none-eabi compiler and didn't encounter
>>> this error, can you give me a little more config info about build? For
>>> example, flags_for_target, etc. Thanks again.
>>>
>>
>> Forgot, please also provide the version information of newlib code.
>>
> 
> These are the GIT commit hashes which I tested:
>    gcc 39d81b667373b0033f44702a4b532a4618dde9ff
>    binutils c96ceed9dce7617f270aa4742645706e535f74b7
>    newlib 39f734a857e2692224715b03b99fc7bd83e94a0f
> 
> This is the script I'm using to build arm-none-eabi:
>     https://github.com/dinuxbg/gnupru/blob/master/testing/manual-build-arm.sh
> The build steps and config parameters are easily seen there.
> 
> Note that the Linaro CI is also detecting issues. It hits ICEs when
> building libgcc:
>    https://patchwork.sourceware.org/project/gcc/patch/20231108034740.834590-8-lehua.ding@rivai.ai/

Thanks so much for the information, I can reproduce the problem now! I 
will fixed these bugs in the V2 patchs.

-- 
Best,
Lehua (RiVAI)
lehua.ding@rivai.ai