Re: [PATCH 0/7] ira/lra: Support subreg coalesce

[Lehua Ding <lehua.ding@rivai.ai>]

Hi Jeff,

On 2023/11/9 3:13, Jeff Law wrote:
> The other thing to ponder.  Jivan and I have been banging on Joern's 
> sub-object tracking bits for a totally different problem in the RISC-V 
> space.  But there may be some overlap.
> 
> Essentially Joern's code tracks liveness for a few chunks in registers. 
> bits 0..7, bits 8..15, bits 16..31 and bits 32..63.  This includes 
> propagating liveness from the destination through to the sources.  SO 
> for example if we have
> 
> (set (reg:SI dest) (plus:SI (srcreg1:SI) (srcreg2:SI)))
> 
> If we had previously determined that only bits 0..15 were live in DEST, 
> then we'll propagate that into the source registers.
> 
> The goal is to ultimately transform something like
> 
> (set (dest:mode) (any_extend:mode (reg:narrower_mode)))
> 
> into
> 
> (set (dest:mode) (subreg:mode (reg:narrower_mode)))
> 
> Where the latter typically will get simplified and propagated away.
> 
> 
> Joern's code is a bit of a mess, but Jivan and I are slowly untangling 
> it from a correctness standpoint.  It'll also need the usual cleanups.
> 
> Anyway, point being I think it'll be worth looking at Lehua's bits and 
> Joern's bits to see if there's anything that can and should be shared. 
> Given I'm getting fairly familiar with Joern's bits, that likely falls 
> to me.

Maybe subreg live range track classes (in patch 2) could be shared. 
Including range's UNION, Diff, and other operations should be similar. 
I'll see if I'm going to extract a separate patch to review this part. 
What do you think?

-- 
Best,
Lehua (RiVAI)
lehua.ding@rivai.ai