[PATCH] s390: Add more vcond_mask patterns.

[Robin Dapp <rdapp@linux.ibm.com>]

[-- Attachment #1: Type: text/plain, Size: 605 bytes --]

Hi,

this patch adds vcond_mask patterns with mixed mode for the 
condition/mask and source, target so e.g. boolean conditions become 
possible:

   vtarget = bool_cond ? vsource1 : vsource2.

Is it OK for trunk?

Regards
  Robin

gcc/ChangeLog:

         * config/s390/vector.md 
(vcond_mask_<VX_VEC_CONV_BFP:mode><VX_VEC_CONV_INT:mode>): Add 
vcond_mask with mixed mode.
         (vcond_mask_<VX_VEC_CONV_INT:mode><VX_VEC_CONV_BFP:mode>): Dito.

gcc/testsuite/ChangeLog:

         * gcc.target/s390/vector/vcond-mixed-double.c: New test.
         * gcc.target/s390/vector/vcond-mixed-float.c: New test.

[-- Attachment #2: 0003-s390-Add-more-vcond_mask-patterns.patch --]
[-- Type: text/x-patch, Size: 4550 bytes --]

From 4ce2d9a3f43c44d35142a726921258540adfca51 Mon Sep 17 00:00:00 2001
From: Robin Dapp <rdapp@linux.ibm.com>
Date: Thu, 18 Mar 2021 11:31:02 +0100
Subject: [PATCH 3/7] s390: Add more vcond_mask patterns.

Add vcond_mask patterns that allow another mode for the condition/mask
than the source and target so e.g. boolean conditions become possible:

  vtarget = bool_cond ? vsource1 : vsource2.

Also, add test cases for vcond_mask with mixed modes.
---
 gcc/config/s390/vector.md                     | 21 ++++++++++
 .../s390/vector/vcond-mixed-double.c          | 41 +++++++++++++++++++
 .../s390/vector/vcond-mixed-float.c           | 41 +++++++++++++++++++
 3 files changed, 103 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/s390/vector/vcond-mixed-double.c
 create mode 100644 gcc/testsuite/gcc.target/s390/vector/vcond-mixed-float.c

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index c80d582a300..7c730432d80 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -36,6 +36,7 @@
 (define_mode_iterator V_HW2 [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE")
 			     (V1TF "TARGET_VXE") (TF "TARGET_VXE")])
 
+
 (define_mode_iterator V_HW_64 [V2DI V2DF])
 (define_mode_iterator VT_HW_HSDT [V8HI V4SI V4SF V2DI V2DF V1TI V1TF TI TF])
 (define_mode_iterator V_HW_HSD [V8HI V4SI (V4SF "TARGET_VXE") V2DI V2DF])
@@ -725,6 +726,26 @@
   "TARGET_VX"
   "operands[4] = CONST0_RTX (<TOINTVEC>mode);")
 
+(define_expand "vcond_mask_<VX_VEC_CONV_BFP:mode><VX_VEC_CONV_INT:mode>"
+  [(set (match_operand:VX_VEC_CONV_BFP 0 "register_operand" "")
+	(if_then_else:VX_VEC_CONV_BFP
+	 (eq (match_operand:VX_VEC_CONV_INT 3 "register_operand" "")
+	     (match_dup 4))
+	 (match_operand:VX_VEC_CONV_BFP 2 "register_operand" "")
+	 (match_operand:VX_VEC_CONV_BFP 1 "register_operand" "")))]
+  "TARGET_VX"
+  "operands[4] = CONST0_RTX (<VX_VEC_CONV_INT:MODE>mode);")
+
+(define_expand "vcond_mask_<VX_VEC_CONV_INT:mode><VX_VEC_CONV_BFP:mode>"
+  [(set (match_operand:VX_VEC_CONV_INT 0 "register_operand" "")
+	(if_then_else:VX_VEC_CONV_INT
+	 (eq (match_operand:VX_VEC_CONV_BFP 3 "register_operand" "")
+	     (match_dup 4))
+	 (match_operand:VX_VEC_CONV_INT 2 "register_operand" "")
+	 (match_operand:VX_VEC_CONV_INT 1 "register_operand" "")))]
+  "TARGET_VX"
+  "operands[4] = CONST0_RTX (<VX_VEC_CONV_BFP:MODE>mode);")
+
 
 ; We only have HW support for byte vectors.  The middle-end is
 ; supposed to lower the mode if required.
diff --git a/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-double.c b/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-double.c
new file mode 100644
index 00000000000..8795d08a732
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-double.c
@@ -0,0 +1,41 @@
+/* Check for vectorization of mixed conditionals.  */
+/* { dg-do compile { target { s390*-*-* } } } */
+/* { dg-options "-O3 -march=z14 -mzarch" } */
+
+double xd[1024];
+double zd[1024];
+double wd[1024];
+
+long xl[1024];
+long zl[1024];
+long wl[1024];
+
+void foold ()
+{
+  int i;
+  for (i = 0; i < 1024; ++i)
+    zd[i] = xl[i] ? zd[i] : wd[i];
+}
+
+void foodl ()
+{
+  int i;
+  for (i = 0; i < 1024; ++i)
+    zl[i] = xd[i] ? zl[i] : wl[i];
+}
+
+void foold2 ()
+{
+  int i;
+  for (i = 0; i < 1024; ++i)
+    zd[i] = (xd[i] > 0) ? zd[i] : wd[i];
+}
+
+void foold3 ()
+{
+  int i;
+  for (i = 0; i < 1024; ++i)
+    zd[i] = (xd[i] > 0. & wd[i] < 0.) ? zd[i] : wd[i];
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-float.c b/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-float.c
new file mode 100644
index 00000000000..1153cace420
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-float.c
@@ -0,0 +1,41 @@
+/* Check for vectorization of mixed conditionals.  */
+/* { dg-do compile { target { s390*-*-* } } } */
+/* { dg-options "-O3 -march=z15 -mzarch" } */
+
+float xf[1024];
+float zf[1024];
+float wf[1024];
+
+int xi[1024];
+int zi[1024];
+int wi[1024];
+
+void fooif ()
+{
+  int i;
+  for (i = 0; i < 1024; ++i)
+    zf[i] = xi[i] ? zf[i] : wf[i];
+}
+
+void foofi ()
+{
+  int i;
+  for (i = 0; i < 1024; ++i)
+    zi[i] = xf[i] ? zi[i] : wi[i];
+}
+
+void fooif2 ()
+{
+  int i;
+  for (i = 0; i < 1024; ++i)
+    zf[i] = (xf[i] > 0) ? zf[i] : wf[i];
+}
+
+void fooif3 ()
+{
+  int i;
+  for (i = 0; i < 1024; ++i)
+    zf[i] = (xf[i] > 0.f & wf[i] < 0.f) ? zf[i] : wf[i];
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */
-- 
2.23.0