From: jiawei@iscas.ac.cn
To: "Kito Cheng" <kito.cheng@gmail.com>
Cc: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com,
palmer@rivosinc.com, juzhe.zhong@rivai.ai,
christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu,
wuwei2016@iscas.ac.cn
Subject: Re: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.
Date: Tue, 15 Nov 2022 10:37:43 +0800 (GMT+08:00) [thread overview]
Message-ID: <4daf8bdf.263a4.18479264c94.Coremail.jiawei@iscas.ac.cn> (raw)
In-Reply-To: <CA+yXCZDsKb-OTTgz9KgY9S4EBShX1F4Cq+3Wr4rNtdytU35b=Q@mail.gmail.com>
> -----原始邮件-----
> 发件人: "Kito Cheng" <kito.cheng@gmail.com>
> 发送时间: 2022-11-15 09:48:26 (星期二)
> 收件人: jiawei <jiawei@iscas.ac.cn>
> 抄送: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, palmer@rivosinc.com, juzhe.zhong@rivai.ai, christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu, wuwei2016@iscas.ac.cn
> 主题: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.
>
> Could you provide some testcase?
Sorry for not giving a clear description，
You can use amost all testcases in gcc.target/riscv/rvv/base/spill-*.c
compile with -march=rv64gcv and check the assemble file spill-*.s,
before this patch, it will generate assemble code contain additional
`addi sp,sp,0`:
```
csrr t0,vlenb
slli t1,t0,1
add sp,sp,t1
addi sp,sp,0
ld s0,24(sp)
addi sp,sp,32
jr ra
```
after this patch it will removed:
```
csrr t0,vlenb
slli t1,t0,1
add sp,sp,t1
ld s0,24(sp)
addi sp,sp,32
jr ra
```
>
> On Tue, Nov 15, 2022 at 12:29 AM jiawei <jiawei@iscas.ac.cn> wrote:
> >
> > Skip add insn generate if the adjust size equal to zero.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv.cc (riscv_expand_epilogue):
> > New if control segement.
> >
> > ---
> > gcc/config/riscv/riscv.cc | 18 ++++++++++--------
> > 1 file changed, 10 insertions(+), 8 deletions(-)
> >
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 02a01ca0b7c..af138db7545 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style)
> > }
> >
> > /* Get an rtx for STEP1 that we can add to BASE. */
> > - rtx adjust = GEN_INT (step1.to_constant ());
> > - if (!SMALL_OPERAND (step1.to_constant ()))
> > + if (step1.to_constant () != 0){
> > + rtx adjust = GEN_INT (step1.to_constant ());
> > + if (!SMALL_OPERAND (step1.to_constant ()))
> > {
> > riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
> > adjust = RISCV_PROLOGUE_TEMP (Pmode);
> > }
> >
> > - insn = emit_insn (
> > + insn = emit_insn (
> > gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
> >
> > - rtx dwarf = NULL_RTX;
> > - rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
> > + rtx dwarf = NULL_RTX;
> > + rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
> > GEN_INT (step2));
> >
> > - dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
> > - RTX_FRAME_RELATED_P (insn) = 1;
> > + dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
> > + RTX_FRAME_RELATED_P (insn) = 1;
> >
> > - REG_NOTES (insn) = dwarf;
> > + REG_NOTES (insn) = dwarf;
> > + }
> > }
> > else if (frame_pointer_needed)
> > {
> > --
> > 2.25.1
> >
</jiawei@iscas.ac.cn></jiawei@iscas.ac.cn></kito.cheng@gmail.com>
next prev parent reply other threads:[~2022-11-15 2:37 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-14 16:29 jiawei
2022-11-15 1:48 ` Kito Cheng
2022-11-15 2:37 ` jiawei [this message]
2022-11-15 2:46 ` juzhe.zhong
2022-11-15 3:13 ` Kito Cheng
2022-11-15 3:42 ` Jeff Law
2022-11-15 3:30 ` Jeff Law
2022-11-15 10:35 ` Philipp Tomsich
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