Re: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.

["juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>]

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I think you'd better change assembler checking of "spill-*.c" cases.
Check they don't have "addi sp,sp,0" redundant instruction.
Let's see whether Kito aggree with that.


juzhe.zhong@rivai.ai
 
From: jiawei
Date: 2022-11-15 10:37
To: Kito Cheng
CC: gcc-patches; kito.cheng; palmer; juzhe.zhong; christoph.muellner; philipp.tomsich; wuwei2016
Subject: Re: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.
> -----原始邮件-----
&gt; 发件人: "Kito Cheng" <kito.cheng@gmail.com>
&gt; 发送时间: 2022-11-15 09:48:26 (星期二)
&gt; 收件人: jiawei <jiawei@iscas.ac.cn>
&gt; 抄送: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, palmer@rivosinc.com, juzhe.zhong@rivai.ai, christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu, wuwei2016@iscas.ac.cn
&gt; 主题: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.
&gt; 
&gt; Could you provide some testcase?
 
Sorry for not giving a clear description， 
 
You can use amost all testcases in gcc.target/riscv/rvv/base/spill-*.c
 
compile with -march=rv64gcv and check the assemble file spill-*.s,
 
before this patch, it will generate assemble code contain additional
 
`addi sp,sp,0`:
 
```
        csrr    t0,vlenb
        slli    t1,t0,1
        add     sp,sp,t1
        addi    sp,sp,0
        ld      s0,24(sp)
        addi    sp,sp,32
        jr      ra
```
 
after this patch it will removed:
 
```
        csrr    t0,vlenb
        slli    t1,t0,1
        add     sp,sp,t1
        ld      s0,24(sp)
        addi    sp,sp,32
        jr      ra
```
 
&gt; 
&gt; On Tue, Nov 15, 2022 at 12:29 AM jiawei <jiawei@iscas.ac.cn> wrote:
&gt; &gt;
&gt; &gt; Skip add insn generate if the adjust size equal to zero.
&gt; &gt;
&gt; &gt; gcc/ChangeLog:
&gt; &gt;
&gt; &gt;         * config/riscv/riscv.cc (riscv_expand_epilogue):
&gt; &gt;                                 New if control segement.
&gt; &gt;
&gt; &gt; ---
&gt; &gt;  gcc/config/riscv/riscv.cc | 18 ++++++++++--------
&gt; &gt;  1 file changed, 10 insertions(+), 8 deletions(-)
&gt; &gt;
&gt; &gt; diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
&gt; &gt; index 02a01ca0b7c..af138db7545 100644
&gt; &gt; --- a/gcc/config/riscv/riscv.cc
&gt; &gt; +++ b/gcc/config/riscv/riscv.cc
&gt; &gt; @@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style)
&gt; &gt;         }
&gt; &gt;
&gt; &gt;        /* Get an rtx for STEP1 that we can add to BASE.  */
&gt; &gt; -      rtx adjust = GEN_INT (step1.to_constant ());
&gt; &gt; -      if (!SMALL_OPERAND (step1.to_constant ()))
&gt; &gt; +      if (step1.to_constant () != 0){
&gt; &gt; +        rtx adjust = GEN_INT (step1.to_constant ());
&gt; &gt; +        if (!SMALL_OPERAND (step1.to_constant ()))
&gt; &gt;         {
&gt; &gt;           riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
&gt; &gt;           adjust = RISCV_PROLOGUE_TEMP (Pmode);
&gt; &gt;         }
&gt; &gt;
&gt; &gt; -      insn = emit_insn (
&gt; &gt; +        insn = emit_insn (
&gt; &gt;                gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
&gt; &gt;
&gt; &gt; -      rtx dwarf = NULL_RTX;
&gt; &gt; -      rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
&gt; &gt; +        rtx dwarf = NULL_RTX;
&gt; &gt; +        rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
&gt; &gt;                                          GEN_INT (step2));
&gt; &gt;
&gt; &gt; -      dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
&gt; &gt; -      RTX_FRAME_RELATED_P (insn) = 1;
&gt; &gt; +        dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
&gt; &gt; +        RTX_FRAME_RELATED_P (insn) = 1;
&gt; &gt;
&gt; &gt; -      REG_NOTES (insn) = dwarf;
&gt; &gt; +        REG_NOTES (insn) = dwarf;
&gt; &gt; +      }
&gt; &gt;      }
&gt; &gt;    else if (frame_pointer_needed)
&gt; &gt;      {
&gt; &gt; --
&gt; &gt; 2.25.1
&gt; &gt;
</jiawei@iscas.ac.cn></jiawei@iscas.ac.cn></kito.cheng@gmail.com>