From: Jeff Law <jeffreyalaw@gmail.com>
To: Sergei Lewis <slewis@rivosinc.com>, gcc-patches@gcc.gnu.org
Subject: Re: [PATCH v2 1/3] RISC-V: movmem for RISCV with V extension
Date: Tue, 19 Dec 2023 22:28:50 -0700 [thread overview]
Message-ID: <5098d3c3-845f-4b71-ba8f-751b03b73240@gmail.com> (raw)
In-Reply-To: <20231219095348.356551-2-slewis@rivosinc.com>
On 12/19/23 02:53, Sergei Lewis wrote:
> gcc/ChangeLog
>
> * config/riscv/riscv.md (movmem<mode>): Use riscv_vector::expand_block_move,
> if and only if we know the entire operation can be performed using one vector
> load followed by one vector store
>
> gcc/testsuite/ChangeLog
>
> PR target/112109
> * gcc.target/riscv/rvv/base/movmem-1.c: New test
So this needs to be regression tested. Given that it only affects RVV,
I would suggest testing rv64gcv or rv32gcv.
> +(define_expand "movmem<mode>"
> + [(parallel [(set (match_operand:BLK 0 "general_operand")
> + (match_operand:BLK 1 "general_operand"))
> + (use (match_operand:P 2 "const_int_operand"))
> + (use (match_operand:SI 3 "const_int_operand"))])]
> + "TARGET_VECTOR"
> +{
> + if ((INTVAL (operands[2]) >= TARGET_MIN_VLEN/8)
> + && (INTVAL (operands[2]) <= TARGET_MIN_VLEN)
> + && riscv_vector::expand_block_move (operands[0], operands[1],
> + operands[2]))
> + DONE;
> + else
> + FAIL;
> +})
Just a formatting nit. A space on each side of the '/' operator above.
Jeff
next prev parent reply other threads:[~2023-12-20 5:28 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-19 9:53 [PATCH v2 0/3] RISC-V: vectorised memory operations Sergei Lewis
2023-12-19 9:53 ` [PATCH v2 1/3] RISC-V: movmem for RISCV with V extension Sergei Lewis
2023-12-20 5:28 ` Jeff Law [this message]
2023-12-20 9:44 ` Sergei Lewis
2024-05-13 23:36 ` Jeff Law
2023-12-19 9:53 ` [PATCH v2 2/3] RISC-V: setmem " Sergei Lewis
2023-12-20 5:38 ` Jeff Law
2023-12-20 9:48 ` Sergei Lewis
2023-12-20 16:02 ` Jeff Law
2023-12-19 9:53 ` [PATCH v2 3/3] RISC-V: cmpmem " Sergei Lewis
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