From: Sergei Lewis <slewis@rivosinc.com>
To: Jeff Law <jeffreyalaw@gmail.com>
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH v2 1/3] RISC-V: movmem for RISCV with V extension
Date: Wed, 20 Dec 2023 09:44:45 +0000 [thread overview]
Message-ID: <CAE2KcLrpsGmcizuy7L63QdvjSwOo4SJ-N9aTtPhKAOHOejzghA@mail.gmail.com> (raw)
In-Reply-To: <5098d3c3-845f-4b71-ba8f-751b03b73240@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1489 bytes --]
Hi,
this patchset has been tested with the following configurations:
rv64gcv_zvl128b
rv64gcv_zvl256b
rv32imafd_zve32x1p0
rv32gc_zve64f_zvl128b
Will fix the formatting in v3.
Thanks
On Wed, Dec 20, 2023 at 5:28 AM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
> On 12/19/23 02:53, Sergei Lewis wrote:
> > gcc/ChangeLog
> >
> > * config/riscv/riscv.md (movmem<mode>): Use
> riscv_vector::expand_block_move,
> > if and only if we know the entire operation can be performed using
> one vector
> > load followed by one vector store
> >
> > gcc/testsuite/ChangeLog
> >
> > PR target/112109
> > * gcc.target/riscv/rvv/base/movmem-1.c: New test
> So this needs to be regression tested. Given that it only affects RVV,
> I would suggest testing rv64gcv or rv32gcv.
>
>
>
> > +(define_expand "movmem<mode>"
> > + [(parallel [(set (match_operand:BLK 0 "general_operand")
> > + (match_operand:BLK 1 "general_operand"))
> > + (use (match_operand:P 2 "const_int_operand"))
> > + (use (match_operand:SI 3 "const_int_operand"))])]
> > + "TARGET_VECTOR"
> > +{
> > + if ((INTVAL (operands[2]) >= TARGET_MIN_VLEN/8)
> > + && (INTVAL (operands[2]) <= TARGET_MIN_VLEN)
> > + && riscv_vector::expand_block_move (operands[0], operands[1],
> > + operands[2]))
> > + DONE;
> > + else
> > + FAIL;
> > +})
> Just a formatting nit. A space on each side of the '/' operator above.
>
>
> Jeff
>
next prev parent reply other threads:[~2023-12-20 9:44 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-19 9:53 [PATCH v2 0/3] RISC-V: vectorised memory operations Sergei Lewis
2023-12-19 9:53 ` [PATCH v2 1/3] RISC-V: movmem for RISCV with V extension Sergei Lewis
2023-12-20 5:28 ` Jeff Law
2023-12-20 9:44 ` Sergei Lewis [this message]
2024-05-13 23:36 ` Jeff Law
2023-12-19 9:53 ` [PATCH v2 2/3] RISC-V: setmem " Sergei Lewis
2023-12-20 5:38 ` Jeff Law
2023-12-20 9:48 ` Sergei Lewis
2023-12-20 16:02 ` Jeff Law
2023-12-19 9:53 ` [PATCH v2 3/3] RISC-V: cmpmem " Sergei Lewis
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