From: will schmidt <will_schmidt@vnet.ibm.com>
To: Segher Boessenkool <segher@kernel.crashing.org>,
David Edelsohn <dje.gcc@gmail.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>,
Will Schmidt <will_schmidt@vnet.ibm.com>
Subject: Re: [PATCH, rs6000] Clean up the option_mask defines (part 2)
Date: Wed, 25 May 2022 15:29:29 -0500 [thread overview]
Message-ID: <7358d46022bb9da997c77c910a6c2b86518d3401.camel@vnet.ibm.com> (raw)
In-Reply-To: <6591013b62270c39c912f0c13c4cd12ffbaf75a2.camel@vnet.ibm.com>
[PATCH, rs6000] Clean up the option_mask defines (part 2)
Hi,
This patch reworks most of the lingering MASK_*
values to OPTION_MASK_* and removes the now redundant defines.
Regtested OK on power10. OK for trunk?
gcc/
* rs6000.h (RS6000_BTM_VSX, RS6000_BTM_P8_VECTOR, RS6000_BTM_P9_VECTOR,
RS6000_BTM_P9_MISC, RS6000_BTM_HTM, RS6000_BTM_POPCNTD,
RS6000_BTM_DFP, RS6000_BTM_HARD_FLOAT, RS6000_BTM_LDBL128,
RS6000_BTM_FLOAT128, RS6000_BTM_FLOAT128_HW, RS6000_BTM_MMA,
RS6000_BTM_P10): Rework defines to use OPTION_MASK_<xxxx>.
(MASK_DFP, MASK_DIRECT_MOVE, MASK_FLOAT128_KEYWORD,
MASK_FLOAT128_HW, MASK_P8_FUSION, MASK_HARD_FLOAT, MASK_HTM,
MASK_MMA, MASK_MULTIPLE, MASK_NO_UPDATE, MASK_P8_VECTOR,
MASK_P9_VECTOR, MASK_P9_MISC, MASK_POPCNTD, MASK_RECIP_PRECISION,
MASK_SOFT_FLOAT, MASK_UPDATE, MASK_VSX, MASK_POWER10,
MASK_P10_FUSION): Remove unused defines.
* config/rs6000/rs6000-cpus.def (RS6000_CPU): Rework macro calls to
use OPTION_MASK_<xxxx> defines.
* config/rs6000/darwin.h (TARGET_DEFAULT) Update define to use
OPTION_MASK_MULTIPLE.
* config/rs6000/darwin64-biarch.h (TARGET_DEFAULT): Same.
diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h
index 86556ccbbf58..6a8845eb3bb7 100644
--- a/gcc/config/rs6000/darwin.h
+++ b/gcc/config/rs6000/darwin.h
@@ -365,11 +365,11 @@
/* Default target flag settings. Despite the fact that STMW/LMW
serializes, it's still a big code size win to use them. Use FSEL by
default as well. */
#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT)
+#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT)
/* Darwin always uses IBM long double, never IEEE long double. */
#undef TARGET_IEEEQUAD
#define TARGET_IEEEQUAD 0
diff --git a/gcc/config/rs6000/darwin64-biarch.h b/gcc/config/rs6000/darwin64-biarch.h
index 6a700c61c4c2..6515bcc8bf5a 100644
--- a/gcc/config/rs6000/darwin64-biarch.h
+++ b/gcc/config/rs6000/darwin64-biarch.h
@@ -19,11 +19,11 @@
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \
- | MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT)
+ | OPTION_MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT)
#undef DARWIN_ARCH_SPEC
#define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}"
/* Actually, there's really only 970 as an active option. */
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index ca78bd8cf89f..4301b1bcb120 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -174,29 +174,31 @@
RS6000_CPU (NAME, CPU, FLAGS)
where the arguments are the fields of struct rs6000_ptt. */
-RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
-RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
-RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | OPTION_MASK_MULHW
- | OPTION_MASK_DLMZB)
+RS6000_CPU ("401", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT)
+RS6000_CPU ("403", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
+RS6000_CPU ("405", PROCESSOR_PPC405, OPTION_MASK_SOFT_FLOAT
+ | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("405fp", PROCESSOR_PPC405, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
-RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | OPTION_MASK_MULHW
+RS6000_CPU ("440", PROCESSOR_PPC440, OPTION_MASK_SOFT_FLOAT | OPTION_MASK_MULHW
| OPTION_MASK_DLMZB)
RS6000_CPU ("440fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
-RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | OPTION_MASK_MULHW
+RS6000_CPU ("464", PROCESSOR_PPC440, OPTION_MASK_SOFT_FLOAT | OPTION_MASK_MULHW
| OPTION_MASK_DLMZB)
RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
-RS6000_CPU ("476", PROCESSOR_PPC476, MASK_SOFT_FLOAT | OPTION_MASK_PPC_GFXOPT
- | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND
- | OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
-RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT
- | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND
- | OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
+RS6000_CPU ("476", PROCESSOR_PPC476,
+ OPTION_MASK_SOFT_FLOAT | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF
+ | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND | OPTION_MASK_CMPB
+ | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
+RS6000_CPU ("476fp", PROCESSOR_PPC476,
+ OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
+ | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW
+ | OPTION_MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
-RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE)
+RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE)
RS6000_CPU ("602", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("603", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("603e", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("604", PROCESSOR_PPC604, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("604e", PROCESSOR_PPC604e, OPTION_MASK_PPC_GFXOPT)
@@ -204,35 +206,34 @@ RS6000_CPU ("620", PROCESSOR_PPC620, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("630", PROCESSOR_PPC630, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("740", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("750", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT)
-RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
-RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
-RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
+RS6000_CPU ("801", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
+RS6000_CPU ("821", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
+RS6000_CPU ("823", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | OPTION_MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | OPTION_MASK_ISEL)
RS6000_CPU ("a2", PROCESSOR_PPCA2, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64
- | OPTION_MASK_POPCNTB | OPTION_MASK_CMPB | MASK_NO_UPDATE)
-RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
+ | OPTION_MASK_POPCNTB | OPTION_MASK_CMPB | OPTION_MASK_NO_UPDATE)
+RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, OPTION_MASK_PPC_GFXOPT
| OPTION_MASK_ISEL)
RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
MASK_POWERPC64 | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL)
RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
MASK_POWERPC64 | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL)
RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
| OPTION_MASK_MFCRF | OPTION_MASK_ISEL)
-RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
-RS6000_CPU ("970", PROCESSOR_POWER4,
- POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF
- | MASK_POWERPC64)
+RS6000_CPU ("860", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
+RS6000_CPU ("970", PROCESSOR_POWER4, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT
+ | OPTION_MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("cell", PROCESSOR_CELL,
- POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF
- | MASK_POWERPC64)
-RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
+ POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF
+ | MASK_POWERPC64)
+RS6000_CPU ("ec603e", PROCESSOR_PPC603, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("G3", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("G5", PROCESSOR_POWER4, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("titan", PROCESSOR_TITAN, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
@@ -245,16 +246,16 @@ RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
| OPTION_MASK_FPRND)
RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
- | OPTION_MASK_FPRND | OPTION_MASK_CMPB | MASK_DFP
- | MASK_RECIP_PRECISION)
+ | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP
+ | OPTION_MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
- | OPTION_MASK_FPRND | OPTION_MASK_CMPB | MASK_DFP
- | MASK_RECIP_PRECISION)
+ | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP
+ | OPTION_MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
| OPTION_MASK_HTM)
RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER
| OPTION_MASK_HTM)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ef7f10e4efee..dcf632c1f1ad 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -505,31 +505,11 @@ extern int rs6000_vector_align[];
&& (TARGET_P9_MINMAX || !flag_trapping_math))
/* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
OPTION_MASK_<xxx> back into MASK_<xxx>. */
-#define MASK_DFP OPTION_MASK_DFP
-#define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
-#define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD
-#define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW
-#define MASK_P8_FUSION OPTION_MASK_P8_FUSION
-#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
-#define MASK_HTM OPTION_MASK_HTM
-#define MASK_MMA OPTION_MASK_MMA
-#define MASK_MULTIPLE OPTION_MASK_MULTIPLE
-#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
-#define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
-#define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR
-#define MASK_P9_MISC OPTION_MASK_P9_MISC
-#define MASK_POPCNTD OPTION_MASK_POPCNTD
-#define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
-#define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
#define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
-#define MASK_UPDATE OPTION_MASK_UPDATE
-#define MASK_VSX OPTION_MASK_VSX
-#define MASK_POWER10 OPTION_MASK_POWER10
-#define MASK_P10_FUSION OPTION_MASK_P10_FUSION
#ifndef IN_LIBGCC2
#define MASK_POWERPC64 OPTION_MASK_POWERPC64
#endif
@@ -2241,31 +2221,31 @@ extern int frame_pointer_needed;
target flags, and pick a random bit for ldbl128, which isn't in
target_flags. */
#define RS6000_BTM_ALWAYS 0 /* Always enabled. */
#define RS6000_BTM_ALTIVEC OPTION_MASK_ALTIVEC /* VMX/altivec vectors. */
#define RS6000_BTM_CMPB OPTION_MASK_CMPB /* ISA 2.05: compare bytes. */
-#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
-#define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
-#define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */
-#define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */
+#define RS6000_BTM_VSX OPTION_MASK_VSX /* VSX (vector/scalar). */
+#define RS6000_BTM_P8_VECTOR OPTION_MASK_P8_VECTOR /* ISA 2.07 vector. */
+#define RS6000_BTM_P9_VECTOR OPTION_MASK_P9_VECTOR /* ISA 3.0 vector. */
+#define RS6000_BTM_P9_MISC OPTION_MASK_P9_MISC /* ISA 3.0 misc. non-vector */
#define RS6000_BTM_CRYPTO OPTION_MASK_CRYPTO /* crypto funcs. */
-#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
+#define RS6000_BTM_HTM OPTION_MASK_HTM /* hardware TM funcs. */
#define RS6000_BTM_FRE OPTION_MASK_POPCNTB /* FRE instruction. */
#define RS6000_BTM_FRES OPTION_MASK_PPC_GFXOPT /* FRES instruction. */
#define RS6000_BTM_FRSQRTE OPTION_MASK_PPC_GFXOPT /* FRSQRTE instruction. */
#define RS6000_BTM_FRSQRTES OPTION_MASK_POPCNTB /* FRSQRTES instruction. */
-#define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */
+#define RS6000_BTM_POPCNTD OPTION_MASK_POPCNTD /* Target supports ISA 2.06. */
#define RS6000_BTM_CELL OPTION_MASK_FPRND /* Target is cell powerpc. */
-#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
-#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
-#define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
+#define RS6000_BTM_DFP OPTION_MASK_DFP /* Decimal floating point. */
+#define RS6000_BTM_HARD_FLOAT OPTION_MASK_SOFT_FLOAT /* Hardware floating point. */
+#define RS6000_BTM_LDBL128 OPTION_MASK_MULTIPLE /* 128-bit long double. */
#define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
#define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */
-#define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */
-#define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */
-#define RS6000_BTM_MMA MASK_MMA /* ISA 3.1 MMA. */
-#define RS6000_BTM_P10 MASK_POWER10
+#define RS6000_BTM_FLOAT128 OPTION_MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */
+#define RS6000_BTM_FLOAT128_HW OPTION_MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */
+#define RS6000_BTM_MMA OPTION_MASK_MMA /* ISA 3.1 MMA. */
+#define RS6000_BTM_P10 OPTION_MASK_POWER10
#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
| RS6000_BTM_VSX \
| RS6000_BTM_P8_VECTOR \
| RS6000_BTM_P9_VECTOR \
next prev parent reply other threads:[~2022-05-25 20:29 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-25 20:25 [PATCH, rs6000] Clean up the option_mask defines (part 1) will schmidt
2022-05-25 20:29 ` will schmidt [this message]
2022-05-25 20:30 ` [PATCH, rs6000] Clean up the option_mask defines (part 3) will schmidt
2022-05-26 6:12 ` [PATCH, rs6000] Clean up the option_mask defines (part 1) Kewen.Lin
2022-05-26 7:01 ` Kewen.Lin
2022-05-26 10:47 ` Segher Boessenkool
2022-05-26 14:40 ` will schmidt
2022-05-26 18:31 ` Segher Boessenkool
2022-05-26 19:38 ` will schmidt
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