Re: [PATCH, rs6000] Clean up the option_mask defines (part 1)

["Kewen.Lin" <linkw@linux.ibm.com>]

on 2022/5/26 14:12, Kewen.Lin via Gcc-patches wrote:
> Hi Will,
> 
> on 2022/5/26 04:25, will schmidt via Gcc-patches wrote:
>> [PATCH, rs6000] Clean up the option_mask defines
>>     
>> Hi,
>>
>> We have an assortment of MASK and OPTION_MASK #defines throughout
>> the rs6000 code, MASK_ALTIVEC and OPTION_MASK_ALTIVEC as an example.
>>
>> We currently #define the MASK_<xxxx> entries to their OPTION_MASK_<xxxx>
>> equivalents so the two names could be used interchangeably.
>>
>> The mapping is in place from when we switched from using
>> target_flags to rs6000_isa_flags via
>> commit 4d9675496a28ef6184f2a9c3ac5e6e3ea63606c1 in 2012.
>>
>> This patch converts the references for most of the lingering MASK_*
>> values to OPTION_MASK_*  and removes the now redundant defines.
>>
> 
> Nice, thanks for the cleanup!
> 
>> I have split this into multiple parts due to size.
>>
> 
> I guess they can be bootstrapped & regressed incrementally?
> 
> I found there are still some masks left:
> 
> MASK_POWERPC64, MASK_64BIT and MASK_LITTLE_ENDIAN.
> 
> Is there one part 4 for them?  Or is there some particular reason
> not to clean up them?
> 

aha, I see.  Those three are conditional definitions, I agree it's better
to leave them alone. :)


>> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
>> index d4defc855d02..200bef3f822e 100644
>> --- a/gcc/config/rs6000/rs6000.cc
>> +++ b/gcc/config/rs6000/rs6000.cc
>> @@ -20727,15 +20727,15 @@ rs6000_darwin_file_start (void)
>>      const char *arg;
>>      const char *name;
>>      HOST_WIDE_INT if_set;
>>    } mapping[] = {
>>      { "ppc64", "ppc64", MASK_64BIT },
>> -    { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
>> +    { "970", "ppc970", OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF | MASK_POWERPC64 },

Nit: This line is too long.

>>      { "power4", "ppc970", 0 },
>>      { "G5", "ppc970", 0 },
>>      { "7450", "ppc7450", 0 },
>> -    { "7400", "ppc7400", MASK_ALTIVEC },
>> +    { "7400", "ppc7400", OPTION_MASK_ALTIVEC },
>>      { "G4", "ppc7400", 0 },
>>      { "750", "ppc750", 0 },
>>      { "740", "ppc750", 0 },
>>      { "G3", "ppc750", 0 },
>>      { "604e", "ppc604e", 0 },
...
>>  /* Builtin targets.  For now, we reuse the masks for those options that are in
>>     target flags, and pick a random bit for ldbl128, which isn't in
>>     target_flags.  */

Nit: Some of these BTM lines below exceed 80 characters, a few already existed
previously.

>>  #define RS6000_BTM_ALWAYS	0		/* Always enabled.  */
>> -#define RS6000_BTM_ALTIVEC	MASK_ALTIVEC	/* VMX/altivec vectors.  */
>> -#define RS6000_BTM_CMPB		MASK_CMPB	/* ISA 2.05: compare bytes.  */
>> +#define RS6000_BTM_ALTIVEC	OPTION_MASK_ALTIVEC	/* VMX/altivec vectors.  */
>> +#define RS6000_BTM_CMPB		OPTION_MASK_CMPB	/* ISA 2.05: compare bytes.  */
>>  #define RS6000_BTM_VSX		MASK_VSX	/* VSX (vector/scalar).  */
>>  #define RS6000_BTM_P8_VECTOR	MASK_P8_VECTOR	/* ISA 2.07 vector.  */
>>  #define RS6000_BTM_P9_VECTOR	MASK_P9_VECTOR	/* ISA 3.0 vector.  */
>>  #define RS6000_BTM_P9_MISC	MASK_P9_MISC	/* ISA 3.0 misc. non-vector */
>> -#define RS6000_BTM_CRYPTO	MASK_CRYPTO	/* crypto funcs.  */
>> +#define RS6000_BTM_CRYPTO	OPTION_MASK_CRYPTO	/* crypto funcs.  */
>>  #define RS6000_BTM_HTM		MASK_HTM	/* hardware TM funcs.  */
>> -#define RS6000_BTM_FRE		MASK_POPCNTB	/* FRE instruction.  */
>> -#define RS6000_BTM_FRES		MASK_PPC_GFXOPT	/* FRES instruction.  */
>> -#define RS6000_BTM_FRSQRTE	MASK_PPC_GFXOPT	/* FRSQRTE instruction.  */
>> -#define RS6000_BTM_FRSQRTES	MASK_POPCNTB	/* FRSQRTES instruction.  */
>> +#define RS6000_BTM_FRE		OPTION_MASK_POPCNTB	/* FRE instruction.  */
>> +#define RS6000_BTM_FRES		OPTION_MASK_PPC_GFXOPT	/* FRES instruction.  */
>> +#define RS6000_BTM_FRSQRTE	OPTION_MASK_PPC_GFXOPT	/* FRSQRTE instruction.  */
>> +#define RS6000_BTM_FRSQRTES	OPTION_MASK_POPCNTB	/* FRSQRTES instruction.  */
>>  #define RS6000_BTM_POPCNTD	MASK_POPCNTD	/* Target supports ISA 2.06.  */
>> -#define RS6000_BTM_CELL		MASK_FPRND	/* Target is cell powerpc.  */
>> +#define RS6000_BTM_CELL		OPTION_MASK_FPRND	/* Target is cell powerpc.  */
>>  #define RS6000_BTM_DFP		MASK_DFP	/* Decimal floating point.  */
>>  #define RS6000_BTM_HARD_FLOAT	MASK_SOFT_FLOAT	/* Hardware floating point.  */
>>  #define RS6000_BTM_LDBL128	MASK_MULTIPLE	/* 128-bit long double.  */
>>  #define RS6000_BTM_64BIT	MASK_64BIT	/* 64-bit addressing.  */
>>  #define RS6000_BTM_POWERPC64	MASK_POWERPC64	/* 64-bit registers.  */


BR,
Kewen

BR,
Kewen