* [PATCH 0/5] LoongArch: Initial LA664 support
@ 2023-11-16 13:18 Xi Ruoyao
2023-11-16 13:18 ` [PATCH 1/5] LoongArch: Switch loongarch-def to C++ Xi Ruoyao
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Xi Ruoyao @ 2023-11-16 13:18 UTC (permalink / raw)
To: gcc-patches; +Cc: chenglulu, i, xuchenghua, Xi Ruoyao
Loongson 3A6000 processor will be shipped to general users in this month
and it features 4 cores with the new LA664 micro architecture. Here is
some changes from LA464:
1. The 32-bit division instruction now ignores the high 32 bits of the
input registers. This is enumerated via CPUCFG word 0x2, bit 26.
2. The micro architecture now guarantees two loads on the same memory
address won't be reordered with each other. dbar 0x700 is turned
into nop.
3. The architecture now supports approximate square root instructions
(FRECIPE and VRSQRTE) on 32-bit or 64-bit floating-point values and
the vectors of these values.
4. The architecture now supports SC.Q instruction for 128-bit CAS.
5. The architecture now supports LL.ACQ and SC.REL instructions (well, I
don't really know what they are for).
6. The architecture now supports CAS instructions for 64, 32, 16, or 8-bit
values.
7. The architecture now supports atomic add and atomic swap instructions
for 16 or 8-bit values.
8. Some non-zero hint values of DBAR instructions are added.
These features are documented in LoongArch v1.1. Implementations can
implement any subset of them and enumerate the implemented features via
CPUCFG. LA664 implements them all.
(8) is already implemented in previous patches because it's completely
backward-compatible. This series implements (1) and (2) with switches
-mdiv32 and -mld-seq-sa (these names are derived from the names of the
corresponding CPUCFG bits documented in the LoongArch v1.1
specification).
The other features require Binutils support and we are close to the end
of GCC 14 stage 1, so I'm posting this series first now.
With -march=la664, these two options are implicitly enabled but they can
be turned off with -mno-div32 or -mno-ld-seq-sa.
With -march=native, the current CPU is probed via CPUCFG and these
options are implicitly enabled if the CPU supports the corresponding
feature. They can be turned off with explicit -mno-div32 or
-mno-ld-seq-sa as well.
-mtune=la664 is implemented as a copy of -mtune=la464 and we can adjust
it with benchmark results later.
Bootstrapped and regtested on a LA664 with BOOT_CFLAGS="-march=la664
-O2", a LA464 with BOOT_CFLAGS="-march=native -O2". And manually
verified -march=native probing on LA664 and LA464.
Xi Ruoyao (5):
LoongArch: Switch loongarch-def to C++
LoongArch: genopts: Add infrastructure to generate code for new
features in ISA evolution
LoongArch: Take the advantage of -mdiv32 if it's enabled
LoongArch: Don't emit dbar 0x700 if -mld-seq-sa
LoongArch: Add -march=la664 and -mtune=la664
gcc/config/loongarch/genopts/genstr.sh | 78 ++++++-
gcc/config/loongarch/genopts/isa-evolution.in | 2 +
.../loongarch/genopts/loongarch-strings | 1 +
gcc/config/loongarch/genopts/loongarch.opt.in | 10 +
gcc/config/loongarch/loongarch-cpu.cc | 37 ++--
gcc/config/loongarch/loongarch-cpucfg-map.h | 36 +++
gcc/config/loongarch/loongarch-def-array.h | 40 ++++
gcc/config/loongarch/loongarch-def.c | 205 ------------------
gcc/config/loongarch/loongarch-def.cc | 193 +++++++++++++++++
gcc/config/loongarch/loongarch-def.h | 67 ++++--
gcc/config/loongarch/loongarch-opts.h | 9 +-
gcc/config/loongarch/loongarch-str.h | 8 +-
gcc/config/loongarch/loongarch-tune.h | 123 ++++++++++-
gcc/config/loongarch/loongarch.cc | 6 +-
gcc/config/loongarch/loongarch.md | 31 ++-
gcc/config/loongarch/loongarch.opt | 23 +-
gcc/config/loongarch/t-loongarch | 25 ++-
.../gcc.target/loongarch/div-div32.c | 31 +++
.../gcc.target/loongarch/div-no-div32.c | 11 +
19 files changed, 664 insertions(+), 272 deletions(-)
create mode 100644 gcc/config/loongarch/genopts/isa-evolution.in
create mode 100644 gcc/config/loongarch/loongarch-cpucfg-map.h
create mode 100644 gcc/config/loongarch/loongarch-def-array.h
delete mode 100644 gcc/config/loongarch/loongarch-def.c
create mode 100644 gcc/config/loongarch/loongarch-def.cc
create mode 100644 gcc/testsuite/gcc.target/loongarch/div-div32.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/div-no-div32.c
--
2.42.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/5] LoongArch: Switch loongarch-def to C++
2023-11-16 13:18 [PATCH 0/5] LoongArch: Initial LA664 support Xi Ruoyao
@ 2023-11-16 13:18 ` Xi Ruoyao
2023-11-16 13:18 ` [PATCH 2/5] LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution Xi Ruoyao
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Xi Ruoyao @ 2023-11-16 13:18 UTC (permalink / raw)
To: gcc-patches; +Cc: chenglulu, i, xuchenghua, Xi Ruoyao
We'll use HOST_WIDE_INT in LoongArch static properties in following
patches. Switch loongarch-def from C to C++ to make it possible.
To keep the same readability as C99 designated initializers, create a
std::array like data structure with position setter function, and add
field setter functions for structs used in loongarch-def.cc.
gcc/ChangeLog:
* config/loongarch/loongarch-def-array.h: New file for a
std::array like data structure with position setter function.
* config/loongarch/loongarch-def.h: Remove extern "C".
(loongarch_isa_base_strings): Declare as loongarch_def_array
instead of plain array.
(loongarch_isa_ext_strings): Likewise.
(loongarch_abi_base_strings): Likewise.
(loongarch_abi_ext_strings): Likewise.
(loongarch_cmodel_strings): Likewise.
(loongarch_cpu_strings): Likewise.
(loongarch_cpu_default_isa): Likewise.
(loongarch_cpu_issue_rate): Likewise.
(loongarch_cpu_multipass_dfa_lookahead): Likewise.
(loongarch_cpu_cache): Likewise.
(loongarch_cpu_align): Likewise.
(loongarch_cpu_rtx_cost_data): Likewise.
(loongarch_isa): Add a constructor and field setter functions.
* config/loongarch/loongarch-opts.h (loongarch-defs.h): Do not
include for target libraries.
* config/loongarch/loongarch-tune.h (loongarch_rtx_cost_data):
Likewise.
(loongarch_cache): Likewise.
(loongarch_align): Likewise.
* config/loongarch/loongarch-def.c: Rename to ...
* config/loongarch/loongarch-def.cc: ... here.
(loongarch_cpu_strings): Define as loongarch_def_array instead
of plain array.
(loongarch_cpu_default_isa): Likewise.
(loongarch_cpu_cache): Likewise.
(loongarch_cpu_align): Likewise.
(loongarch_cpu_rtx_cost_data): Likewise.
(loongarch_cpu_issue_rate): Likewise.
(loongarch_cpu_multipass_dfa_lookahead): Likewise.
(loongarch_isa_base_strings): Likewise.
(loongarch_isa_ext_strings): Likewise.
(loongarch_abi_base_strings): Likewise.
(loongarch_abi_ext_strings): Likewise.
(loongarch_cmodel_strings): Likewise.
(abi_minimal_isa): Likewise.
(loongarch_rtx_cost_optimize_size): Use field setter functions
instead of designated initializers.
(loongarch_rtx_cost_data): Implement default constructor.
* config/loongarch/t-loongarch: Compile loongarch-def.cc with
the C++ compiler.
---
gcc/config/loongarch/loongarch-def-array.h | 40 ++++
gcc/config/loongarch/loongarch-def.c | 205 ---------------------
gcc/config/loongarch/loongarch-def.cc | 176 ++++++++++++++++++
gcc/config/loongarch/loongarch-def.h | 53 +++---
gcc/config/loongarch/loongarch-opts.h | 3 +
gcc/config/loongarch/loongarch-tune.h | 123 ++++++++++++-
gcc/config/loongarch/t-loongarch | 4 +-
7 files changed, 371 insertions(+), 233 deletions(-)
create mode 100644 gcc/config/loongarch/loongarch-def-array.h
delete mode 100644 gcc/config/loongarch/loongarch-def.c
create mode 100644 gcc/config/loongarch/loongarch-def.cc
diff --git a/gcc/config/loongarch/loongarch-def-array.h b/gcc/config/loongarch/loongarch-def-array.h
new file mode 100644
index 00000000000..bdb3e9c6a2b
--- /dev/null
+++ b/gcc/config/loongarch/loongarch-def-array.h
@@ -0,0 +1,40 @@
+/* A std::array like data structure for LoongArch static properties.
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#ifndef _LOONGARCH_DEF_ARRAY_H
+#define _LOONGARCH_DEF_ARRAY_H 1
+
+template <class T, int N>
+class loongarch_def_array {
+private:
+ T arr[N];
+public:
+ loongarch_def_array () : arr{} {}
+
+ T &operator[] (int n) { return arr[n]; }
+ const T &operator[] (int n) const { return arr[n]; }
+
+ loongarch_def_array set (int idx, T &&value)
+ {
+ (*this)[idx] = value;
+ return *this;
+ }
+};
+
+#endif
diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c
deleted file mode 100644
index 430ef8b2d95..00000000000
--- a/gcc/config/loongarch/loongarch-def.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* LoongArch static properties.
- Copyright (C) 2021-2023 Free Software Foundation, Inc.
- Contributed by Loongson Ltd.
-
-This file is part of GCC.
-
-GCC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3, or (at your option)
-any later version.
-
-GCC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GCC; see the file COPYING3. If not see
-<http://www.gnu.org/licenses/>. */
-
-#include "loongarch-def.h"
-#include "loongarch-str.h"
-
-/* CPU property tables. */
-const char*
-loongarch_cpu_strings[N_TUNE_TYPES] = {
- [CPU_NATIVE] = STR_CPU_NATIVE,
- [CPU_ABI_DEFAULT] = STR_CPU_ABI_DEFAULT,
- [CPU_LOONGARCH64] = STR_CPU_LOONGARCH64,
- [CPU_LA464] = STR_CPU_LA464,
-};
-
-struct loongarch_isa
-loongarch_cpu_default_isa[N_ARCH_TYPES] = {
- [CPU_LOONGARCH64] = {
- .base = ISA_BASE_LA64V100,
- .fpu = ISA_EXT_FPU64,
- .simd = 0,
- },
- [CPU_LA464] = {
- .base = ISA_BASE_LA64V100,
- .fpu = ISA_EXT_FPU64,
- .simd = ISA_EXT_SIMD_LASX,
- },
-};
-
-struct loongarch_cache
-loongarch_cpu_cache[N_TUNE_TYPES] = {
- [CPU_LOONGARCH64] = {
- .l1d_line_size = 64,
- .l1d_size = 64,
- .l2d_size = 256,
- .simultaneous_prefetches = 4,
- },
- [CPU_LA464] = {
- .l1d_line_size = 64,
- .l1d_size = 64,
- .l2d_size = 256,
- .simultaneous_prefetches = 4,
- },
-};
-
-struct loongarch_align
-loongarch_cpu_align[N_TUNE_TYPES] = {
- [CPU_LOONGARCH64] = {
- .function = "32",
- .label = "16",
- },
- [CPU_LA464] = {
- .function = "32",
- .label = "16",
- },
-};
-
-
-/* Default RTX cost initializer. */
-#define COSTS_N_INSNS(N) ((N) * 4)
-#define DEFAULT_COSTS \
- .fp_add = COSTS_N_INSNS (1), \
- .fp_mult_sf = COSTS_N_INSNS (2), \
- .fp_mult_df = COSTS_N_INSNS (4), \
- .fp_div_sf = COSTS_N_INSNS (6), \
- .fp_div_df = COSTS_N_INSNS (8), \
- .int_mult_si = COSTS_N_INSNS (1), \
- .int_mult_di = COSTS_N_INSNS (1), \
- .int_div_si = COSTS_N_INSNS (4), \
- .int_div_di = COSTS_N_INSNS (6), \
- .branch_cost = 6, \
- .memory_latency = 4
-
-/* The following properties cannot be looked up directly using "cpucfg".
- So it is necessary to provide a default value for "unknown native"
- tune targets (i.e. -mtune=native while PRID does not correspond to
- any known "-mtune" type). */
-
-struct loongarch_rtx_cost_data
-loongarch_cpu_rtx_cost_data[N_TUNE_TYPES] = {
- [CPU_NATIVE] = {
- DEFAULT_COSTS
- },
- [CPU_LOONGARCH64] = {
- DEFAULT_COSTS
- },
- [CPU_LA464] = {
- DEFAULT_COSTS
- },
-};
-
-/* RTX costs to use when optimizing for size. */
-const struct loongarch_rtx_cost_data
-loongarch_rtx_cost_optimize_size = {
- .fp_add = 4,
- .fp_mult_sf = 4,
- .fp_mult_df = 4,
- .fp_div_sf = 4,
- .fp_div_df = 4,
- .int_mult_si = 4,
- .int_mult_di = 4,
- .int_div_si = 4,
- .int_div_di = 4,
- .branch_cost = 6,
- .memory_latency = 4,
-};
-
-int
-loongarch_cpu_issue_rate[N_TUNE_TYPES] = {
- [CPU_NATIVE] = 4,
- [CPU_LOONGARCH64] = 4,
- [CPU_LA464] = 4,
-};
-
-int
-loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = {
- [CPU_NATIVE] = 4,
- [CPU_LOONGARCH64] = 4,
- [CPU_LA464] = 4,
-};
-
-/* Wiring string definitions from loongarch-str.h to global arrays
- with standard index values from loongarch-opts.h, so we can
- print config-related messages and do ABI self-spec filtering
- from the driver in a self-consistent manner. */
-
-const char*
-loongarch_isa_base_strings[N_ISA_BASE_TYPES] = {
- [ISA_BASE_LA64V100] = STR_ISA_BASE_LA64V100,
-};
-
-const char*
-loongarch_isa_ext_strings[N_ISA_EXT_TYPES] = {
- [ISA_EXT_NONE] = STR_NONE,
- [ISA_EXT_FPU32] = STR_ISA_EXT_FPU32,
- [ISA_EXT_FPU64] = STR_ISA_EXT_FPU64,
- [ISA_EXT_SIMD_LSX] = STR_ISA_EXT_LSX,
- [ISA_EXT_SIMD_LASX] = STR_ISA_EXT_LASX,
-};
-
-const char*
-loongarch_abi_base_strings[N_ABI_BASE_TYPES] = {
- [ABI_BASE_LP64D] = STR_ABI_BASE_LP64D,
- [ABI_BASE_LP64F] = STR_ABI_BASE_LP64F,
- [ABI_BASE_LP64S] = STR_ABI_BASE_LP64S,
-};
-
-const char*
-loongarch_abi_ext_strings[N_ABI_EXT_TYPES] = {
- [ABI_EXT_BASE] = STR_ABI_EXT_BASE,
-};
-
-const char*
-loongarch_cmodel_strings[] = {
- [CMODEL_NORMAL] = STR_CMODEL_NORMAL,
- [CMODEL_TINY] = STR_CMODEL_TINY,
- [CMODEL_TINY_STATIC] = STR_CMODEL_TS,
- [CMODEL_MEDIUM] = STR_CMODEL_MEDIUM,
- [CMODEL_LARGE] = STR_CMODEL_LARGE,
- [CMODEL_EXTREME] = STR_CMODEL_EXTREME,
-};
-
-
-/* ABI-related definitions. */
-const struct loongarch_isa
-abi_minimal_isa[N_ABI_BASE_TYPES][N_ABI_EXT_TYPES] = {
- [ABI_BASE_LP64D] = {
- [ABI_EXT_BASE] = {
- .base = ISA_BASE_LA64V100,
- .fpu = ISA_EXT_FPU64,
- .simd = 0
- },
- },
- [ABI_BASE_LP64F] = {
- [ABI_EXT_BASE] = {
- .base = ISA_BASE_LA64V100,
- .fpu = ISA_EXT_FPU32,
- .simd = 0
- },
- },
- [ABI_BASE_LP64S] = {
- [ABI_EXT_BASE] = {
- .base = ISA_BASE_LA64V100,
- .fpu = ISA_EXT_NONE,
- .simd = 0
- },
- },
-};
diff --git a/gcc/config/loongarch/loongarch-def.cc b/gcc/config/loongarch/loongarch-def.cc
new file mode 100644
index 00000000000..0200c48f43b
--- /dev/null
+++ b/gcc/config/loongarch/loongarch-def.cc
@@ -0,0 +1,176 @@
+/* LoongArch static properties.
+ Copyright (C) 2021-2023 Free Software Foundation, Inc.
+ Contributed by Loongson Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#include "loongarch-def.h"
+#include "loongarch-str.h"
+
+template <class T, int N>
+using array = loongarch_def_array<T, N>;
+
+template <class T>
+using array_tune = array<T, N_TUNE_TYPES>;
+
+template <class T>
+using array_arch = array<T, N_ARCH_TYPES>;
+
+/* CPU property tables. */
+array_tune<const char *> loongarch_cpu_strings = array_tune<const char *> ()
+ .set (CPU_NATIVE, STR_CPU_NATIVE)
+ .set (CPU_ABI_DEFAULT, STR_CPU_ABI_DEFAULT)
+ .set (CPU_LOONGARCH64, STR_CPU_LOONGARCH64)
+ .set (CPU_LA464, STR_CPU_LA464);
+
+array_arch<loongarch_isa> loongarch_cpu_default_isa =
+ array_arch<loongarch_isa> ()
+ .set (CPU_LOONGARCH64,
+ loongarch_isa ()
+ .base_ (ISA_BASE_LA64V100)
+ .fpu_ (ISA_EXT_FPU64))
+ .set (CPU_LA464,
+ loongarch_isa ()
+ .base_ (ISA_BASE_LA64V100)
+ .fpu_ (ISA_EXT_FPU64)
+ .simd_ (ISA_EXT_SIMD_LASX));
+
+static inline loongarch_cache la464_cache ()
+{
+ return loongarch_cache ()
+ .l1d_line_size_ (64)
+ .l1d_size_ (64)
+ .l2d_size_ (256)
+ .simultaneous_prefetches_ (4);
+}
+
+array_tune<loongarch_cache> loongarch_cpu_cache =
+ array_tune<loongarch_cache> ()
+ .set (CPU_LOONGARCH64, la464_cache ())
+ .set (CPU_LA464, la464_cache ());
+
+static inline loongarch_align la464_align ()
+{
+ return loongarch_align ().function_ ("32").label_ ("16");
+}
+
+array_tune<loongarch_align> loongarch_cpu_align =
+ array_tune<loongarch_align> ()
+ .set (CPU_LOONGARCH64, la464_align ())
+ .set (CPU_LA464, la464_align ());
+
+#define COSTS_N_INSNS(N) ((N) * 4)
+
+/* Default RTX cost initializer. */
+loongarch_rtx_cost_data::loongarch_rtx_cost_data ()
+ : fp_add (COSTS_N_INSNS (1)),
+ fp_mult_sf (COSTS_N_INSNS (2)),
+ fp_mult_df (COSTS_N_INSNS (4)),
+ fp_div_sf (COSTS_N_INSNS (6)),
+ fp_div_df (COSTS_N_INSNS (8)),
+ int_mult_si (COSTS_N_INSNS (1)),
+ int_mult_di (COSTS_N_INSNS (1)),
+ int_div_si (COSTS_N_INSNS (4)),
+ int_div_di (COSTS_N_INSNS (6)),
+ branch_cost (6),
+ memory_latency (4) {}
+
+/* The following properties cannot be looked up directly using "cpucfg".
+ So it is necessary to provide a default value for "unknown native"
+ tune targets (i.e. -mtune=native while PRID does not correspond to
+ any known "-mtune" type). Currently all numbers are default. */
+array_tune<loongarch_rtx_cost_data> loongarch_cpu_rtx_cost_data =
+ array_tune<loongarch_rtx_cost_data> ();
+
+/* RTX costs to use when optimizing for size. */
+const loongarch_rtx_cost_data loongarch_rtx_cost_optimize_size =
+ loongarch_rtx_cost_data ()
+ .fp_add_ (4)
+ .fp_mult_sf_ (4)
+ .fp_mult_df_ (4)
+ .fp_div_sf_ (4)
+ .fp_div_df_ (4)
+ .int_mult_si_ (4)
+ .int_mult_di_ (4)
+ .int_div_si_ (4)
+ .int_div_di_ (4);
+
+array_tune<int> loongarch_cpu_issue_rate = array_tune<int> ()
+ .set (CPU_NATIVE, 4)
+ .set (CPU_LOONGARCH64, 4)
+ .set (CPU_LA464, 4);
+
+array_tune<int> loongarch_cpu_multipass_dfa_lookahead = array_tune<int> ()
+ .set (CPU_NATIVE, 4)
+ .set (CPU_LOONGARCH64, 4)
+ .set (CPU_LA464, 4);
+
+/* Wiring string definitions from loongarch-str.h to global arrays
+ with standard index values from loongarch-opts.h, so we can
+ print config-related messages and do ABI self-spec filtering
+ from the driver in a self-consistent manner. */
+
+array<const char *, N_ISA_BASE_TYPES> loongarch_isa_base_strings =
+ array<const char *, N_ISA_BASE_TYPES> ()
+ .set (ISA_BASE_LA64V100, STR_ISA_BASE_LA64V100);
+
+array<const char *, N_ISA_EXT_TYPES> loongarch_isa_ext_strings =
+ array<const char *, N_ISA_EXT_TYPES> ()
+ .set (ISA_EXT_NONE, STR_NONE)
+ .set (ISA_EXT_FPU32, STR_ISA_EXT_FPU32)
+ .set (ISA_EXT_FPU64, STR_ISA_EXT_FPU64)
+ .set (ISA_EXT_SIMD_LSX, STR_ISA_EXT_LSX)
+ .set (ISA_EXT_SIMD_LASX, STR_ISA_EXT_LASX);
+
+array<const char *, N_ABI_BASE_TYPES> loongarch_abi_base_strings =
+ array<const char *, N_ABI_BASE_TYPES> ()
+ .set (ABI_BASE_LP64D, STR_ABI_BASE_LP64D)
+ .set (ABI_BASE_LP64F, STR_ABI_BASE_LP64F)
+ .set (ABI_BASE_LP64S, STR_ABI_BASE_LP64S);
+
+array<const char *, N_ABI_EXT_TYPES> loongarch_abi_ext_strings =
+ array<const char *, N_ABI_EXT_TYPES> ()
+ .set (ABI_EXT_BASE, STR_ABI_EXT_BASE);
+
+array<const char *, N_CMODEL_TYPES> loongarch_cmodel_strings =
+ array<const char *, N_CMODEL_TYPES> ()
+ .set (CMODEL_NORMAL, STR_CMODEL_NORMAL)
+ .set (CMODEL_TINY, STR_CMODEL_TINY)
+ .set (CMODEL_TINY_STATIC, STR_CMODEL_TS)
+ .set (CMODEL_MEDIUM, STR_CMODEL_MEDIUM)
+ .set (CMODEL_LARGE, STR_CMODEL_LARGE)
+ .set (CMODEL_EXTREME, STR_CMODEL_EXTREME);
+
+array<array<loongarch_isa, N_ABI_EXT_TYPES>, N_ABI_BASE_TYPES>
+ abi_minimal_isa = array<array<loongarch_isa, N_ABI_EXT_TYPES>,
+ N_ABI_BASE_TYPES> ()
+ .set (ABI_BASE_LP64D,
+ array<loongarch_isa, N_ABI_EXT_TYPES> ()
+ .set (ABI_EXT_BASE,
+ loongarch_isa ()
+ .base_ (ISA_BASE_LA64V100)
+ .fpu_ (ISA_EXT_FPU64)))
+ .set (ABI_BASE_LP64F,
+ array<loongarch_isa, N_ABI_EXT_TYPES> ()
+ .set (ABI_EXT_BASE,
+ loongarch_isa ()
+ .base_ (ISA_BASE_LA64V100)
+ .fpu_ (ISA_EXT_FPU32)))
+ .set (ABI_BASE_LP64S,
+ array<loongarch_isa, N_ABI_EXT_TYPES> ()
+ .set (ABI_EXT_BASE,
+ loongarch_isa ().base_ (ISA_BASE_LA64V100)));
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index 6e2a6987910..d36c2769f78 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -46,19 +46,16 @@ along with GCC; see the file COPYING3. If not see
#ifndef LOONGARCH_DEF_H
#define LOONGARCH_DEF_H
+#include "loongarch-def-array.h"
#include "loongarch-tune.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
/* enum isa_base */
-extern const char* loongarch_isa_base_strings[];
#define ISA_BASE_LA64V100 0
#define N_ISA_BASE_TYPES 1
+extern loongarch_def_array<const char *, N_ISA_BASE_TYPES>
+ loongarch_isa_base_strings;
/* enum isa_ext_* */
-extern const char* loongarch_isa_ext_strings[];
#define ISA_EXT_NONE 0
#define ISA_EXT_FPU32 1
#define ISA_EXT_FPU64 2
@@ -66,13 +63,16 @@ extern const char* loongarch_isa_ext_strings[];
#define ISA_EXT_SIMD_LSX 3
#define ISA_EXT_SIMD_LASX 4
#define N_ISA_EXT_TYPES 5
+extern loongarch_def_array<const char *, N_ISA_EXT_TYPES>
+ loongarch_isa_ext_strings;
/* enum abi_base */
-extern const char* loongarch_abi_base_strings[];
#define ABI_BASE_LP64D 0
#define ABI_BASE_LP64F 1
#define ABI_BASE_LP64S 2
#define N_ABI_BASE_TYPES 3
+extern loongarch_def_array<const char *, N_ABI_BASE_TYPES>
+ loongarch_abi_base_strings;
#define TO_LP64_ABI_BASE(C) (C)
@@ -85,12 +85,12 @@ extern const char* loongarch_abi_base_strings[];
/* enum abi_ext */
-extern const char* loongarch_abi_ext_strings[];
#define ABI_EXT_BASE 0
#define N_ABI_EXT_TYPES 1
+extern loongarch_def_array<const char *, N_ABI_EXT_TYPES>
+ loongarch_abi_ext_strings;
/* enum cmodel */
-extern const char* loongarch_cmodel_strings[];
#define CMODEL_NORMAL 0
#define CMODEL_TINY 1
#define CMODEL_TINY_STATIC 2
@@ -98,6 +98,8 @@ extern const char* loongarch_cmodel_strings[];
#define CMODEL_LARGE 4
#define CMODEL_EXTREME 5
#define N_CMODEL_TYPES 6
+extern loongarch_def_array<const char *, N_CMODEL_TYPES>
+ loongarch_cmodel_strings;
/* enum explicit_relocs */
#define EXPLICIT_RELOCS_AUTO 0
@@ -111,13 +113,17 @@ extern const char* loongarch_cmodel_strings[];
#define M_OPT_UNSET -1
#define M_OPT_ABSENT(opt_enum) ((opt_enum) == M_OPT_UNSET)
-
/* Internal representation of the target. */
struct loongarch_isa
{
int base; /* ISA_BASE_ */
int fpu; /* ISA_EXT_FPU_ */
int simd; /* ISA_EXT_SIMD_ */
+
+ loongarch_isa () : base (0), fpu (0), simd (0) {}
+ loongarch_isa base_ (int _base) { base = _base; return *this; }
+ loongarch_isa fpu_ (int _fpu) { fpu = _fpu; return *this; }
+ loongarch_isa simd_ (int _simd) { simd = _simd; return *this; }
};
struct loongarch_abi
@@ -145,16 +151,19 @@ struct loongarch_target
#define N_TUNE_TYPES 4
/* parallel tables. */
-extern const char* loongarch_cpu_strings[];
-extern struct loongarch_isa loongarch_cpu_default_isa[];
-extern int loongarch_cpu_issue_rate[];
-extern int loongarch_cpu_multipass_dfa_lookahead[];
-
-extern struct loongarch_cache loongarch_cpu_cache[];
-extern struct loongarch_align loongarch_cpu_align[];
-extern struct loongarch_rtx_cost_data loongarch_cpu_rtx_cost_data[];
-
-#ifdef __cplusplus
-}
-#endif
+extern loongarch_def_array<const char *, N_ARCH_TYPES>
+ loongarch_cpu_strings;
+extern loongarch_def_array<loongarch_isa, N_ARCH_TYPES>
+ loongarch_cpu_default_isa;
+extern loongarch_def_array<int, N_TUNE_TYPES>
+ loongarch_cpu_issue_rate;
+extern loongarch_def_array<int, N_TUNE_TYPES>
+ loongarch_cpu_multipass_dfa_lookahead;
+extern loongarch_def_array<loongarch_cache, N_TUNE_TYPES>
+ loongarch_cpu_cache;
+extern loongarch_def_array<loongarch_align, N_TUNE_TYPES>
+ loongarch_cpu_align;
+extern loongarch_def_array<loongarch_rtx_cost_data, N_TUNE_TYPES>
+ loongarch_cpu_rtx_cost_data;
+
#endif /* LOONGARCH_DEF_H */
diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h
index 8de41bbc4f7..aa99e510282 100644
--- a/gcc/config/loongarch/loongarch-opts.h
+++ b/gcc/config/loongarch/loongarch-opts.h
@@ -21,7 +21,10 @@ along with GCC; see the file COPYING3. If not see
#ifndef LOONGARCH_OPTS_H
#define LOONGARCH_OPTS_H
+/* This is a C++ header and it shouldn't be used by target libraries. */
+#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
#include "loongarch-def.h"
+#endif
/* Target configuration */
extern struct loongarch_target la_target;
diff --git a/gcc/config/loongarch/loongarch-tune.h b/gcc/config/loongarch/loongarch-tune.h
index 5c03262daff..4aa01c54c08 100644
--- a/gcc/config/loongarch/loongarch-tune.h
+++ b/gcc/config/loongarch/loongarch-tune.h
@@ -21,6 +21,8 @@ along with GCC; see the file COPYING3. If not see
#ifndef LOONGARCH_TUNE_H
#define LOONGARCH_TUNE_H
+#include "loongarch-def-array.h"
+
/* RTX costs of various operations on the different architectures. */
struct loongarch_rtx_cost_data
{
@@ -35,6 +37,76 @@ struct loongarch_rtx_cost_data
unsigned short int_div_di;
unsigned short branch_cost;
unsigned short memory_latency;
+
+ /* Default RTX cost initializer, implemented in loongarch-def.cc. */
+ loongarch_rtx_cost_data ();
+
+ loongarch_rtx_cost_data fp_add_ (unsigned short _fp_add)
+ {
+ fp_add = _fp_add;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data fp_mult_sf_ (unsigned short _fp_mult_sf)
+ {
+ fp_mult_sf = _fp_mult_sf;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data fp_mult_df_ (unsigned short _fp_mult_df)
+ {
+ fp_mult_df = _fp_mult_df;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data fp_div_sf_ (unsigned short _fp_div_sf)
+ {
+ fp_div_sf = _fp_div_sf;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data fp_div_df_ (unsigned short _fp_div_df)
+ {
+ fp_div_df = _fp_div_df;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data int_mult_si_ (unsigned short _int_mult_si)
+ {
+ int_mult_si = _int_mult_si;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data int_mult_di_ (unsigned short _int_mult_di)
+ {
+ int_mult_di = _int_mult_di;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data int_div_si_ (unsigned short _int_div_si)
+ {
+ int_div_si = _int_div_si;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data int_div_di_ (unsigned short _int_div_di)
+ {
+ int_div_di = _int_div_di;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data branch_cost_ (unsigned short _branch_cost)
+ {
+ branch_cost = _branch_cost;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data memory_latency_ (unsigned short _memory_latency)
+ {
+ memory_latency = _memory_latency;
+ return *this;
+ }
+
};
/* Costs to use when optimizing for size. */
@@ -42,10 +114,39 @@ extern const struct loongarch_rtx_cost_data loongarch_rtx_cost_optimize_size;
/* Cache size record of known processor models. */
struct loongarch_cache {
- int l1d_line_size; /* bytes */
- int l1d_size; /* KiB */
- int l2d_size; /* kiB */
- int simultaneous_prefetches; /* number of parallel prefetch */
+ int l1d_line_size; /* bytes */
+ int l1d_size; /* KiB */
+ int l2d_size; /* kiB */
+ int simultaneous_prefetches; /* number of parallel prefetch */
+
+ loongarch_cache () : l1d_line_size (0),
+ l1d_size (0),
+ l2d_size (0),
+ simultaneous_prefetches (0) {}
+
+ loongarch_cache l1d_line_size_ (int _l1d_line_size)
+ {
+ l1d_line_size = _l1d_line_size;
+ return *this;
+ }
+
+ loongarch_cache l1d_size_ (int _l1d_size)
+ {
+ l1d_size = _l1d_size;
+ return *this;
+ }
+
+ loongarch_cache l2d_size_ (int _l2d_size)
+ {
+ l2d_size = _l2d_size;
+ return *this;
+ }
+
+ loongarch_cache simultaneous_prefetches_ (int _simultaneous_prefetches)
+ {
+ simultaneous_prefetches = _simultaneous_prefetches;
+ return *this;
+ }
};
/* Alignment for functions and labels for best performance. For new uarchs
@@ -54,6 +155,20 @@ struct loongarch_cache {
struct loongarch_align {
const char *function; /* default value for -falign-functions */
const char *label; /* default value for -falign-labels */
+
+ loongarch_align () : function (nullptr), label (nullptr) {}
+
+ loongarch_align function_ (const char *_function)
+ {
+ function = _function;
+ return *this;
+ }
+
+ loongarch_align label_ (const char *_label)
+ {
+ label = _label;
+ return *this;
+ }
};
#endif /* LOONGARCH_TUNE_H */
diff --git a/gcc/config/loongarch/t-loongarch b/gcc/config/loongarch/t-loongarch
index 667a6bb3b50..0a7eaf6271f 100644
--- a/gcc/config/loongarch/t-loongarch
+++ b/gcc/config/loongarch/t-loongarch
@@ -61,8 +61,8 @@ loongarch-opts.o: $(srcdir)/config/loongarch/loongarch-opts.cc $(LA_STR_H)
loongarch-cpu.o: $(srcdir)/config/loongarch/loongarch-cpu.cc $(LA_STR_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
-loongarch-def.o: $(srcdir)/config/loongarch/loongarch-def.c $(LA_STR_H)
- $(CC) -c $(ALL_CFLAGS) $(INCLUDES) $<
+loongarch-def.o: $(srcdir)/config/loongarch/loongarch-def.cc $(LA_STR_H)
+ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
$(srcdir)/config/loongarch/loongarch.opt: s-loongarch-opt ; @true
s-loongarch-opt: $(srcdir)/config/loongarch/genopts/genstr.sh \
--
2.42.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/5] LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution
2023-11-16 13:18 [PATCH 0/5] LoongArch: Initial LA664 support Xi Ruoyao
2023-11-16 13:18 ` [PATCH 1/5] LoongArch: Switch loongarch-def to C++ Xi Ruoyao
@ 2023-11-16 13:18 ` Xi Ruoyao
2023-11-16 13:18 ` [PATCH 3/5] LoongArch: Take the advantage of -mdiv32 if it's enabled Xi Ruoyao
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Xi Ruoyao @ 2023-11-16 13:18 UTC (permalink / raw)
To: gcc-patches; +Cc: chenglulu, i, xuchenghua, Xi Ruoyao
LoongArch v1.10 introduced the concept of ISA evolution. During ISA
evolution, many independent features can be added and enumerated via
CPUCFG.
Add a data file into genopts storing the CPUCFG word, bit, the name
of the command line option controlling if this feature should be used
for compilation, and the text description. Make genstr.sh process these
info and add the command line options into loongarch.opt and
loongarch-str.h, and generate a new file loongarch-cpucfg-map.h for
mapping CPUCFG output to the corresponding option. When handling
-march=native, use the information in loongarch-cpucfg-map.h to generate
the corresponding option mask. Enable the features implied by -march
setting unless the user has explicitly disabled the feature.
The added options (-mdiv32 and -mld-seq-sa) are not really handled yet.
They'll be used in the following patches.
gcc/ChangeLog:
* config/loongarch/genopts/isa-evolution.in: New data file.
* config/loongarch/genopts/genstr.sh: Translate info in
isa-evolution.in when generating loongarch-str.h, loongarch.opt,
and loongarch-cpucfg-map.h.
* config/loongarch/genopts/loongarch.opt.in (isa_evolution):
New variable.
* config/loongarch/t-loongarch: (loongarch-cpucfg-map.h): New
rule.
(loongarch-str.h): Depend on isa-evolution.in.
(loongarch.opt): Depend on isa-evolution.in.
(loongarch-cpu.o): Depend on loongarch-cpucfg-map.h.
* config/loongarch/loongarch-str.h: Regenerate.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-cpucfg-map.h: Generate.
* config/loongarch/loongarch-def.h (loongarch_isa): Add field
for evolution features. Add helper function to enable features
in this field.
Probe native CPU capability and save the corresponding options
into preset.
* config/loongarch/loongarch-cpu.cc (fill_native_cpu_config):
Probe native CPU capability and save the corresponding options
into preset.
* config/loongarch/loongarch.cc
(loongarch_option_override_internal): Enable the ISA evolution
feature options implied by -march and not explicitly disabled.
* config/loongarch/loongarch-def.cc: Define IN_TARGET_CODE to 1
so it's possible to include config.h and system.h for
HOST_WIDE_INT.
---
gcc/config/loongarch/genopts/genstr.sh | 78 +++++++++++++++++--
gcc/config/loongarch/genopts/isa-evolution.in | 2 +
gcc/config/loongarch/genopts/loongarch.opt.in | 7 ++
gcc/config/loongarch/loongarch-cpu.cc | 37 +++++----
gcc/config/loongarch/loongarch-cpucfg-map.h | 36 +++++++++
gcc/config/loongarch/loongarch-def.cc | 3 +
gcc/config/loongarch/loongarch-def.h | 11 ++-
gcc/config/loongarch/loongarch-str.h | 7 +-
gcc/config/loongarch/loongarch.cc | 4 +
gcc/config/loongarch/loongarch.opt | 20 ++++-
gcc/config/loongarch/t-loongarch | 21 ++++-
11 files changed, 196 insertions(+), 30 deletions(-)
create mode 100644 gcc/config/loongarch/genopts/isa-evolution.in
create mode 100644 gcc/config/loongarch/loongarch-cpucfg-map.h
diff --git a/gcc/config/loongarch/genopts/genstr.sh b/gcc/config/loongarch/genopts/genstr.sh
index 04e785576bb..7f461118a97 100755
--- a/gcc/config/loongarch/genopts/genstr.sh
+++ b/gcc/config/loongarch/genopts/genstr.sh
@@ -25,8 +25,8 @@ cd "$(dirname "$0")"
# Generate a header containing definitions from the string table.
gen_defines() {
cat <<EOF
-/* Generated automatically by "genstr" from "loongarch-strings".
- Please do not edit this file directly.
+/* Generated automatically by "genstr" from "loongarch-strings" and
+ "isa-evolution.in". Please do not edit this file directly.
Copyright (C) 2021-2023 Free Software Foundation, Inc.
Contributed by Loongson Ltd.
@@ -55,6 +55,15 @@ EOF
-e 's@^\([^ \t]\+\)[ \t]*\([^ \t]*\)@#define \1 "\2"@' \
loongarch-strings
+ echo
+
+ # Generate the strings from isa-evolution.in.
+ awk '{
+ a=$3
+ gsub(/-/, "_", a)
+ print("#define OPTSTR_"toupper(a)"\t\""$3"\"")
+ }' isa-evolution.in
+
echo
echo "#endif /* LOONGARCH_STR_H */"
}
@@ -77,11 +86,12 @@ gen_options() {
# print a header
cat << EOF
; Generated by "genstr" from the template "loongarch.opt.in"
-; and definitions from "loongarch-strings".
+; and definitions from "loongarch-strings" and "isa-evolution.in".
;
; Please do not edit this file directly.
; It will be automatically updated during a gcc build
-; if you change "loongarch.opt.in" or "loongarch-strings".
+; if you change "loongarch.opt.in", "loongarch-strings", or
+; "isa-evolution.in".
;
EOF
@@ -91,13 +101,71 @@ EOF
eval "echo \"$line\""
done
}
+
+ # Generate the strings from isa-evolution.in.
+ awk '{
+ print("")
+ print("m"$3)
+ gsub(/-/, "_", $3)
+ print("Target Mask(ISA_"toupper($3)") Var(isa_evolution)")
+ $1=""; $2=""; $3=""
+ sub(/^ */, "", $0)
+ print($0)
+ }' isa-evolution.in
+}
+
+gen_cpucfg_map() {
+ cat <<EOF
+/* Generated automatically by "genstr" from "isa-evolution.in".
+ Please do not edit this file directly.
+
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#ifndef LOONGARCH_CPUCFG_MAP_H
+#define LOONGARCH_CPUCFG_MAP_H
+
+#include "options.h"
+
+static constexpr struct {
+ int cpucfg_word;
+ unsigned int cpucfg_bit;
+ HOST_WIDE_INT isa_evolution_bit;
+} cpucfg_map[] = {
+EOF
+
+ # Generate the strings from isa-evolution.in.
+ awk '{
+ gsub(/-/, "_", $3)
+ print(" { "$1", 1u << "$2", OPTION_MASK_ISA_"toupper($3)" },")
+ }' isa-evolution.in
+
+ echo "};"
+ echo
+ echo "#endif /* LOONGARCH_STR_H */"
}
main() {
case "$1" in
+ cpucfg-map) gen_cpucfg_map;;
header) gen_defines;;
opt) gen_options;;
- *) echo "Unknown Command: \"$1\". Available: header, opt"; exit 1;;
+ *) echo "Unknown Command: \"$1\". Available: cpucfg-map, header, opt"; exit 1;;
esac
}
diff --git a/gcc/config/loongarch/genopts/isa-evolution.in b/gcc/config/loongarch/genopts/isa-evolution.in
new file mode 100644
index 00000000000..7525be762fb
--- /dev/null
+++ b/gcc/config/loongarch/genopts/isa-evolution.in
@@ -0,0 +1,2 @@
+0x2 26 div32 Support div.w[u] and mod.w[u] instructions with inputs not sign-extended.
+0x3 23 ld-seq-sa Do not need load-load barriers (dbar 0x700).
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
index 158701d327a..4a22039681f 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -241,3 +241,10 @@ Target Undocumented Joined UInteger Var(loongarch_vect_issue_info) Init(4) Integ
Indicate how many non memory access vector instructions can be issued per
cycle, it's used in unroll factor determination for autovectorizer. The
default value is 4.
+
+; Features added during ISA evolution. This concept is different from ISA
+; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the
+; explanation. These features may be implemented and enumerated with
+; CPUCFG independantly, so we use bit flags to specify them.
+Variable
+HOST_WIDE_INT isa_evolution = 0
diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc
index 7a2866f60f9..03acf632353 100644
--- a/gcc/config/loongarch/loongarch-cpu.cc
+++ b/gcc/config/loongarch/loongarch-cpu.cc
@@ -29,6 +29,7 @@ along with GCC; see the file COPYING3. If not see
#include "loongarch-def.h"
#include "loongarch-opts.h"
#include "loongarch-cpu.h"
+#include "loongarch-cpucfg-map.h"
#include "loongarch-str.h"
/* Native CPU detection with "cpucfg" */
@@ -121,11 +122,12 @@ fill_native_cpu_config (struct loongarch_target *tgt)
int tmp;
tgt->cpu_arch = native_cpu_type;
+ auto &preset = loongarch_cpu_default_isa[tgt->cpu_arch];
+
/* Fill: loongarch_cpu_default_isa[tgt->cpu_arch].base
With: base architecture (ARCH)
At: cpucfg_words[1][1:0] */
- #define PRESET_ARCH (loongarch_cpu_default_isa[tgt->cpu_arch].base)
switch (cpucfg_cache[1] & 0x3)
{
case 0x02:
@@ -140,19 +142,18 @@ fill_native_cpu_config (struct loongarch_target *tgt)
}
/* Check consistency with PRID presets. */
- if (native_cpu_type != CPU_NATIVE && tmp != PRESET_ARCH)
+ if (native_cpu_type != CPU_NATIVE && tmp != preset.base)
warning (0, "base architecture %qs differs from PRID preset %qs",
loongarch_isa_base_strings[tmp],
- loongarch_isa_base_strings[PRESET_ARCH]);
+ loongarch_isa_base_strings[preset.base]);
/* Use the native value anyways. */
- PRESET_ARCH = tmp;
+ preset.base = tmp;
/* Fill: loongarch_cpu_default_isa[tgt->cpu_arch].fpu
With: FPU type (FP, FP_SP, FP_DP)
At: cpucfg_words[2][2:0] */
- #define PRESET_FPU (loongarch_cpu_default_isa[tgt->cpu_arch].fpu)
switch (cpucfg_cache[2] & 0x7)
{
case 0x07:
@@ -175,20 +176,19 @@ fill_native_cpu_config (struct loongarch_target *tgt)
}
/* Check consistency with PRID presets. */
- if (native_cpu_type != CPU_NATIVE && tmp != PRESET_FPU)
+ if (native_cpu_type != CPU_NATIVE && tmp != preset.fpu)
warning (0, "floating-point unit %qs differs from PRID preset %qs",
loongarch_isa_ext_strings[tmp],
- loongarch_isa_ext_strings[PRESET_FPU]);
+ loongarch_isa_ext_strings[preset.fpu]);
/* Use the native value anyways. */
- PRESET_FPU = tmp;
+ preset.fpu = tmp;
/* Fill: loongarch_cpu_default_isa[CPU_NATIVE].simd
With: SIMD extension type (LSX, LASX)
At: cpucfg_words[2][7:6] */
- #define PRESET_SIMD (loongarch_cpu_default_isa[tgt->cpu_arch].simd)
switch (cpucfg_cache[2] & 0xc0)
{
case 0xc0:
@@ -215,14 +215,19 @@ fill_native_cpu_config (struct loongarch_target *tgt)
/* Check consistency with PRID presets. */
/*
- if (native_cpu_type != CPU_NATIVE && tmp != PRESET_SIMD)
+ if (native_cpu_type != CPU_NATIVE && tmp != preset.simd)
warning (0, "SIMD extension %qs differs from PRID preset %qs",
loongarch_isa_ext_strings[tmp],
- loongarch_isa_ext_strings[PRESET_SIMD]);
+ loongarch_isa_ext_strings[preset.simd]);
*/
/* Use the native value anyways. */
- PRESET_SIMD = tmp;
+ preset.simd = tmp;
+
+ /* Features added during ISA evolution. */
+ for (const auto &entry: cpucfg_map)
+ if (cpucfg_cache[entry.cpucfg_word] & entry.cpucfg_bit)
+ preset.evol_add_feat (entry.isa_evolution_bit);
}
if (tune_native_p)
@@ -233,7 +238,7 @@ fill_native_cpu_config (struct loongarch_target *tgt)
With: cache size info
At: cpucfg_words[16:20][31:0] */
- #define PRESET_CACHE (loongarch_cpu_cache[tgt->cpu_tune])
+ auto &preset_cache = loongarch_cpu_cache[tgt->cpu_tune];
struct loongarch_cache native_cache;
int l1d_present = 0, l1u_present = 0;
int l2d_present = 0;
@@ -264,8 +269,8 @@ fill_native_cpu_config (struct loongarch_target *tgt)
>> 10; /* in kibibytes */
/* Use the native value anyways. */
- PRESET_CACHE.l1d_line_size = native_cache.l1d_line_size;
- PRESET_CACHE.l1d_size = native_cache.l1d_size;
- PRESET_CACHE.l2d_size = native_cache.l2d_size;
+ preset_cache.l1d_line_size = native_cache.l1d_line_size;
+ preset_cache.l1d_size = native_cache.l1d_size;
+ preset_cache.l2d_size = native_cache.l2d_size;
}
}
diff --git a/gcc/config/loongarch/loongarch-cpucfg-map.h b/gcc/config/loongarch/loongarch-cpucfg-map.h
new file mode 100644
index 00000000000..78a4acf535b
--- /dev/null
+++ b/gcc/config/loongarch/loongarch-cpucfg-map.h
@@ -0,0 +1,36 @@
+/* Generated automatically by "genstr" from "isa-evolution.in".
+ Please do not edit this file directly.
+
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#ifndef LOONGARCH_CPUCFG_MAP_H
+#define LOONGARCH_CPUCFG_MAP_H
+
+#include "options.h"
+
+static constexpr struct {
+ int cpucfg_word;
+ unsigned int cpucfg_bit;
+ HOST_WIDE_INT isa_evolution_bit;
+} cpucfg_map[] = {
+ { 0x2, 1u << 26, OPTION_MASK_ISA_DIV32 },
+ { 0x3, 1u << 23, OPTION_MASK_ISA_LD_SEQ_SA },
+};
+
+#endif /* LOONGARCH_STR_H */
diff --git a/gcc/config/loongarch/loongarch-def.cc b/gcc/config/loongarch/loongarch-def.cc
index 0200c48f43b..9c2ec1ec135 100644
--- a/gcc/config/loongarch/loongarch-def.cc
+++ b/gcc/config/loongarch/loongarch-def.cc
@@ -18,6 +18,9 @@ You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
+#define IN_TARGET_CODE
+#include "config.h"
+#include "system.h"
#include "loongarch-def.h"
#include "loongarch-str.h"
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index d36c2769f78..e74036fda33 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -120,10 +120,19 @@ struct loongarch_isa
int fpu; /* ISA_EXT_FPU_ */
int simd; /* ISA_EXT_SIMD_ */
- loongarch_isa () : base (0), fpu (0), simd (0) {}
+ /* ISA evolution features implied by cpu_arch or probed for native. */
+ HOST_WIDE_INT evolution;
+
+ loongarch_isa () : base (0), fpu (0), simd (0), evolution (0) {}
loongarch_isa base_ (int _base) { base = _base; return *this; }
loongarch_isa fpu_ (int _fpu) { fpu = _fpu; return *this; }
loongarch_isa simd_ (int _simd) { simd = _simd; return *this; }
+
+ loongarch_isa evol_add_feat (HOST_WIDE_INT bit)
+ {
+ evolution |= bit;
+ return *this;
+ }
};
struct loongarch_abi
diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
index 072558c28f1..3fa2ed5fc49 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -1,5 +1,5 @@
-/* Generated automatically by "genstr" from "loongarch-strings".
- Please do not edit this file directly.
+/* Generated automatically by "genstr" from "loongarch-strings" and
+ "isa-evolution.in". Please do not edit this file directly.
Copyright (C) 2021-2023 Free Software Foundation, Inc.
Contributed by Loongson Ltd.
@@ -67,4 +67,7 @@ along with GCC; see the file COPYING3. If not see
#define STR_EXPLICIT_RELOCS_NONE "none"
#define STR_EXPLICIT_RELOCS_ALWAYS "always"
+#define OPTSTR_DIV32 "div32"
+#define OPTSTR_LD_SEQ_SA "ld-seq-sa"
+
#endif /* LOONGARCH_STR_H */
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 738911661d7..6f89d468795 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -7455,6 +7455,10 @@ loongarch_option_override_internal (struct gcc_options *opts,
if (loongarch_branch_cost == 0)
loongarch_branch_cost = loongarch_cost->branch_cost;
+ /* If the user hasn't disabled a feature added during ISA evolution,
+ use the processor's default. */
+ isa_evolution |= (la_target.isa.evolution &
+ ~global_options_set.x_isa_evolution);
/* Enable sw prefetching at -O3 and higher. */
if (opts->x_flag_prefetch_loop_arrays < 0
diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index a5988411fbb..b17df1302f7 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -1,9 +1,10 @@
; Generated by "genstr" from the template "loongarch.opt.in"
-; and definitions from "loongarch-strings".
+; and definitions from "loongarch-strings" and "isa-evolution.in".
;
; Please do not edit this file directly.
; It will be automatically updated during a gcc build
-; if you change "loongarch.opt.in" or "loongarch-strings".
+; if you change "loongarch.opt.in", "loongarch-strings", or
+; "isa-evolution.in".
;
; Copyright (C) 2021-2023 Free Software Foundation, Inc.
;
@@ -248,3 +249,18 @@ Target Undocumented Joined UInteger Var(loongarch_vect_issue_info) Init(4) Integ
Indicate how many non memory access vector instructions can be issued per
cycle, it's used in unroll factor determination for autovectorizer. The
default value is 4.
+
+; Features added during ISA evolution. This concept is different from ISA
+; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the
+; explanation. These features may be implemented and enumerated with
+; CPUCFG independantly, so we use bit flags to specify them.
+Variable
+HOST_WIDE_INT isa_evolution = 0
+
+mdiv32
+Target Mask(ISA_DIV32) Var(isa_evolution)
+Support div.w[u] and mod.w[u] instructions with inputs not sign-extended.
+
+mld-seq-sa
+Target Mask(ISA_LD_SEQ_SA) Var(isa_evolution)
+Do not need load-load barriers (dbar 0x700).
diff --git a/gcc/config/loongarch/t-loongarch b/gcc/config/loongarch/t-loongarch
index 0a7eaf6271f..10a984f3cb1 100644
--- a/gcc/config/loongarch/t-loongarch
+++ b/gcc/config/loongarch/t-loongarch
@@ -18,8 +18,9 @@
GTM_H += loongarch-multilib.h
-OPTIONS_H_EXTRA += $(srcdir)/config/loongarch/loongarch-def.h \
- $(srcdir)/config/loongarch/loongarch-tune.h
+OPTIONS_H_EXTRA += $(srcdir)/config/loongarch/loongarch-def.h \
+ $(srcdir)/config/loongarch/loongarch-tune.h \
+ $(srcdir)/config/loongarch/loongarch-cpucfg-map.h
# Canonical target triplet from config.gcc
LA_MULTIARCH_TRIPLET = $(patsubst LA_MULTIARCH_TRIPLET=%,%,$\
@@ -31,7 +32,8 @@ LA_STR_H = $(srcdir)/config/loongarch/loongarch-str.h
# String definition header
$(LA_STR_H): s-loongarch-str ; @true
s-loongarch-str: $(srcdir)/config/loongarch/genopts/genstr.sh \
- $(srcdir)/config/loongarch/genopts/loongarch-strings
+ $(srcdir)/config/loongarch/genopts/loongarch-strings \
+ $(srcdir)/config/loongarch/genopts/isa-evolution.in
$(SHELL) $(srcdir)/config/loongarch/genopts/genstr.sh header \
$(srcdir)/config/loongarch/genopts/loongarch-strings > \
tmp-loongarch-str.h
@@ -58,7 +60,8 @@ loongarch-driver.o : $(srcdir)/config/loongarch/loongarch-driver.cc $(LA_STR_H)
loongarch-opts.o: $(srcdir)/config/loongarch/loongarch-opts.cc $(LA_STR_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
-loongarch-cpu.o: $(srcdir)/config/loongarch/loongarch-cpu.cc $(LA_STR_H)
+loongarch-cpu.o: $(srcdir)/config/loongarch/loongarch-cpu.cc $(LA_STR_H) \
+ $(srcdir)/config/loongarch/loongarch-cpucfg-map.h
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
loongarch-def.o: $(srcdir)/config/loongarch/loongarch-def.cc $(LA_STR_H)
@@ -67,6 +70,7 @@ loongarch-def.o: $(srcdir)/config/loongarch/loongarch-def.cc $(LA_STR_H)
$(srcdir)/config/loongarch/loongarch.opt: s-loongarch-opt ; @true
s-loongarch-opt: $(srcdir)/config/loongarch/genopts/genstr.sh \
$(srcdir)/config/loongarch/genopts/loongarch.opt.in \
+ $(srcdir)/config/loongarch/genopts/isa-evolution.in \
$(srcdir)/config/loongarch/genopts/loongarch-strings $(LA_STR_H)
$(SHELL) $(srcdir)/config/loongarch/genopts/genstr.sh opt \
$(srcdir)/config/loongarch/genopts/loongarch.opt.in \
@@ -74,3 +78,12 @@ s-loongarch-opt: $(srcdir)/config/loongarch/genopts/genstr.sh \
$(SHELL) $(srcdir)/../move-if-change tmp-loongarch.opt \
$(srcdir)/config/loongarch/loongarch.opt
$(STAMP) s-loongarch-opt
+
+$(srcdir)/config/loongarch/loongarch-cpucfg-map.h: s-loongarch-cpucfg-map
+ @true
+s-loongarch-cpucfg-map: $(srcdir)/config/loongarch/genopts/genstr.sh \
+ $(srcdir)/config/loongarch/genopts/isa-evolution.in
+ $(SHELL) $< cpucfg-map > tmp-cpucfg.h
+ $(SHELL) $(srcdir)/../move-if-change tmp-cpucfg.h \
+ $(srcdir)/config/loongarch/loongarch-cpucfg-map.h
+ $(STAMP) $@
--
2.42.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/5] LoongArch: Take the advantage of -mdiv32 if it's enabled
2023-11-16 13:18 [PATCH 0/5] LoongArch: Initial LA664 support Xi Ruoyao
2023-11-16 13:18 ` [PATCH 1/5] LoongArch: Switch loongarch-def to C++ Xi Ruoyao
2023-11-16 13:18 ` [PATCH 2/5] LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution Xi Ruoyao
@ 2023-11-16 13:18 ` Xi Ruoyao
2023-11-16 13:18 ` [PATCH 4/5] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa Xi Ruoyao
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Xi Ruoyao @ 2023-11-16 13:18 UTC (permalink / raw)
To: gcc-patches; +Cc: chenglulu, i, xuchenghua, Xi Ruoyao
With -mdiv32, we can assume div.w[u] and mod.w[u] works on low 32 bits
of a 64-bit GPR even if it's not sign-extended.
gcc/ChangeLog:
* config/loongarch/loongarch.md (DIV): New mode iterator.
(<optab:ANY_DIV><mode:GPR>3): Don't expand if TARGET_DIV32.
(<optab:ANY_DIV>di3_fake): Disable if TARGET_DIV32.
(*<optab:ANY_DIV><mode:GPR>3): Allow SImode if TARGET_DIV32.
(<optab:ANY_DIV>si3_extended): New insn if TARGET_DIV32.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/div-div32.c: New test.
* gcc.target/loongarch/div-no-div32.c: New test.
---
gcc/config/loongarch/loongarch.md | 31 ++++++++++++++++---
.../gcc.target/loongarch/div-div32.c | 31 +++++++++++++++++++
.../gcc.target/loongarch/div-no-div32.c | 11 +++++++
3 files changed, 68 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/loongarch/div-div32.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/div-no-div32.c
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 22814a3679c..a97e5ee094a 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -408,6 +408,10 @@ (define_mode_iterator LD_AT_LEAST_32_BIT [GPR ANYF])
;; st.w.
(define_mode_iterator ST_ANY [QHWD ANYF])
+;; A mode for anything legal as a input of a div or mod instruction.
+(define_mode_iterator DIV [(DI "TARGET_64BIT")
+ (SI "!TARGET_64BIT || TARGET_DIV32")])
+
;; In GPR templates, a string like "mul.<d>" will expand to "mul.w" in the
;; 32-bit version and "mul.d" in the 64-bit version.
(define_mode_attr d [(SI "w") (DI "d")])
@@ -914,7 +918,7 @@ (define_expand "<optab><mode>3"
(match_operand:GPR 2 "register_operand")))]
""
{
- if (GET_MODE (operands[0]) == SImode && TARGET_64BIT)
+ if (GET_MODE (operands[0]) == SImode && TARGET_64BIT && !TARGET_DIV32)
{
rtx reg1 = gen_reg_rtx (DImode);
rtx reg2 = gen_reg_rtx (DImode);
@@ -934,9 +938,9 @@ (define_expand "<optab><mode>3"
})
(define_insn "*<optab><mode>3"
- [(set (match_operand:X 0 "register_operand" "=r,&r,&r")
- (any_div:X (match_operand:X 1 "register_operand" "r,r,0")
- (match_operand:X 2 "register_operand" "r,r,r")))]
+ [(set (match_operand:DIV 0 "register_operand" "=r,&r,&r")
+ (any_div:DIV (match_operand:DIV 1 "register_operand" "r,r,0")
+ (match_operand:DIV 2 "register_operand" "r,r,r")))]
""
{
return loongarch_output_division ("<insn>.<d><u>\t%0,%1,%2", operands);
@@ -949,6 +953,23 @@ (define_insn "*<optab><mode>3"
(const_string "yes")
(const_string "no")))])
+(define_insn "<optab>si3_extended"
+ [(set (match_operand:DI 0 "register_operand" "=r,&r,&r")
+ (sign_extend
+ (any_div:SI (match_operand:SI 1 "register_operand" "r,r,0")
+ (match_operand:SI 2 "register_operand" "r,r,r"))))]
+ "TARGET_64BIT && TARGET_DIV32"
+{
+ return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands);
+}
+ [(set_attr "type" "idiv")
+ (set_attr "mode" "SI")
+ (set (attr "enabled")
+ (if_then_else
+ (match_test "!!which_alternative == loongarch_check_zero_div_p()")
+ (const_string "yes")
+ (const_string "no")))])
+
(define_insn "<optab>di3_fake"
[(set (match_operand:DI 0 "register_operand" "=r,&r,&r")
(sign_extend:DI
@@ -957,7 +978,7 @@ (define_insn "<optab>di3_fake"
(any_div:DI (match_operand:DI 1 "register_operand" "r,r,0")
(match_operand:DI 2 "register_operand" "r,r,r")) 0)]
UNSPEC_FAKE_ANY_DIV)))]
- "TARGET_64BIT"
+ "TARGET_64BIT && !TARGET_DIV32"
{
return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands);
}
diff --git a/gcc/testsuite/gcc.target/loongarch/div-div32.c b/gcc/testsuite/gcc.target/loongarch/div-div32.c
new file mode 100644
index 00000000000..8b1f686eca2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/div-div32.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mdiv32" } */
+/* { dg-final { scan-assembler "div\.w" } } */
+/* { dg-final { scan-assembler "div\.wu" } } */
+/* { dg-final { scan-assembler "mod\.w" } } */
+/* { dg-final { scan-assembler "mod\.wu" } } */
+/* { dg-final { scan-assembler-not "slli\.w.*,0" } } */
+
+int
+divw (long a, long b)
+{
+ return (int)a / (int)b;
+}
+
+unsigned int
+divwu (long a, long b)
+{
+ return (unsigned int)a / (unsigned int)b;
+}
+
+int
+modw (long a, long b)
+{
+ return (int)a % (int)b;
+}
+
+unsigned int
+modwu (long a, long b)
+{
+ return (unsigned int)a % (unsigned int)b;
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/div-no-div32.c b/gcc/testsuite/gcc.target/loongarch/div-no-div32.c
new file mode 100644
index 00000000000..f0f697ba589
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/div-no-div32.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */
+/* { dg-final { scan-assembler "div\.w" } } */
+/* { dg-final { scan-assembler "div\.wu" } } */
+/* { dg-final { scan-assembler "mod\.w" } } */
+/* { dg-final { scan-assembler "mod\.wu" } } */
+
+/* -mno-div32 should be implied by -march=loongarch64. */
+/* { dg-final { scan-assembler-times "slli\.w\[^\n\]*0" 8 } } */
+
+#include "div-div32.c"
--
2.42.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 4/5] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa
2023-11-16 13:18 [PATCH 0/5] LoongArch: Initial LA664 support Xi Ruoyao
` (2 preceding siblings ...)
2023-11-16 13:18 ` [PATCH 3/5] LoongArch: Take the advantage of -mdiv32 if it's enabled Xi Ruoyao
@ 2023-11-16 13:18 ` Xi Ruoyao
2023-11-16 13:18 ` [PATCH 5/5] LoongArch: Add -march=la664 and -mtune=la664 Xi Ruoyao
2023-11-17 2:41 ` [PATCH 0/5] LoongArch: Initial LA664 support chenglulu
5 siblings, 0 replies; 9+ messages in thread
From: Xi Ruoyao @ 2023-11-16 13:18 UTC (permalink / raw)
To: gcc-patches; +Cc: chenglulu, i, xuchenghua, Xi Ruoyao
This option (CPUCFG word 0x3 bit 23) means "the hardware guarantee that
two loads on the same address won't be reordered with each other". Thus
we can omit the "load-load" barrier dbar 0x700.
This is only a micro-optimization because dbar 0x700 is already treated
as nop if the hardware supports LD_SEQ_SA.
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_print_operand): Don't
print dbar 0x700 if TARGET_LD_SEQ_SA.
---
gcc/config/loongarch/loongarch.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 6f89d468795..c6eec2345a9 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -6061,7 +6061,7 @@ loongarch_print_operand (FILE *file, rtx op, int letter)
if (loongarch_cas_failure_memorder_needs_acquire (
memmodel_from_int (INTVAL (op))))
fputs ("dbar\t0b10100", file);
- else
+ else if (!TARGET_LD_SEQ_SA)
fputs ("dbar\t0x700", file);
break;
--
2.42.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 5/5] LoongArch: Add -march=la664 and -mtune=la664
2023-11-16 13:18 [PATCH 0/5] LoongArch: Initial LA664 support Xi Ruoyao
` (3 preceding siblings ...)
2023-11-16 13:18 ` [PATCH 4/5] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa Xi Ruoyao
@ 2023-11-16 13:18 ` Xi Ruoyao
2023-11-17 2:41 ` [PATCH 0/5] LoongArch: Initial LA664 support chenglulu
5 siblings, 0 replies; 9+ messages in thread
From: Xi Ruoyao @ 2023-11-16 13:18 UTC (permalink / raw)
To: gcc-patches; +Cc: chenglulu, i, xuchenghua, Xi Ruoyao
Allow using -march=la664 and -mtune=la664. -march=la664 implies -mdiv32
and -mld-seq-sa. -mtune=la664 is currently same as -mtune=la464 and it
may need an update later.
gcc/ChangeLog:
* config/loongarch/genopts/loongarch-strings: Add la664 as
STR_CPU_LA664.
* config/loongarch/genopts/loongarch.opt.in (cpu_type): Add
la664.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-str.h: Regenerate.
* config/loongarch/loongarch-def.h (CPU_LA664): Define.
(N_ARCH_TYPES): Increase to 5.
(N_TUNE_TYPES): Increase to 5.
* config/loongarch/loongarch-def.cc (loongarch_cpu_strings):
Set [CPU_LA664] to STR_CPU_LA664.
(loongarch_cpu_default_isa): Set [CPU_LA664] to
{ISA_BASE_LA64V100, ISA_EXT_FPU64, ISA_EXT_SIMD_LASX} with
OPTION_MASK_ISA_DIV32 and OPTION_MASK_ISA_LD_SEQ_SA implied.
(loongarch_cpu_cache): Set [CPU_LA664] to la464_cache ().
The CPUCFG fields about cache are same on LA464 and LA664.
(loongarch_cpu_align): Set [CPU_LA664] to la464_align ().
This may be inaccurate and need an update.
(loongarch_cpu_issue_rate): Set [CPU_LA664] to 4.
This may be inaccurate and need an update.
(loongarch_cpu_multipass_dfa_lookahead): Set [CPU_LA664] to 4.
This may be inaccurate and need an update.
* config/loongarch/loongarch-opts.h (TARGET_uARCH_LA464): Return
true for -mtune=la664 for now.
---
.../loongarch/genopts/loongarch-strings | 1 +
gcc/config/loongarch/genopts/loongarch.opt.in | 3 +++
gcc/config/loongarch/loongarch-def.cc | 26 ++++++++++++++-----
gcc/config/loongarch/loongarch-def.h | 5 ++--
gcc/config/loongarch/loongarch-opts.h | 6 +++--
gcc/config/loongarch/loongarch-str.h | 1 +
gcc/config/loongarch/loongarch.opt | 3 +++
7 files changed, 35 insertions(+), 10 deletions(-)
diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings
index 8e412f7536e..7bc4824007e 100644
--- a/gcc/config/loongarch/genopts/loongarch-strings
+++ b/gcc/config/loongarch/genopts/loongarch-strings
@@ -26,6 +26,7 @@ STR_CPU_NATIVE native
STR_CPU_ABI_DEFAULT abi-default
STR_CPU_LOONGARCH64 loongarch64
STR_CPU_LA464 la464
+STR_CPU_LA664 la664
# Base architecture
STR_ISA_BASE_LA64V100 la64
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
index 4a22039681f..483b185b059 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -107,6 +107,9 @@ Enum(cpu_type) String(@@STR_CPU_LOONGARCH64@@) Value(CPU_LOONGARCH64)
EnumValue
Enum(cpu_type) String(@@STR_CPU_LA464@@) Value(CPU_LA464)
+EnumValue
+Enum(cpu_type) String(@@STR_CPU_LA664@@) Value(CPU_LA664)
+
m@@OPTSTR_ARCH@@=
Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPT_UNSET)
-m@@OPTSTR_ARCH@@=PROCESSOR Generate code for the given PROCESSOR ISA.
diff --git a/gcc/config/loongarch/loongarch-def.cc b/gcc/config/loongarch/loongarch-def.cc
index 9c2ec1ec135..cf8b66e9130 100644
--- a/gcc/config/loongarch/loongarch-def.cc
+++ b/gcc/config/loongarch/loongarch-def.cc
@@ -21,6 +21,8 @@ along with GCC; see the file COPYING3. If not see
#define IN_TARGET_CODE
#include "config.h"
#include "system.h"
+#include "coretypes.h"
+#include "options.h"
#include "loongarch-def.h"
#include "loongarch-str.h"
@@ -38,7 +40,8 @@ array_tune<const char *> loongarch_cpu_strings = array_tune<const char *> ()
.set (CPU_NATIVE, STR_CPU_NATIVE)
.set (CPU_ABI_DEFAULT, STR_CPU_ABI_DEFAULT)
.set (CPU_LOONGARCH64, STR_CPU_LOONGARCH64)
- .set (CPU_LA464, STR_CPU_LA464);
+ .set (CPU_LA464, STR_CPU_LA464)
+ .set (CPU_LA664, STR_CPU_LA664);
array_arch<loongarch_isa> loongarch_cpu_default_isa =
array_arch<loongarch_isa> ()
@@ -50,7 +53,14 @@ array_arch<loongarch_isa> loongarch_cpu_default_isa =
loongarch_isa ()
.base_ (ISA_BASE_LA64V100)
.fpu_ (ISA_EXT_FPU64)
- .simd_ (ISA_EXT_SIMD_LASX));
+ .simd_ (ISA_EXT_SIMD_LASX))
+ .set (CPU_LA664,
+ loongarch_isa ()
+ .base_ (ISA_BASE_LA64V100)
+ .fpu_ (ISA_EXT_FPU64)
+ .simd_ (ISA_EXT_SIMD_LASX)
+ .evol_add_feat (OPTION_MASK_ISA_DIV32)
+ .evol_add_feat (OPTION_MASK_ISA_LD_SEQ_SA));
static inline loongarch_cache la464_cache ()
{
@@ -64,7 +74,8 @@ static inline loongarch_cache la464_cache ()
array_tune<loongarch_cache> loongarch_cpu_cache =
array_tune<loongarch_cache> ()
.set (CPU_LOONGARCH64, la464_cache ())
- .set (CPU_LA464, la464_cache ());
+ .set (CPU_LA464, la464_cache ())
+ .set (CPU_LA664, la464_cache ()); /* not changed */
static inline loongarch_align la464_align ()
{
@@ -74,7 +85,8 @@ static inline loongarch_align la464_align ()
array_tune<loongarch_align> loongarch_cpu_align =
array_tune<loongarch_align> ()
.set (CPU_LOONGARCH64, la464_align ())
- .set (CPU_LA464, la464_align ());
+ .set (CPU_LA464, la464_align ())
+ .set (CPU_LA664, la464_align ());
#define COSTS_N_INSNS(N) ((N) * 4)
@@ -115,12 +127,14 @@ const loongarch_rtx_cost_data loongarch_rtx_cost_optimize_size =
array_tune<int> loongarch_cpu_issue_rate = array_tune<int> ()
.set (CPU_NATIVE, 4)
.set (CPU_LOONGARCH64, 4)
- .set (CPU_LA464, 4);
+ .set (CPU_LA464, 4)
+ .set (CPU_LA664, 4);
array_tune<int> loongarch_cpu_multipass_dfa_lookahead = array_tune<int> ()
.set (CPU_NATIVE, 4)
.set (CPU_LOONGARCH64, 4)
- .set (CPU_LA464, 4);
+ .set (CPU_LA464, 4)
+ .set (CPU_LA664, 4);
/* Wiring string definitions from loongarch-str.h to global arrays
with standard index values from loongarch-opts.h, so we can
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index e74036fda33..87a66d9ce30 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -156,8 +156,9 @@ struct loongarch_target
#define CPU_ABI_DEFAULT 1
#define CPU_LOONGARCH64 2
#define CPU_LA464 3
-#define N_ARCH_TYPES 4
-#define N_TUNE_TYPES 4
+#define CPU_LA664 4
+#define N_ARCH_TYPES 5
+#define N_TUNE_TYPES 5
/* parallel tables. */
extern loongarch_def_array<const char *, N_ARCH_TYPES>
diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h
index aa99e510282..9badecb7cb6 100644
--- a/gcc/config/loongarch/loongarch-opts.h
+++ b/gcc/config/loongarch/loongarch-opts.h
@@ -89,8 +89,10 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target,
#define ISA_HAS_LASX (la_target.isa.simd == ISA_EXT_SIMD_LASX)
-/* TARGET_ macros for use in *.md template conditionals */
-#define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464)
+/* TARGET_ macros for use in *.md template conditionals.
+ For now treat LA664 in the same way as LA464. */
+#define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464 || \
+ la_target.cpu_tune == CPU_LA664)
/* Note: optimize_size may vary across functions,
while -m[no]-memcpy imposes a global constraint. */
diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
index 3fa2ed5fc49..d9f4cc53d4c 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -30,6 +30,7 @@ along with GCC; see the file COPYING3. If not see
#define STR_CPU_ABI_DEFAULT "abi-default"
#define STR_CPU_LOONGARCH64 "loongarch64"
#define STR_CPU_LA464 "la464"
+#define STR_CPU_LA664 "la664"
#define STR_ISA_BASE_LA64V100 "la64"
diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index b17df1302f7..a8be307f92d 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -115,6 +115,9 @@ Enum(cpu_type) String(loongarch64) Value(CPU_LOONGARCH64)
EnumValue
Enum(cpu_type) String(la464) Value(CPU_LA464)
+EnumValue
+Enum(cpu_type) String(la664) Value(CPU_LA664)
+
march=
Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPT_UNSET)
-march=PROCESSOR Generate code for the given PROCESSOR ISA.
--
2.42.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/5] LoongArch: Initial LA664 support
2023-11-16 13:18 [PATCH 0/5] LoongArch: Initial LA664 support Xi Ruoyao
` (4 preceding siblings ...)
2023-11-16 13:18 ` [PATCH 5/5] LoongArch: Add -march=la664 and -mtune=la664 Xi Ruoyao
@ 2023-11-17 2:41 ` chenglulu
2023-11-17 4:55 ` Xi Ruoyao
5 siblings, 1 reply; 9+ messages in thread
From: chenglulu @ 2023-11-17 2:41 UTC (permalink / raw)
To: Xi Ruoyao, gcc-patches; +Cc: i, xuchenghua
[-- Attachment #1: Type: text/plain, Size: 4699 bytes --]
Hi,
Thank you very much for the modification, but I think we need to support
la664 with the configuration items of configure.
I also defined ISA_BASE_LA64V110 to represent the LoongArch1.1
instruction set, what do you think?
在 2023/11/16 下午9:18, Xi Ruoyao 写道:
> Loongson 3A6000 processor will be shipped to general users in this month
> and it features 4 cores with the new LA664 micro architecture. Here is
> some changes from LA464:
>
> 1. The 32-bit division instruction now ignores the high 32 bits of the
> input registers. This is enumerated via CPUCFG word 0x2, bit 26.
> 2. The micro architecture now guarantees two loads on the same memory
> address won't be reordered with each other. dbar 0x700 is turned
> into nop.
> 3. The architecture now supports approximate square root instructions
> (FRECIPE and VRSQRTE) on 32-bit or 64-bit floating-point values and
> the vectors of these values.
> 4. The architecture now supports SC.Q instruction for 128-bit CAS.
> 5. The architecture now supports LL.ACQ and SC.REL instructions (well, I
> don't really know what they are for).
> 6. The architecture now supports CAS instructions for 64, 32, 16, or 8-bit
> values.
> 7. The architecture now supports atomic add and atomic swap instructions
> for 16 or 8-bit values.
> 8. Some non-zero hint values of DBAR instructions are added.
>
> These features are documented in LoongArch v1.1. Implementations can
> implement any subset of them and enumerate the implemented features via
> CPUCFG. LA664 implements them all.
>
> (8) is already implemented in previous patches because it's completely
> backward-compatible. This series implements (1) and (2) with switches
> -mdiv32 and -mld-seq-sa (these names are derived from the names of the
> corresponding CPUCFG bits documented in the LoongArch v1.1
> specification).
>
> The other features require Binutils support and we are close to the end
> of GCC 14 stage 1, so I'm posting this series first now.
>
> With -march=la664, these two options are implicitly enabled but they can
> be turned off with -mno-div32 or -mno-ld-seq-sa.
>
> With -march=native, the current CPU is probed via CPUCFG and these
> options are implicitly enabled if the CPU supports the corresponding
> feature. They can be turned off with explicit -mno-div32 or
> -mno-ld-seq-sa as well.
>
> -mtune=la664 is implemented as a copy of -mtune=la464 and we can adjust
> it with benchmark results later.
>
> Bootstrapped and regtested on a LA664 with BOOT_CFLAGS="-march=la664
> -O2", a LA464 with BOOT_CFLAGS="-march=native -O2". And manually
> verified -march=native probing on LA664 and LA464.
>
> Xi Ruoyao (5):
> LoongArch: Switch loongarch-def to C++
> LoongArch: genopts: Add infrastructure to generate code for new
> features in ISA evolution
> LoongArch: Take the advantage of -mdiv32 if it's enabled
> LoongArch: Don't emit dbar 0x700 if -mld-seq-sa
> LoongArch: Add -march=la664 and -mtune=la664
>
> gcc/config/loongarch/genopts/genstr.sh | 78 ++++++-
> gcc/config/loongarch/genopts/isa-evolution.in | 2 +
> .../loongarch/genopts/loongarch-strings | 1 +
> gcc/config/loongarch/genopts/loongarch.opt.in | 10 +
> gcc/config/loongarch/loongarch-cpu.cc | 37 ++--
> gcc/config/loongarch/loongarch-cpucfg-map.h | 36 +++
> gcc/config/loongarch/loongarch-def-array.h | 40 ++++
> gcc/config/loongarch/loongarch-def.c | 205 ------------------
> gcc/config/loongarch/loongarch-def.cc | 193 +++++++++++++++++
> gcc/config/loongarch/loongarch-def.h | 67 ++++--
> gcc/config/loongarch/loongarch-opts.h | 9 +-
> gcc/config/loongarch/loongarch-str.h | 8 +-
> gcc/config/loongarch/loongarch-tune.h | 123 ++++++++++-
> gcc/config/loongarch/loongarch.cc | 6 +-
> gcc/config/loongarch/loongarch.md | 31 ++-
> gcc/config/loongarch/loongarch.opt | 23 +-
> gcc/config/loongarch/t-loongarch | 25 ++-
> .../gcc.target/loongarch/div-div32.c | 31 +++
> .../gcc.target/loongarch/div-no-div32.c | 11 +
> 19 files changed, 664 insertions(+), 272 deletions(-)
> create mode 100644 gcc/config/loongarch/genopts/isa-evolution.in
> create mode 100644 gcc/config/loongarch/loongarch-cpucfg-map.h
> create mode 100644 gcc/config/loongarch/loongarch-def-array.h
> delete mode 100644 gcc/config/loongarch/loongarch-def.c
> create mode 100644 gcc/config/loongarch/loongarch-def.cc
> create mode 100644 gcc/testsuite/gcc.target/loongarch/div-div32.c
> create mode 100644 gcc/testsuite/gcc.target/loongarch/div-no-div32.c
>
[-- Attachment #2: v1-0001-LoongArch-Add-LA664-support.patch --]
[-- Type: text/x-patch, Size: 12125 bytes --]
From a22073dc47602e4de7922efe66fd83d6196eb5f9 Mon Sep 17 00:00:00 2001
From: Lulu Cheng <chenglulu@loongson.cn>
Date: Thu, 16 Nov 2023 20:43:53 +0800
Subject: [PATCH v1 1/2] LoongArch: Add LA664 support.
Define ISA_BASE_LA64V110, which represents the base instruction set defined in LoongArch1.1.
Support the configure setting --with-arch =la664, and support -march=la664,-mtune=la664.
gcc/ChangeLog:
* config.gcc: Support LA664.
* config/loongarch/genopts/loongarch-strings: Likewise.
* config/loongarch/genopts/loongarch.opt.in: Likewise.
* config/loongarch/loongarch-cpu.cc (fill_native_cpu_config): Likewise.
* config/loongarch/loongarch-def.c: Likewise.
* config/loongarch/loongarch-def.h (N_ISA_BASE_TYPES): Likewise.
(ISA_BASE_LA64V110): Define macro.
(N_ARCH_TYPES): Update value.
(N_TUNE_TYPES): Update value.
(CPU_LA664): New macro.
* config/loongarch/loongarch-opts.cc (isa_default_abi): Likewise.
(isa_base_compat_p): Likewise.
* config/loongarch/loongarch-opts.h (TARGET_64BIT): This parameter is enabled
when la_target.isa.base is equal to ISA_BASE_LA64V100 or ISA_BASE_LA64V110.
(TARGET_uARCH_LA664): Define macro.
* config/loongarch/loongarch-str.h (STR_CPU_LA664): Likewise.
* config/loongarch/loongarch.cc (loongarch_cpu_sched_reassociation_width):
Add LA664 support.
* config/loongarch/loongarch.opt: Regenerate.
---
gcc/config.gcc | 10 ++++-----
.../loongarch/genopts/loongarch-strings | 1 +
gcc/config/loongarch/genopts/loongarch.opt.in | 3 +++
gcc/config/loongarch/loongarch-cpu.cc | 4 ++++
gcc/config/loongarch/loongarch-def.c | 21 +++++++++++++++++++
gcc/config/loongarch/loongarch-def.h | 8 ++++---
gcc/config/loongarch/loongarch-opts.cc | 8 +++----
gcc/config/loongarch/loongarch-opts.h | 4 +++-
gcc/config/loongarch/loongarch-str.h | 1 +
gcc/config/loongarch/loongarch.cc | 1 +
gcc/config/loongarch/loongarch.opt | 3 +++
11 files changed, 51 insertions(+), 13 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index c1460ca354e..5565fc24baa 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -5039,7 +5039,7 @@ case "${target}" in
# Perform initial sanity checks on --with-* options.
case ${with_arch} in
- "" | abi-default | loongarch64 | la464) ;; # OK, append here.
+ "" | abi-default | loongarch64 | la[46]64) ;; # OK, append here.
native)
if test x${host} != x${target}; then
echo "--with-arch=native is illegal for cross-compiler." 1>&2
@@ -5088,7 +5088,7 @@ case "${target}" in
case ${abi_base}/${abi_ext} in
lp64*/base)
# architectures that support lp64* ABI
- arch_pattern="native|abi-default|loongarch64|la464"
+ arch_pattern="native|abi-default|loongarch64|la[46]64"
# default architecture for lp64* ABI
arch_default="abi-default"
;;
@@ -5163,7 +5163,7 @@ case "${target}" in
# Check default with_tune configuration using with_arch.
case ${with_arch} in
loongarch64)
- tune_pattern="native|abi-default|loongarch64|la464"
+ tune_pattern="native|abi-default|loongarch64|la[46]64"
;;
*)
# By default, $with_tune == $with_arch
@@ -5219,7 +5219,7 @@ case "${target}" in
# Fixed: use the default gcc configuration for all multilib
# builds by default.
with_multilib_default="" ;;
- arch,native|arch,loongarch64|arch,la464) # OK, append here.
+ arch,native|arch,loongarch64|arch,la[46]64) # OK, append here.
with_multilib_default="/march=${component}" ;;
arch,*)
with_multilib_default="/march=abi-default"
@@ -5307,7 +5307,7 @@ case "${target}" in
if test x${parse_state} = x"arch"; then
# -march option
case ${component} in
- native | abi-default | loongarch64 | la464) # OK, append here.
+ native | abi-default | loongarch64 | la[46]64) # OK, append here.
# Append -march spec for each multilib variant.
loongarch_multilib_list_make="${loongarch_multilib_list_make}/march=${component}"
parse_state="opts"
diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings
index 8e412f7536e..7bc4824007e 100644
--- a/gcc/config/loongarch/genopts/loongarch-strings
+++ b/gcc/config/loongarch/genopts/loongarch-strings
@@ -26,6 +26,7 @@ STR_CPU_NATIVE native
STR_CPU_ABI_DEFAULT abi-default
STR_CPU_LOONGARCH64 loongarch64
STR_CPU_LA464 la464
+STR_CPU_LA664 la664
# Base architecture
STR_ISA_BASE_LA64V100 la64
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
index 158701d327a..00b4733d75b 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -107,6 +107,9 @@ Enum(cpu_type) String(@@STR_CPU_LOONGARCH64@@) Value(CPU_LOONGARCH64)
EnumValue
Enum(cpu_type) String(@@STR_CPU_LA464@@) Value(CPU_LA464)
+EnumValue
+Enum(cpu_type) String(@@STR_CPU_LA664@@) Value(CPU_LA664)
+
m@@OPTSTR_ARCH@@=
Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPT_UNSET)
-m@@OPTSTR_ARCH@@=PROCESSOR Generate code for the given PROCESSOR ISA.
diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc
index 7a2866f60f9..f3a13414143 100644
--- a/gcc/config/loongarch/loongarch-cpu.cc
+++ b/gcc/config/loongarch/loongarch-cpu.cc
@@ -106,6 +106,10 @@ fill_native_cpu_config (struct loongarch_target *tgt)
native_cpu_type = CPU_LA464;
break;
+ case 0x0014d000: /* LA664 */
+ native_cpu_type = CPU_LA664;
+ break;
+
default:
/* Unknown PRID. */
if (tune_native_p)
diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c
index 430ef8b2d95..067629141b6 100644
--- a/gcc/config/loongarch/loongarch-def.c
+++ b/gcc/config/loongarch/loongarch-def.c
@@ -28,6 +28,7 @@ loongarch_cpu_strings[N_TUNE_TYPES] = {
[CPU_ABI_DEFAULT] = STR_CPU_ABI_DEFAULT,
[CPU_LOONGARCH64] = STR_CPU_LOONGARCH64,
[CPU_LA464] = STR_CPU_LA464,
+ [CPU_LA664] = STR_CPU_LA664,
};
struct loongarch_isa
@@ -42,6 +43,11 @@ loongarch_cpu_default_isa[N_ARCH_TYPES] = {
.fpu = ISA_EXT_FPU64,
.simd = ISA_EXT_SIMD_LASX,
},
+ [CPU_LA664] = {
+ .base = ISA_BASE_LA64V110,
+ .fpu = ISA_EXT_FPU64,
+ .simd = ISA_EXT_SIMD_LASX,
+ },
};
struct loongarch_cache
@@ -58,6 +64,12 @@ loongarch_cpu_cache[N_TUNE_TYPES] = {
.l2d_size = 256,
.simultaneous_prefetches = 4,
},
+ [CPU_LA664] = {
+ .l1d_line_size = 64,
+ .l1d_size = 64,
+ .l2d_size = 256,
+ .simultaneous_prefetches = 4,
+ },
};
struct loongarch_align
@@ -70,6 +82,10 @@ loongarch_cpu_align[N_TUNE_TYPES] = {
.function = "32",
.label = "16",
},
+ [CPU_LA664] = {
+ .function = "32",
+ .label = "16",
+ },
};
@@ -104,6 +120,9 @@ loongarch_cpu_rtx_cost_data[N_TUNE_TYPES] = {
[CPU_LA464] = {
DEFAULT_COSTS
},
+ [CPU_LA664] = {
+ DEFAULT_COSTS
+ },
};
/* RTX costs to use when optimizing for size. */
@@ -127,6 +146,7 @@ loongarch_cpu_issue_rate[N_TUNE_TYPES] = {
[CPU_NATIVE] = 4,
[CPU_LOONGARCH64] = 4,
[CPU_LA464] = 4,
+ [CPU_LA664] = 6,
};
int
@@ -134,6 +154,7 @@ loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = {
[CPU_NATIVE] = 4,
[CPU_LOONGARCH64] = 4,
[CPU_LA464] = 4,
+ [CPU_LA664] = 6,
};
/* Wiring string definitions from loongarch-str.h to global arrays
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index 6e2a6987910..db497f3ffe2 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -55,7 +55,8 @@ extern "C" {
/* enum isa_base */
extern const char* loongarch_isa_base_strings[];
#define ISA_BASE_LA64V100 0
-#define N_ISA_BASE_TYPES 1
+#define ISA_BASE_LA64V110 1
+#define N_ISA_BASE_TYPES 2
/* enum isa_ext_* */
extern const char* loongarch_isa_ext_strings[];
@@ -141,8 +142,9 @@ struct loongarch_target
#define CPU_ABI_DEFAULT 1
#define CPU_LOONGARCH64 2
#define CPU_LA464 3
-#define N_ARCH_TYPES 4
-#define N_TUNE_TYPES 4
+#define CPU_LA664 4
+#define N_ARCH_TYPES 5
+#define N_TUNE_TYPES 5
/* parallel tables. */
extern const char* loongarch_cpu_strings[];
diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc
index e5921189a06..67a59152a01 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -552,17 +552,17 @@ isa_default_abi (const struct loongarch_isa *isa)
switch (isa->fpu)
{
case ISA_EXT_FPU64:
- if (isa->base == ISA_BASE_LA64V100)
+ if (isa->base >= ISA_BASE_LA64V100)
abi.base = ABI_BASE_LP64D;
break;
case ISA_EXT_FPU32:
- if (isa->base == ISA_BASE_LA64V100)
+ if (isa->base >= ISA_BASE_LA64V100)
abi.base = ABI_BASE_LP64F;
break;
case ISA_EXT_NONE:
- if (isa->base == ISA_BASE_LA64V100)
+ if (isa->base >= ISA_BASE_LA64V100)
abi.base = ABI_BASE_LP64S;
break;
@@ -582,7 +582,7 @@ isa_base_compat_p (const struct loongarch_isa *set1,
switch (set2->base)
{
case ISA_BASE_LA64V100:
- return (set1->base == ISA_BASE_LA64V100);
+ return (set1->base >= ISA_BASE_LA64V100);
default:
gcc_unreachable ();
diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h
index 8de41bbc4f7..bd2e86a5aa7 100644
--- a/gcc/config/loongarch/loongarch-opts.h
+++ b/gcc/config/loongarch/loongarch-opts.h
@@ -76,7 +76,8 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target,
#define TARGET_DOUBLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU64)
#define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D)
-#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100)
+#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100 \
+ || la_target.isa.base == ISA_BASE_LA64V110)
#define TARGET_ABI_LP64 (la_target.abi.base == ABI_BASE_LP64D \
|| la_target.abi.base == ABI_BASE_LP64F \
|| la_target.abi.base == ABI_BASE_LP64S)
@@ -88,6 +89,7 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target,
/* TARGET_ macros for use in *.md template conditionals */
#define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464)
+#define TARGET_uARCH_LA664 (la_target.cpu_tune == CPU_LA664)
/* Note: optimize_size may vary across functions,
while -m[no]-memcpy imposes a global constraint. */
diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
index 072558c28f1..fc4f41bfc1e 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -30,6 +30,7 @@ along with GCC; see the file COPYING3. If not see
#define STR_CPU_ABI_DEFAULT "abi-default"
#define STR_CPU_LOONGARCH64 "loongarch64"
#define STR_CPU_LA464 "la464"
+#define STR_CPU_LA664 "la664"
#define STR_ISA_BASE_LA64V100 "la64"
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 738911661d7..2793427fa61 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -10173,6 +10173,7 @@ loongarch_cpu_sched_reassociation_width (struct loongarch_target *target,
{
case CPU_LOONGARCH64:
case CPU_LA464:
+ case CPU_LA664:
/* Vector part. */
if (LSX_SUPPORTED_MODE_P (mode) || LASX_SUPPORTED_MODE_P (mode))
{
diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index a5988411fbb..7f129e53ba5 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -114,6 +114,9 @@ Enum(cpu_type) String(loongarch64) Value(CPU_LOONGARCH64)
EnumValue
Enum(cpu_type) String(la464) Value(CPU_LA464)
+EnumValue
+Enum(cpu_type) String(la664) Value(CPU_LA664)
+
march=
Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPT_UNSET)
-march=PROCESSOR Generate code for the given PROCESSOR ISA.
--
2.31.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/5] LoongArch: Initial LA664 support
2023-11-17 2:41 ` [PATCH 0/5] LoongArch: Initial LA664 support chenglulu
@ 2023-11-17 4:55 ` Xi Ruoyao
2023-11-17 6:07 ` chenglulu
0 siblings, 1 reply; 9+ messages in thread
From: Xi Ruoyao @ 2023-11-17 4:55 UTC (permalink / raw)
To: chenglulu, gcc-patches; +Cc: i, xuchenghua
On Fri, 2023-11-17 at 10:41 +0800, chenglulu wrote:
> Hi,
>
> Thank you very much for the modification, but I think we need to support
> la664 with the configuration items of configure.
I'll add it.
> I also defined ISA_BASE_LA64V110 to represent the LoongArch1.1
> instruction set, what do you think?
I'll add it too. I had misread section 1.5 paragraph 1 of the spec so I
didn't consider this a good idea, but after reading it again I think it
should be added.
> 在 2023/11/16 下午9:18, Xi Ruoyao 写道:
> > Loongson 3A6000 processor will be shipped to general users in this month
> > and it features 4 cores with the new LA664 micro architecture. Here is
> > some changes from LA464:
> >
> > 1. The 32-bit division instruction now ignores the high 32 bits of the
> > input registers. This is enumerated via CPUCFG word 0x2, bit 26.
> > 2. The micro architecture now guarantees two loads on the same memory
> > address won't be reordered with each other. dbar 0x700 is turned
> > into nop.
> > 3. The architecture now supports approximate square root instructions
> > (FRECIPE and VRSQRTE) on 32-bit or 64-bit floating-point values and
> > the vectors of these values.
> > 4. The architecture now supports SC.Q instruction for 128-bit CAS.
> > 5. The architecture now supports LL.ACQ and SC.REL instructions (well, I
> > don't really know what they are for).
> > 6. The architecture now supports CAS instructions for 64, 32, 16, or 8-bit
> > values.
> > 7. The architecture now supports atomic add and atomic swap instructions
> > for 16 or 8-bit values.
> > 8. Some non-zero hint values of DBAR instructions are added.
> >
> > These features are documented in LoongArch v1.1. Implementations can
> > implement any subset of them and enumerate the implemented features via
> > CPUCFG. LA664 implements them all.
> >
> > (8) is already implemented in previous patches because it's completely
> > backward-compatible. This series implements (1) and (2) with switches
> > -mdiv32 and -mld-seq-sa (these names are derived from the names of the
> > corresponding CPUCFG bits documented in the LoongArch v1.1
> > specification).
> >
> > The other features require Binutils support and we are close to the end
> > of GCC 14 stage 1, so I'm posting this series first now.
> >
> > With -march=la664, these two options are implicitly enabled but they can
> > be turned off with -mno-div32 or -mno-ld-seq-sa.
> >
> > With -march=native, the current CPU is probed via CPUCFG and these
> > options are implicitly enabled if the CPU supports the corresponding
> > feature. They can be turned off with explicit -mno-div32 or
> > -mno-ld-seq-sa as well.
> >
> > -mtune=la664 is implemented as a copy of -mtune=la464 and we can adjust
> > it with benchmark results later.
> >
> > Bootstrapped and regtested on a LA664 with BOOT_CFLAGS="-march=la664
> > -O2", a LA464 with BOOT_CFLAGS="-march=native -O2". And manually
> > verified -march=native probing on LA664 and LA464.
> >
> > Xi Ruoyao (5):
> > LoongArch: Switch loongarch-def to C++
> > LoongArch: genopts: Add infrastructure to generate code for new
> > features in ISA evolution
> > LoongArch: Take the advantage of -mdiv32 if it's enabled
> > LoongArch: Don't emit dbar 0x700 if -mld-seq-sa
> > LoongArch: Add -march=la664 and -mtune=la664
> >
> > gcc/config/loongarch/genopts/genstr.sh | 78 ++++++-
> > gcc/config/loongarch/genopts/isa-evolution.in | 2 +
> > .../loongarch/genopts/loongarch-strings | 1 +
> > gcc/config/loongarch/genopts/loongarch.opt.in | 10 +
> > gcc/config/loongarch/loongarch-cpu.cc | 37 ++--
> > gcc/config/loongarch/loongarch-cpucfg-map.h | 36 +++
> > gcc/config/loongarch/loongarch-def-array.h | 40 ++++
> > gcc/config/loongarch/loongarch-def.c | 205 ------------------
> > gcc/config/loongarch/loongarch-def.cc | 193 +++++++++++++++++
> > gcc/config/loongarch/loongarch-def.h | 67 ++++--
> > gcc/config/loongarch/loongarch-opts.h | 9 +-
> > gcc/config/loongarch/loongarch-str.h | 8 +-
> > gcc/config/loongarch/loongarch-tune.h | 123 ++++++++++-
> > gcc/config/loongarch/loongarch.cc | 6 +-
> > gcc/config/loongarch/loongarch.md | 31 ++-
> > gcc/config/loongarch/loongarch.opt | 23 +-
> > gcc/config/loongarch/t-loongarch | 25 ++-
> > .../gcc.target/loongarch/div-div32.c | 31 +++
> > .../gcc.target/loongarch/div-no-div32.c | 11 +
> > 19 files changed, 664 insertions(+), 272 deletions(-)
> > create mode 100644 gcc/config/loongarch/genopts/isa-evolution.in
> > create mode 100644 gcc/config/loongarch/loongarch-cpucfg-map.h
> > create mode 100644 gcc/config/loongarch/loongarch-def-array.h
> > delete mode 100644 gcc/config/loongarch/loongarch-def.c
> > create mode 100644 gcc/config/loongarch/loongarch-def.cc
> > create mode 100644 gcc/testsuite/gcc.target/loongarch/div-div32.c
> > create mode 100644 gcc/testsuite/gcc.target/loongarch/div-no-div32.c
> >
--
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/5] LoongArch: Initial LA664 support
2023-11-17 4:55 ` Xi Ruoyao
@ 2023-11-17 6:07 ` chenglulu
0 siblings, 0 replies; 9+ messages in thread
From: chenglulu @ 2023-11-17 6:07 UTC (permalink / raw)
To: Xi Ruoyao, gcc-patches; +Cc: i, xuchenghua
在 2023/11/17 下午12:55, Xi Ruoyao 写道:
> On Fri, 2023-11-17 at 10:41 +0800, chenglulu wrote:
>> Hi,
>>
>> Thank you very much for the modification, but I think we need to support
>> la664 with the configuration items of configure.
> I'll add it.
>
>> I also defined ISA_BASE_LA64V110 to represent the LoongArch1.1
>> instruction set, what do you think?
> I'll add it too. I had misread section 1.5 paragraph 1 of the spec so I
> didn't consider this a good idea, but after reading it again I think it
> should be added.
I have already added these two, but not on the basis of your patch. So...
>
>> 在 2023/11/16 下午9:18, Xi Ruoyao 写道:
>>> Loongson 3A6000 processor will be shipped to general users in this month
>>> and it features 4 cores with the new LA664 micro architecture. Here is
>>> some changes from LA464:
>>>
>>> 1. The 32-bit division instruction now ignores the high 32 bits of the
>>> input registers. This is enumerated via CPUCFG word 0x2, bit 26.
>>> 2. The micro architecture now guarantees two loads on the same memory
>>> address won't be reordered with each other. dbar 0x700 is turned
>>> into nop.
>>> 3. The architecture now supports approximate square root instructions
>>> (FRECIPE and VRSQRTE) on 32-bit or 64-bit floating-point values and
>>> the vectors of these values.
>>> 4. The architecture now supports SC.Q instruction for 128-bit CAS.
>>> 5. The architecture now supports LL.ACQ and SC.REL instructions (well, I
>>> don't really know what they are for).
>>> 6. The architecture now supports CAS instructions for 64, 32, 16, or 8-bit
>>> values.
>>> 7. The architecture now supports atomic add and atomic swap instructions
>>> for 16 or 8-bit values.
>>> 8. Some non-zero hint values of DBAR instructions are added.
>>>
>>> These features are documented in LoongArch v1.1. Implementations can
>>> implement any subset of them and enumerate the implemented features via
>>> CPUCFG. LA664 implements them all.
>>>
>>> (8) is already implemented in previous patches because it's completely
>>> backward-compatible. This series implements (1) and (2) with switches
>>> -mdiv32 and -mld-seq-sa (these names are derived from the names of the
>>> corresponding CPUCFG bits documented in the LoongArch v1.1
>>> specification).
>>>
>>> The other features require Binutils support and we are close to the end
>>> of GCC 14 stage 1, so I'm posting this series first now.
>>>
>>> With -march=la664, these two options are implicitly enabled but they can
>>> be turned off with -mno-div32 or -mno-ld-seq-sa.
>>>
>>> With -march=native, the current CPU is probed via CPUCFG and these
>>> options are implicitly enabled if the CPU supports the corresponding
>>> feature. They can be turned off with explicit -mno-div32 or
>>> -mno-ld-seq-sa as well.
>>>
>>> -mtune=la664 is implemented as a copy of -mtune=la464 and we can adjust
>>> it with benchmark results later.
>>>
>>> Bootstrapped and regtested on a LA664 with BOOT_CFLAGS="-march=la664
>>> -O2", a LA464 with BOOT_CFLAGS="-march=native -O2". And manually
>>> verified -march=native probing on LA664 and LA464.
>>>
>>> Xi Ruoyao (5):
>>> LoongArch: Switch loongarch-def to C++
>>> LoongArch: genopts: Add infrastructure to generate code for new
>>> features in ISA evolution
>>> LoongArch: Take the advantage of -mdiv32 if it's enabled
>>> LoongArch: Don't emit dbar 0x700 if -mld-seq-sa
>>> LoongArch: Add -march=la664 and -mtune=la664
>>>
>>> gcc/config/loongarch/genopts/genstr.sh | 78 ++++++-
>>> gcc/config/loongarch/genopts/isa-evolution.in | 2 +
>>> .../loongarch/genopts/loongarch-strings | 1 +
>>> gcc/config/loongarch/genopts/loongarch.opt.in | 10 +
>>> gcc/config/loongarch/loongarch-cpu.cc | 37 ++--
>>> gcc/config/loongarch/loongarch-cpucfg-map.h | 36 +++
>>> gcc/config/loongarch/loongarch-def-array.h | 40 ++++
>>> gcc/config/loongarch/loongarch-def.c | 205 ------------------
>>> gcc/config/loongarch/loongarch-def.cc | 193 +++++++++++++++++
>>> gcc/config/loongarch/loongarch-def.h | 67 ++++--
>>> gcc/config/loongarch/loongarch-opts.h | 9 +-
>>> gcc/config/loongarch/loongarch-str.h | 8 +-
>>> gcc/config/loongarch/loongarch-tune.h | 123 ++++++++++-
>>> gcc/config/loongarch/loongarch.cc | 6 +-
>>> gcc/config/loongarch/loongarch.md | 31 ++-
>>> gcc/config/loongarch/loongarch.opt | 23 +-
>>> gcc/config/loongarch/t-loongarch | 25 ++-
>>> .../gcc.target/loongarch/div-div32.c | 31 +++
>>> .../gcc.target/loongarch/div-no-div32.c | 11 +
>>> 19 files changed, 664 insertions(+), 272 deletions(-)
>>> create mode 100644 gcc/config/loongarch/genopts/isa-evolution.in
>>> create mode 100644 gcc/config/loongarch/loongarch-cpucfg-map.h
>>> create mode 100644 gcc/config/loongarch/loongarch-def-array.h
>>> delete mode 100644 gcc/config/loongarch/loongarch-def.c
>>> create mode 100644 gcc/config/loongarch/loongarch-def.cc
>>> create mode 100644 gcc/testsuite/gcc.target/loongarch/div-div32.c
>>> create mode 100644 gcc/testsuite/gcc.target/loongarch/div-no-div32.c
>>>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-11-17 6:08 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-16 13:18 [PATCH 0/5] LoongArch: Initial LA664 support Xi Ruoyao
2023-11-16 13:18 ` [PATCH 1/5] LoongArch: Switch loongarch-def to C++ Xi Ruoyao
2023-11-16 13:18 ` [PATCH 2/5] LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution Xi Ruoyao
2023-11-16 13:18 ` [PATCH 3/5] LoongArch: Take the advantage of -mdiv32 if it's enabled Xi Ruoyao
2023-11-16 13:18 ` [PATCH 4/5] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa Xi Ruoyao
2023-11-16 13:18 ` [PATCH 5/5] LoongArch: Add -march=la664 and -mtune=la664 Xi Ruoyao
2023-11-17 2:41 ` [PATCH 0/5] LoongArch: Initial LA664 support chenglulu
2023-11-17 4:55 ` Xi Ruoyao
2023-11-17 6:07 ` chenglulu
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