From: Jeff Law <jeffreyalaw@gmail.com>
To: 钟居哲 <juzhe.zhong@rivai.ai>, gcc-patches <gcc-patches@gcc.gnu.org>
Cc: "kito.cheng" <kito.cheng@gmail.com>, palmer <palmer@dabbelt.com>
Subject: Re: [PATCH] RISC-V: Fix RVV mask mode size
Date: Fri, 16 Dec 2022 18:53:49 -0700 [thread overview]
Message-ID: <75eb29fd-6449-e2d1-2702-d297373cecf3@gmail.com> (raw)
In-Reply-To: <27D1642B23C2C0D1+2022121709442960704166@rivai.ai>
On 12/16/22 18:44, 钟居哲 wrote:
> Yes, VNx4DF only has 4 bit in mask mode in case of load and store.
> For example vlm or vsm we will load store 8-bit ??? (I am not sure
> hardward can load store 4bit,but I am sure it definetly not load store
> the whole register size)
Most likely than not you end up loading a larger quantity with the high
bits zero'd. Interesting that we're using a packed model. I'd been
told it was fairly expensive to implement in hardware relative to teh
cost of implementing the sparse model.
> So ideally it should be model more accurate. However, since GCC assumes
> that 1 BOOL is 1-byte, the only thing I do is to model mask mode as
> smallest as possible.
> Maybe in the future, I can support 1BOOL for 1-bit?? I am not sure since
> it will need to change GCC framework.
I'm a bit confused by this. GCC can support single bit bools, though
ports often extend them to 8 bits or more for computational efficiency
purposes. At least that's the case in general. Is there something
particularly special about masks & bools that's causing problems?
Jeff
next prev parent reply other threads:[~2022-12-17 1:53 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-14 6:48 juzhe.zhong
2022-12-16 20:22 ` Jeff Law
2022-12-17 1:44 ` 钟居哲
2022-12-17 1:53 ` Jeff Law [this message]
2022-12-17 2:15 ` 钟居哲
2022-12-19 7:44 ` Richard Biener
2022-12-27 20:46 ` Jeff Law
2023-01-09 7:43 ` Richard Biener
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