From: 钟居哲 <juzhe.zhong@rivai.ai>
To: "Jeff Law" <jeffreyalaw@gmail.com>,
gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>,
kito.cheng <kito.cheng@sifive.com>, palmer <palmer@dabbelt.com>,
palmer <palmer@rivosinc.com>, rdapp.gcc <rdapp.gcc@gmail.com>
Subject: Re: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
Date: Thu, 29 Jun 2023 06:10:40 +0800 [thread overview]
Message-ID: <7A18980BD9E65F8A+202306290610400062820@rivai.ai> (raw)
In-Reply-To: <2abb91f5-36e0-5024-9b15-a45f8c40b4fe@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2362 bytes --]
Sure.
https://godbolt.org/z/8857KzTno
Failed to match this instruction:
(set (reg:VNx2DF 134 [ vect__31.47 ])
(fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [ vect__28.44 ])))
(reg:VNx2DF 150 [ vect__8.12 ])
(reg:VNx2DF 171 [ vect__29.45 ])))
juzhe.zhong@rivai.ai
From: Jeff Law
Date: 2023-06-29 02:16
To: Juzhe-Zhong; gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
On 6/28/23 05:55, Juzhe-Zhong wrote:
> Similar to vfwmacc. Add combine patterns as follows:
>
> For vfwnmsac:
> 1. (set (reg) (fma (neg (float_extend (reg))) (float_extend (reg))) (reg) )))
> 2. (set (reg) (fma (neg (float_extend (reg))) (reg) (reg) )))
>
> For vfwmsac:
> 1. (set (reg) (fma (float_extend (reg)) (float_extend (reg))) (neg (reg)) )))
> 2. (set (reg) (fma (float_extend (reg)) (reg) (neg (reg)) )))
>
> For vfwnmacc:
> 1. (set (reg) (fma (neg (float_extend (reg))) (float_extend (reg))) (neg (reg)) )))
> 2. (set (reg) (fma (neg (float_extend (reg))) (reg) (neg (reg)) )))
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md (*double_widen_fnma<mode>): New pattern.
> (*single_widen_fnma<mode>): Ditto.
> (*double_widen_fms<mode>): Ditto.
> (*single_widen_fms<mode>): Ditto.
> (*double_widen_fnms<mode>): Ditto.
> (*single_widen_fnms<mode>): Ditto.
>
> +
> +;; This helps to match ext + fnma.
> +(define_insn_and_split "*single_widen_fnma<mode>"
> + [(set (match_operand:VWEXTF 0 "register_operand")
> + (fma:VWEXTF
> + (neg:VWEXTF
> + (float_extend:VWEXTF
> + (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand")))
> + (match_operand:VWEXTF 3 "register_operand")
> + (match_operand:VWEXTF 1 "register_operand")))]
I'd like to understand this better. It looks like it's meant to be a
bridge to another pattern. However, it looks like it would be a 4->1
pattern without needing a bridge. So I'd like to know why that code
isn't working.
Can you send the before/after combine dumps which show this bridge
pattern being used?
The same concern exists with the other bridge patterns, but I don't
think I need to see the before/after for each of them.
Thanks,
Jeff
next prev parent reply other threads:[~2023-06-28 22:10 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-28 11:55 Juzhe-Zhong
2023-06-28 18:16 ` Jeff Law
2023-06-28 22:10 ` 钟居哲 [this message]
2023-06-28 22:43 ` Jeff Law
2023-06-28 22:56 ` 钟居哲
2023-06-29 23:43 ` Jeff Law
2023-06-30 1:14 ` juzhe.zhong
2023-06-30 1:26 ` Jeff Law
2023-06-30 1:32 ` juzhe.zhong
2023-07-03 7:48 ` Robin Dapp
2023-07-03 9:01 ` Kito Cheng
2023-07-03 9:12 ` juzhe.zhong
2023-07-03 9:27 ` Lehua Ding
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