From: Jeff Law <jeffreyalaw@gmail.com>
To: 钟居哲 <juzhe.zhong@rivai.ai>, gcc-patches <gcc-patches@gcc.gnu.org>
Cc: "kito.cheng" <kito.cheng@gmail.com>,
"kito.cheng" <kito.cheng@sifive.com>, palmer <palmer@dabbelt.com>,
palmer <palmer@rivosinc.com>, "rdapp.gcc" <rdapp.gcc@gmail.com>
Subject: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
Date: Wed, 28 Jun 2023 16:43:44 -0600 [thread overview]
Message-ID: <dc4aee0e-4ff6-b63f-831e-098d3555cc5d@gmail.com> (raw)
In-Reply-To: <7A18980BD9E65F8A+202306290610400062820@rivai.ai>
On 6/28/23 16:10, 钟居哲 wrote:
> Sure.
>
> https://godbolt.org/z/8857KzTno <https://godbolt.org/z/8857KzTno>
>
> Failed to match this instruction:
> (set (reg:VNx2DF 134 [ vect__31.47 ])
> (fma:VNx2DF (neg:VNx2DF (float_extend:VNx2DF (reg:VNx2SF 136 [
> vect__28.44 ])))
> (reg:VNx2DF 150 [ vect__8.12 ])
> (reg:VNx2DF 171 [ vect__29.45 ])))
Please attach the full dump. I would expect to see additional attempts
with more operands replaced.
jeff
next prev parent reply other threads:[~2023-06-28 22:43 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-28 11:55 Juzhe-Zhong
2023-06-28 18:16 ` Jeff Law
2023-06-28 22:10 ` 钟居哲
2023-06-28 22:43 ` Jeff Law [this message]
2023-06-28 22:56 ` 钟居哲
2023-06-29 23:43 ` Jeff Law
2023-06-30 1:14 ` juzhe.zhong
2023-06-30 1:26 ` Jeff Law
2023-06-30 1:32 ` juzhe.zhong
2023-07-03 7:48 ` Robin Dapp
2023-07-03 9:01 ` Kito Cheng
2023-07-03 9:12 ` juzhe.zhong
2023-07-03 9:27 ` Lehua Ding
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