From: "Jie Mei" <jie.mei@oss.cipunited.com>
To: <gcc-patches@gcc.gnu.org>
Subject: [PATCH v2 8/9] MIPS: Add CACHE instruction for mips16e2
Date: Fri, 12 May 2023 14:18:58 +0800 [thread overview]
Message-ID: <873b50976b7503863a13b747f3685c8481c7ef5c.1683871682.git.jie.mei@oss.cipunited.com> (raw)
In-Reply-To: <cover.1683871682.git.jie.mei@oss.cipunited.com>
[-- Attachment #1: Type: text/plain, Size: 6131 bytes --]
This patch adds CACHE instruction from mips16e2
with corresponding tests.
gcc/ChangeLog:
* config/mips/mips.c(mips_9bit_offset_address_p): Restrict the
address register to M16_REGS for MIPS16.
(BUILTIN_AVAIL_MIPS16E2): Defined a new macro.
(AVAIL_MIPS16E2_OR_NON_MIPS16): Same as above.
(AVAIL_NON_MIPS16 (cache..)): Update to
AVAIL_MIPS16E2_OR_NON_MIPS16.
* config/mips/mips.h (ISA_HAS_CACHE): Add clause for ISA_HAS_MIPS16E2.
* config/mips/mips.md (mips_cache): Mark as extended MIPS16.
gcc/testsuite/ChangeLog:
* gcc.target/mips/mips16e2-cache.c: New tests for mips16e2.
---
gcc/config/mips/mips.cc | 25 ++++++++++++--
gcc/config/mips/mips.h | 3 +-
gcc/config/mips/mips.md | 3 +-
.../gcc.target/mips/mips16e2-cache.c | 34 +++++++++++++++++++
4 files changed, 60 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cache.c
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 275efc5a390..e6f4701ad3a 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -2845,6 +2845,9 @@ mips_9bit_offset_address_p (rtx x, machine_mode mode)
return (mips_classify_address (&addr, x, mode, false)
&& addr.type == ADDRESS_REG
&& CONST_INT_P (addr.offset)
+ && (!TARGET_MIPS16E2
+ || M16_REG_P (REGNO (addr.reg))
+ || REGNO (addr.reg) >= FIRST_PSEUDO_REGISTER)
&& MIPS_9BIT_OFFSET_P (INTVAL (addr.offset)));
}
@@ -15412,9 +15415,13 @@ mips_loongson_ext2_prefetch_cookie (rtx write, rtx)
The function is available on the current target if !TARGET_MIPS16.
BUILTIN_AVAIL_MIPS16
- The function is available on the current target if TARGET_MIPS16. */
+ The function is available on the current target if TARGET_MIPS16.
+
+ BUILTIN_AVAIL_MIPS16E2
+ The function is available on the current target if TARGET_MIPS16E2. */
#define BUILTIN_AVAIL_NON_MIPS16 1
#define BUILTIN_AVAIL_MIPS16 2
+#define BUILTIN_AVAIL_MIPS16E2 4
/* Declare an availability predicate for built-in functions that
require non-MIPS16 mode and also require COND to be true.
@@ -15426,6 +15433,17 @@ mips_loongson_ext2_prefetch_cookie (rtx write, rtx)
return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
}
+/* Declare an availability predicate for built-in functions that
+ require non-MIPS16 mode or MIPS16E2 and also require COND to be true.
+ NAME is the main part of the predicate's name. */
+#define AVAIL_MIPS16E2_OR_NON_MIPS16(NAME, COND) \
+ static unsigned int \
+ mips_builtin_avail_##NAME (void) \
+ { \
+ return ((COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16E2 \
+ : 0); \
+ }
+
/* Declare an availability predicate for built-in functions that
support both MIPS16 and non-MIPS16 code and also require COND
to be true. NAME is the main part of the predicate's name. */
@@ -15471,7 +15489,7 @@ AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_MMI)
-AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
+AVAIL_MIPS16E2_OR_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
AVAIL_NON_MIPS16 (msa, TARGET_MSA)
/* Construct a mips_builtin_description from the given arguments.
@@ -17471,7 +17489,8 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
d = &mips_builtins[fcode];
avail = d->avail ();
gcc_assert (avail != 0);
- if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16))
+ if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16)
+ && (!TARGET_MIPS16E2 || !(avail & BUILTIN_AVAIL_MIPS16E2)))
{
error ("built-in function %qE not supported for MIPS16",
DECL_NAME (fndecl));
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 1947be25aca..207b8871b12 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1385,7 +1385,8 @@ struct mips_cpu_info {
#define TARGET_CACHE_BUILTIN (mips_isa >= MIPS_ISA_MIPS3)
/* The CACHE instruction is available. */
-#define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
+#define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && (!TARGET_MIPS16 \
+ || TARGET_MIPS16E2))
\f
/* Tell collect what flags to pass to nm. */
#ifndef NM_FLAGS
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 5ef8d99d99c..7eb65891820 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -5751,7 +5751,8 @@
(match_operand:QI 1 "address_operand" "ZD")]
UNSPEC_MIPS_CACHE))]
"ISA_HAS_CACHE"
- "cache\t%X0,%a1")
+ "cache\t%X0,%a1"
+ [(set_attr "extended_mips16" "yes")])
;; Similar, but with the operands hard-coded to an R10K cache barrier
;; operation. We keep the pattern distinct so that we can identify
diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cache.c b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c
new file mode 100644
index 00000000000..dcc39b580f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c
@@ -0,0 +1,34 @@
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips32r2 -mips16 -mmips16e2" } */
+/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
+
+/* Test cache. */
+
+void
+test01 (int *area)
+{
+ __builtin_mips_cache (20, area);
+}
+
+void
+test02 (const short *area)
+{
+ __builtin_mips_cache (24, area + 10);
+}
+
+void
+test03 (volatile unsigned int *area, int offset)
+{
+ __builtin_mips_cache (0, area + offset);
+}
+
+void
+test04 (const volatile unsigned char *area)
+{
+ __builtin_mips_cache (4, area - 80);
+}
+
+/* { dg-final { scan-assembler "\tcache\t0x14,0\\(\\\$4\\)" } } */
+/* { dg-final { scan-assembler "\tcache\t0x18,20\\(\\\$4\\)" } } */
+/* { dg-final { scan-assembler "\tcache\t(0x|)0,0\\(\\\$.\\)" } } */
+/* { dg-final { scan-assembler "\tcache\t0x4,-80\\(\\\$4\\)" } } */
+
--
2.40.1
next prev parent reply other threads:[~2023-05-12 6:19 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-12 6:18 [PATCH v2 0/9] MIPS: Add MIPS16e2 ASE instrucions Jie Mei
2023-05-12 6:18 ` [PATCH v2 1/9] MIPS: Add basic support for mips16e2 Jie Mei
2023-05-12 6:18 ` [PATCH v2 2/9] MIPS: Add MOVx instructions " Jie Mei
2023-05-12 6:18 ` [PATCH v2 3/9] MIPS: Add instruction about global pointer register " Jie Mei
2023-05-12 6:18 ` [PATCH v2 4/9] MIPS: Add bitwise instructions " Jie Mei
2023-05-12 6:18 ` [PATCH v2 5/9] MIPS: Add LUI instruction " Jie Mei
2023-05-12 6:18 ` [PATCH v2 6/9] MIPS: Add load/store word left/right instructions " Jie Mei
2023-05-12 6:18 ` [PATCH v2 7/9] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT " Jie Mei
2023-05-12 6:18 ` Jie Mei [this message]
2023-05-12 6:18 ` [PATCH v2 9/9] MIPS: Make mips16e2 generating ZEB/ZEH instead of ANDI under certain conditions Jie Mei
2023-05-19 11:27 ` [PATCH v2 0/9] MIPS: Add MIPS16e2 ASE instrucions Maciej W. Rozycki
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