[PATCH] [PR40457] [arm] expand SI-aligned movdi into pair of movsi

[PATCH] [PR40457] [arm] expand SI-aligned movdi into pair of movsi

[Alexandre Oliva]

When expanding a misaligned DImode move, emit aligned SImode moves if
the parts are sufficiently aligned.  This enables neighboring stores
to be peephole-combined into stm, as expected by the PR40457 testcase,
even after SLP vectorizes the originally aligned SImode stores into a
misaligned DImode store.

Regstraped on x86_64-linux-gnu, also tested with crosses to riscv64-elf
and arm-eabi (tms570).  Ok to install?


for  gcc/ChangeLog

	PR target/40457
	* config/arm/arm.md (movmisaligndi): Prefer aligned SImode
	moves.
---
 gcc/config/arm/arm.md |   12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 69bf343fb0ed6..a9eb0299aa761 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -12783,8 +12783,16 @@ (define_expand "movmisaligndi"
   rtx hi_op0 = gen_highpart_mode (SImode, DImode, operands[0]);
   rtx hi_op1 = gen_highpart_mode (SImode, DImode, operands[1]);
 
-  emit_insn (gen_movmisalignsi (lo_op0, lo_op1));
-  emit_insn (gen_movmisalignsi (hi_op0, hi_op1));
+  if (aligned_operand (lo_op0, SImode) && aligned_operand (lo_op1, SImode))
+    {
+      emit_move_insn (lo_op0, lo_op1);
+      emit_move_insn (hi_op0, hi_op1);
+    }
+  else
+    {
+      emit_insn (gen_movmisalignsi (lo_op0, lo_op1));
+      emit_insn (gen_movmisalignsi (hi_op0, hi_op1));
+    }
   DONE;
 })
 

-- 
Alexandre Oliva, happy hacker                https://FSFLA.org/blogs/lxo/
   Free Software Activist                       GNU Toolchain Engineer
Disinformation flourishes because many people care deeply about injustice
but very few check the facts.  Ask me about <https://stallmansupport.org>

Re: [PATCH] [PR40457] [arm] expand SI-aligned movdi into pair of movsi

[Richard Earnshaw]

On 02/12/2022 09:29, Alexandre Oliva via Gcc-patches wrote:
> 
> When expanding a misaligned DImode move, emit aligned SImode moves if
> the parts are sufficiently aligned.  This enables neighboring stores
> to be peephole-combined into stm, as expected by the PR40457 testcase,
> even after SLP vectorizes the originally aligned SImode stores into a
> misaligned DImode store.
> 
> Regstraped on x86_64-linux-gnu, also tested with crosses to riscv64-elf
> and arm-eabi (tms570).  Ok to install?
> 
> 
> for  gcc/ChangeLog
> 
> 	PR target/40457
> 	* config/arm/arm.md (movmisaligndi): Prefer aligned SImode
> 	moves.

OK.

R.

> ---
>   gcc/config/arm/arm.md |   12 ++++++++++--
>   1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
> index 69bf343fb0ed6..a9eb0299aa761 100644
> --- a/gcc/config/arm/arm.md
> +++ b/gcc/config/arm/arm.md
> @@ -12783,8 +12783,16 @@ (define_expand "movmisaligndi"
>     rtx hi_op0 = gen_highpart_mode (SImode, DImode, operands[0]);
>     rtx hi_op1 = gen_highpart_mode (SImode, DImode, operands[1]);
>   
> -  emit_insn (gen_movmisalignsi (lo_op0, lo_op1));
> -  emit_insn (gen_movmisalignsi (hi_op0, hi_op1));
> +  if (aligned_operand (lo_op0, SImode) && aligned_operand (lo_op1, SImode))
> +    {
> +      emit_move_insn (lo_op0, lo_op1);
> +      emit_move_insn (hi_op0, hi_op1);
> +    }
> +  else
> +    {
> +      emit_insn (gen_movmisalignsi (lo_op0, lo_op1));
> +      emit_insn (gen_movmisalignsi (hi_op0, hi_op1));
> +    }
>     DONE;
>   })
>   
>