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From: Robin Dapp <rdapp.gcc@gmail.com>
To: "Li, Pan2" <pan2.li@intel.com>,
	Thomas Schwinge <thomas@codesourcery.com>,
	Richard Biener <richard.guenther@gmail.com>,
	Jakub Jelinek <jakub@redhat.com>
Cc: rdapp.gcc@gmail.com,
	"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
	"richard.sandiford@arm.com" <richard.sandiford@arm.com>,
	"kito.cheng@gmail.com" <kito.cheng@gmail.com>,
	Jeff Law <jeffreyalaw@gmail.com>,
	"juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>,
	"Wang, Yanzhang" <yanzhang.wang@intel.com>
Subject: Re: Machine Mode ICE in RISC-V when LTO
Date: Fri, 15 Sep 2023 15:33:59 +0200	[thread overview]
Message-ID: <8c55be5d-3a6a-18bd-a054-072ecb28b949@gmail.com> (raw)
In-Reply-To: <MW5PR11MB59086029DC424E960242623BA910A@MW5PR11MB5908.namprd11.prod.outlook.com>

Hi Thomas, Jakub,

is there anything we can do to assist from the riscv side in order to help
with this?  I haven't really been involved with it but was wondering
what's missing.  If I understand correctly Thomas has a major cleanup
operation in plan but might not get to it soon.  The fix he proposed
helps for the riscv case, however, even without the rework?

If so, I'd kindly ping Jakub to check if the fix is reasonable.

Thank you.

Regards
 Robin

  reply	other threads:[~2023-09-15 13:34 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-12  5:00 [PATCH] Machine_Mode: Extend machine_mode from 8 to 16 bits pan2.li
2023-05-12  6:49 ` Richard Biener
2023-05-12 19:14   ` Bernhard Reutner-Fischer
2023-05-13  8:44     ` Kito Cheng
2023-05-13 12:26       ` Li, Pan2
2023-06-30 11:46       ` Adjust LTO mode tables for "Machine_Mode: Extend machine_mode from 8 to 16 bits" (was: [PATCH] Machine_Mode: Extend machine_mode from 8 to 16 bits) Thomas Schwinge
2023-06-30 12:45         ` Kito Cheng
2023-06-30 16:11           ` Thomas Schwinge
2023-06-30 16:37           ` Jakub Jelinek
2023-07-04 15:45             ` Thomas Schwinge
     [not found]         ` <MW5PR11MB590876BB7E52B78E837C95C9A913A@MW5PR11MB5908.namprd11.prod.outlook.com>
     [not found]           ` <CAFiYyc0Ajoi__g1YJhdrh-Z3DsOyU7+1iG6SEmZMDzAShX-L6g@mail.gmail.com>
     [not found]             ` <MW5PR11MB5908E5743F472D48ACF60039A913A@MW5PR11MB5908.namprd11.prod.outlook.com>
2023-08-10 13:23               ` Machine Mode ICE in RISC-V when LTO Thomas Schwinge
2023-08-10 14:14                 ` Li, Pan2
2023-08-11  6:40                   ` Li, Pan2
2023-09-15 13:33                     ` Robin Dapp [this message]
2023-09-18 14:46                       ` LTO: Get rid of 'lto_mode_identity_table' (was: Machine Mode ICE in RISC-V when LTO) Thomas Schwinge
2023-09-18 14:53                         ` Richard Biener
2023-05-12  8:24 ` [PATCH] Machine_Mode: Extend machine_mode from 8 to 16 bits Richard Sandiford
2023-05-12 11:16   ` Li, Pan2
2023-05-12 11:31     ` Richard Sandiford
2023-05-12 11:48       ` Li, Pan2
2023-05-16 15:35 ` pan2.li
2023-05-18  8:57   ` Richard Sandiford
2023-05-18  9:17     ` Li, Pan2
     [not found] <Message-Id: <20230512050016.476110-1-pan2.li@intel.com>
2023-05-12 15:38 ` [PATCH v2] " pan2.li
2023-05-13 13:13 ` [PATCH v3] " pan2.li
2023-05-16  1:12   ` Li, Pan2
2023-05-16  7:29     ` Richard Sandiford
2023-05-16  7:55       ` Li, Pan2
2023-05-16  8:03         ` Xi Ruoyao
2023-05-16  8:05           ` Li, Pan2
2023-05-16  9:09   ` Richard Sandiford
2023-05-16 12:17     ` Li, Pan2
2023-05-16 15:39       ` Li, Pan2

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