From: Richard Biener <richard.guenther@gmail.com>
To: Thomas Schwinge <thomas@codesourcery.com>
Cc: gcc-patches@gcc.gnu.org, Robin Dapp <rdapp.gcc@gmail.com>,
pan2.li@intel.com, Jakub Jelinek <jakub@redhat.com>,
richard.sandiford@arm.com, kito.cheng@gmail.com,
Jeff Law <jeffreyalaw@gmail.com>,
juzhe.zhong@rivai.ai, yanzhang.wang@intel.com
Subject: Re: LTO: Get rid of 'lto_mode_identity_table' (was: Machine Mode ICE in RISC-V when LTO)
Date: Mon, 18 Sep 2023 16:53:43 +0200 [thread overview]
Message-ID: <CAFiYyc3tkrqQAnLKGFPc55ehWF7KLfrmLF=9ZQW1VXbLU6jRqQ@mail.gmail.com> (raw)
In-Reply-To: <87il87bku2.fsf@euler.schwinge.homeip.net>
On Mon, Sep 18, 2023 at 4:46 PM Thomas Schwinge <thomas@codesourcery.com> wrote:
>
> Hi!
>
> On 2023-09-15T15:33:59+0200, Robin Dapp <rdapp.gcc@gmail.com> wrote:
> > is there anything we can do to assist from the riscv side in order to help
> > with this? I haven't really been involved with it but was wondering
> > what's missing. If I understand correctly Thomas has a major cleanup
> > operation in plan
>
> Not really major, but indeed non-trivial -- but WIP already. ;-)
>
> > but might not get to it soon.
>
> Right.
>
> > The fix he proposed
> > helps for the riscv case, however, even without the rework?
>
> Right, and no harm done for my work.
>
> > If so, I'd kindly ping Jakub to check if the fix is reasonable.
>
> I'll push the attached "LTO: Get rid of 'lto_mode_identity_table'"
> mid-week, unless any objections raised.
OK.
Richard.
>
> Grüße
> Thomas
>
>
> -----------------
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next prev parent reply other threads:[~2023-09-18 14:53 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-12 5:00 [PATCH] Machine_Mode: Extend machine_mode from 8 to 16 bits pan2.li
2023-05-12 6:49 ` Richard Biener
2023-05-12 19:14 ` Bernhard Reutner-Fischer
2023-05-13 8:44 ` Kito Cheng
2023-05-13 12:26 ` Li, Pan2
2023-06-30 11:46 ` Adjust LTO mode tables for "Machine_Mode: Extend machine_mode from 8 to 16 bits" (was: [PATCH] Machine_Mode: Extend machine_mode from 8 to 16 bits) Thomas Schwinge
2023-06-30 12:45 ` Kito Cheng
2023-06-30 16:11 ` Thomas Schwinge
2023-06-30 16:37 ` Jakub Jelinek
2023-07-04 15:45 ` Thomas Schwinge
[not found] ` <MW5PR11MB590876BB7E52B78E837C95C9A913A@MW5PR11MB5908.namprd11.prod.outlook.com>
[not found] ` <CAFiYyc0Ajoi__g1YJhdrh-Z3DsOyU7+1iG6SEmZMDzAShX-L6g@mail.gmail.com>
[not found] ` <MW5PR11MB5908E5743F472D48ACF60039A913A@MW5PR11MB5908.namprd11.prod.outlook.com>
2023-08-10 13:23 ` Machine Mode ICE in RISC-V when LTO Thomas Schwinge
2023-08-10 14:14 ` Li, Pan2
2023-08-11 6:40 ` Li, Pan2
2023-09-15 13:33 ` Robin Dapp
2023-09-18 14:46 ` LTO: Get rid of 'lto_mode_identity_table' (was: Machine Mode ICE in RISC-V when LTO) Thomas Schwinge
2023-09-18 14:53 ` Richard Biener [this message]
2023-05-12 8:24 ` [PATCH] Machine_Mode: Extend machine_mode from 8 to 16 bits Richard Sandiford
2023-05-12 11:16 ` Li, Pan2
2023-05-12 11:31 ` Richard Sandiford
2023-05-12 11:48 ` Li, Pan2
2023-05-16 15:35 ` pan2.li
2023-05-18 8:57 ` Richard Sandiford
2023-05-18 9:17 ` Li, Pan2
[not found] <Message-Id: <20230512050016.476110-1-pan2.li@intel.com>
2023-05-12 15:38 ` [PATCH v2] " pan2.li
2023-05-13 13:13 ` [PATCH v3] " pan2.li
2023-05-16 1:12 ` Li, Pan2
2023-05-16 7:29 ` Richard Sandiford
2023-05-16 7:55 ` Li, Pan2
2023-05-16 8:03 ` Xi Ruoyao
2023-05-16 8:05 ` Li, Pan2
2023-05-16 9:09 ` Richard Sandiford
2023-05-16 12:17 ` Li, Pan2
2023-05-16 15:39 ` Li, Pan2
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