Re: [PATCH v6 0/9] RISC-V: autovec: Add autovec support

[Kito Cheng <kito.cheng@gmail.com>]

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Errr, why you just mixed in JuZhe’s patch set into this patch set?

Michael Collison <collison@rivosinc.com>於 2023年5月5日 週五，23:47寫道：

> This series of patches adds foundational support for RISC-V
> auto-vectorization support. These patches are based on the current upstream
> rvv vector intrinsic support and is not a new implementation. Most of the
> implementation consists of adding the new vector cost model, the
> autovectorization patterns themselves and target hooks. This implementation
> only provides support for integer addition and subtraction as a proof of
> concept. This patch set should not be construed to be feature complete.
> Based on conversations with the community these patches are intended to lay
> the groundwork for feature completion and collaboration within the RISC-V
> community.
>
> These patches are largely based off the work of Juzhe Zhong (
> juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>) of RiVAI. More
> specifically the rvv-next branch at:
> https://github.com/riscv-collab/riscv-gcc.git <
> https://github.com/riscv-collab/riscv-gcc.git>is the foundation of this
> patch set.
>
> As discussed on this list, if these patches are approved they will be
> merged into a "auto-vectorization" branch once gcc-13 branches for release.
> There are two known issues related to crashes (assert failures) associated
> with tree vectorization; one of which I have sent a patch for and have
> received feedback.
>
> Changes in v6:
> - Incorporated upstream comments, added target hook for
> TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
>
> Changes in v5:
>
> - Incorporated upstream comments large to delete unnecessary code
>
> Changes in v4:
>
> - Added support for binary integer operations and test cases
> - Fixed bug to support 8-bit integer vectorization
> - Fixed several assert errors related to non-multiple of two vector modes
>
> Changes in v3:
>
> - Removed the cost model and cost hooks based on feedback from Richard
> Biener
> - Used RVV_VUNDEF macro to fix failing patterns
>
> Changes in v2
>
> - Updated ChangeLog entry to include RiVAI contributions
> - Fixed ChangeLog email formatting
> - Fixed gnu formatting issues in the code
>
> Kevin Lee (1):
>   RISC-V:autovec: This patch supports 8 bit auto-vectorization in riscv.
>
> Michael Collison (8):
>   RISC-V: Add new predicates and function prototypes
>   RISC-V: autovec: Export policy functions to global scope
>   RISC-V:autovec: Add auto-vectorization support functions
>   RISC-V:autovec: Add target vectorization hooks
>   RISC-V:autovec: Add autovectorization patterns for binary integer &
>     len_load/store
>   RISC-V:autovec: Add autovectorization tests for add & sub
>   vect: Verify that GET_MODE_NUNITS is a multiple of 2.
>   RISC-V:autovec: Add autovectorization tests for binary integer
>
>  gcc/config/riscv/riscv-opts.h                 |  10 ++
>  gcc/config/riscv/riscv-protos.h               |   9 ++
>  gcc/config/riscv/riscv-v.cc                   |  91 ++++++++++++
>  gcc/config/riscv/riscv-vector-builtins.cc     |   4 +-
>  gcc/config/riscv/riscv-vector-builtins.h      |   3 +
>  gcc/config/riscv/riscv.cc                     | 130 ++++++++++++++++++
>  gcc/config/riscv/riscv.md                     |   1 +
>  gcc/config/riscv/vector-auto.md               |  74 ++++++++++
>  gcc/config/riscv/vector.md                    |   4 +-
>  .../riscv/rvv/autovec/loop-add-rv32.c         |  25 ++++
>  .../gcc.target/riscv/rvv/autovec/loop-add.c   |  25 ++++
>  .../riscv/rvv/autovec/loop-and-rv32.c         |  25 ++++
>  .../gcc.target/riscv/rvv/autovec/loop-and.c   |  25 ++++
>  .../riscv/rvv/autovec/loop-div-rv32.c         |  27 ++++
>  .../gcc.target/riscv/rvv/autovec/loop-div.c   |  27 ++++
>  .../riscv/rvv/autovec/loop-max-rv32.c         |  26 ++++
>  .../gcc.target/riscv/rvv/autovec/loop-max.c   |  26 ++++
>  .../riscv/rvv/autovec/loop-min-rv32.c         |  26 ++++
>  .../gcc.target/riscv/rvv/autovec/loop-min.c   |  26 ++++
>  .../riscv/rvv/autovec/loop-mod-rv32.c         |  27 ++++
>  .../gcc.target/riscv/rvv/autovec/loop-mod.c   |  27 ++++
>  .../riscv/rvv/autovec/loop-mul-rv32.c         |  25 ++++
>  .../gcc.target/riscv/rvv/autovec/loop-mul.c   |  25 ++++
>  .../riscv/rvv/autovec/loop-or-rv32.c          |  25 ++++
>  .../gcc.target/riscv/rvv/autovec/loop-or.c    |  25 ++++
>  .../riscv/rvv/autovec/loop-sub-rv32.c         |  25 ++++
>  .../gcc.target/riscv/rvv/autovec/loop-sub.c   |  25 ++++
>  .../riscv/rvv/autovec/loop-xor-rv32.c         |  25 ++++
>  .../gcc.target/riscv/rvv/autovec/loop-xor.c   |  25 ++++
>  gcc/testsuite/gcc.target/riscv/rvv/rvv.exp    |   4 +
>  gcc/tree-vect-slp.cc                          |   7 +-
>  31 files changed, 843 insertions(+), 6 deletions(-)
>  create mode 100644 gcc/config/riscv/vector-auto.md
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c
>
> --
> 2.34.1
>
>