Re: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll

[Kito Cheng <kito.cheng@gmail.com>]

LGTM, thanks :)

On Thu, Apr 25, 2024 at 9:26 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> lgtm
>
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: pan2.li
> Date: 2024-04-25 09:25
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
> Subject: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
> From: Pan Li <pan2.li@intel.com>
>
> We missed the existing early clobber for the dest operand of vwsll
> pattern when resolve the conflict of revert register overlap.  Thus
> add it back to the pattern.  Unfortunately, we have no test to cover
> this part and will improve this after GCC-15 open.
>
> The below tests are passed for this patch:
> * The rv64gcv fully regression test with isl build.
>
> gcc/ChangeLog:
>
> * config/riscv/vector-crypto.md: Add early clobber to the
> dest operand of vwsll.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
> gcc/config/riscv/vector-crypto.md | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md
> index 8a4888a7653..e474ddf5da7 100755
> --- a/gcc/config/riscv/vector-crypto.md
> +++ b/gcc/config/riscv/vector-crypto.md
> @@ -303,7 +303,7 @@ (define_insn "@pred_vwsll<mode>"
>     (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> (define_insn "@pred_vwsll<mode>_scalar"
> -  [(set (match_operand:VWEXTI 0 "register_operand"              "=vr,     vr")
> +  [(set (match_operand:VWEXTI 0 "register_operand"              "=&vr,    &vr")
>       (if_then_else:VWEXTI
>         (unspec:<VM>
>           [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1, vmWc1")
> --
> 2.34.1
>
>