From: "Li, Pan2" <pan2.li@intel.com>
To: Kito Cheng <kito.cheng@gmail.com>,
"juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>, Robin Dapp <rdapp.gcc@gmail.com>
Subject: RE: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
Date: Thu, 25 Apr 2024 06:50:11 +0000 [thread overview]
Message-ID: <MW5PR11MB5908AE87BA82BFD011CF87C7A9172@MW5PR11MB5908.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CA+yXCZAgDaL8kdf6LrwtATZkuSE53JpRjKoa4DzwUm38P+xB4A@mail.gmail.com>
Committed, thanks Kito and Juzhe.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Thursday, April 25, 2024 2:24 PM
To: juzhe.zhong@rivai.ai
Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; Robin Dapp <rdapp.gcc@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
LGTM, thanks :)
On Thu, Apr 25, 2024 at 9:26 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> lgtm
>
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: pan2.li
> Date: 2024-04-25 09:25
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
> Subject: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
> From: Pan Li <pan2.li@intel.com>
>
> We missed the existing early clobber for the dest operand of vwsll
> pattern when resolve the conflict of revert register overlap. Thus
> add it back to the pattern. Unfortunately, we have no test to cover
> this part and will improve this after GCC-15 open.
>
> The below tests are passed for this patch:
> * The rv64gcv fully regression test with isl build.
>
> gcc/ChangeLog:
>
> * config/riscv/vector-crypto.md: Add early clobber to the
> dest operand of vwsll.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
> gcc/config/riscv/vector-crypto.md | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md
> index 8a4888a7653..e474ddf5da7 100755
> --- a/gcc/config/riscv/vector-crypto.md
> +++ b/gcc/config/riscv/vector-crypto.md
> @@ -303,7 +303,7 @@ (define_insn "@pred_vwsll<mode>"
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> (define_insn "@pred_vwsll<mode>_scalar"
> - [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr")
> + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr, &vr")
> (if_then_else:VWEXTI
> (unspec:<VM>
> [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
> --
> 2.34.1
>
>
prev parent reply other threads:[~2024-04-25 6:50 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-25 1:25 pan2.li
2024-04-25 1:25 ` juzhe.zhong
2024-04-25 6:23 ` Kito Cheng
2024-04-25 6:50 ` Li, Pan2 [this message]
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