* [PATCH] RISC-V:Fix a bug that is the CMO builtins are missing parameter
@ 2022-06-06 7:29 shiyulong
2022-06-06 9:05 ` Kito Cheng
0 siblings, 1 reply; 2+ messages in thread
From: shiyulong @ 2022-06-06 7:29 UTC (permalink / raw)
To: gcc-patches
Cc: andrew, palmer, kito.cheng, jim.wilson.gcc, wuwei2016, jiawei,
shihua, simon.cook, yulong
From: yulong <shiyulong@iscas.ac.cn>
We changed the RTL mode and builtins format about zicbom and zicboz subextensions.
gcc/ChangeLog:
* config/riscv/riscv-cmo.def (RISCV_BUILTIN): changed "RISCV_SI(DI)_FTYPE" to "RISCV_SI(DI)_FTPYE_SI(DI)"
* config/riscv/riscv-ftypes.def (0): deleted DEF_RISCV_FTYPE (0,(SI)) and DEF_RISCV_FTYPE (0,(DI))
* config/riscv/riscv.md: added a immediate_operand about cbo.clean, cbo.flush, cbo.inval and cbo.zero instructions
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cmo-zicbom-1.c: added a parameter
* gcc.target/riscv/cmo-zicbom-2.c: added a parameter
* gcc.target/riscv/cmo-zicboz-1.c: added a parameter
* gcc.target/riscv/cmo-zicboz-2.c: added a parameter
---
gcc/config/riscv/riscv-cmo.def | 16 ++++++++--------
gcc/config/riscv/riscv-ftypes.def | 2 --
gcc/config/riscv/riscv.md | 12 ++++++++----
gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 6 +++---
gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 6 +++---
gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c | 2 +-
7 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
index b30ecf96ec1..d43cbf62954 100644
--- a/gcc/config/riscv/riscv-cmo.def
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -1,16 +1,16 @@
// zicbom
-RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, clean32),
-RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, clean64),
+RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, clean32),
+RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, clean64),
-RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, flush32),
-RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, flush64),
+RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, flush32),
+RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, flush64),
-RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, inval32),
-RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, inval64),
+RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, inval32),
+RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, inval64),
// zicboz
-RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, zero32),
-RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, zero64),
+RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, zero32),
+RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, zero64),
// zicbop
RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, prefetchi32),
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index 62421292ce7..445eb8ee05d 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -28,7 +28,5 @@ along with GCC; see the file COPYING3. If not see
DEF_RISCV_FTYPE (0, (USI))
DEF_RISCV_FTYPE (1, (VOID, USI))
-DEF_RISCV_FTYPE (0, (SI))
-DEF_RISCV_FTYPE (0, (DI))
DEF_RISCV_FTYPE (1, (SI, SI))
DEF_RISCV_FTYPE (1, (DI, DI))
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b8ab0cf169a..2d7d94eebd3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2893,28 +2893,32 @@
[(set_attr "length" "12")])
(define_insn "riscv_clean_<mode>"
- [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+ [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
+ (match_operand:X 1 "immediate_operand" "i")]
UNSPECV_CLEAN)]
"TARGET_ZICBOM"
"cbo.clean\t%a0"
)
(define_insn "riscv_flush_<mode>"
- [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+ [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
+ (match_operand:X 1 "immediate_operand" "i")]
UNSPECV_FLUSH)]
"TARGET_ZICBOM"
"cbo.flush\t%a0"
)
(define_insn "riscv_inval_<mode>"
- [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+ [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
+ (match_operand:X 1 "immediate_operand" "i")]
UNSPECV_INVAL)]
"TARGET_ZICBOM"
"cbo.inval\t%a0"
)
(define_insn "riscv_zero_<mode>"
- [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+ [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
+ (match_operand:X 1 "immediate_operand" "i")]
UNSPECV_ZERO)]
"TARGET_ZICBOZ"
"cbo.zero\t%a0"
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
index e2ba2183511..eb68944418b 100644
--- a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
@@ -3,17 +3,17 @@
int foo1()
{
- return __builtin_riscv_zicbom_cbo_clean();
+ return __builtin_riscv_zicbom_cbo_clean(0);
}
int foo2()
{
- return __builtin_riscv_zicbom_cbo_flush();
+ return __builtin_riscv_zicbom_cbo_flush(0);
}
int foo3()
{
- return __builtin_riscv_zicbom_cbo_inval();
+ return __builtin_riscv_zicbom_cbo_inval(0);
}
/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
index a605e8b1bdc..3dc0f6d3368 100644
--- a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
@@ -3,17 +3,17 @@
int foo1()
{
- return __builtin_riscv_zicbom_cbo_clean();
+ return __builtin_riscv_zicbom_cbo_clean(0);
}
int foo2()
{
- return __builtin_riscv_zicbom_cbo_flush();
+ return __builtin_riscv_zicbom_cbo_flush(0);
}
int foo3()
{
- return __builtin_riscv_zicbom_cbo_inval();
+ return __builtin_riscv_zicbom_cbo_inval(0);
}
/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
index 96c1674ef2d..4726577f119 100644
--- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
@@ -3,7 +3,7 @@
int foo1()
{
- return __builtin_riscv_zicboz_cbo_zero();
+ return __builtin_riscv_zicboz_cbo_zero(0);
}
/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
index 9d99839b1e7..18d66b88515 100644
--- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
@@ -3,7 +3,7 @@
int foo1()
{
- return __builtin_riscv_zicboz_cbo_zero();
+ return __builtin_riscv_zicboz_cbo_zero(0);
}
/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */
--
2.17.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] RISC-V:Fix a bug that is the CMO builtins are missing parameter
2022-06-06 7:29 [PATCH] RISC-V:Fix a bug that is the CMO builtins are missing parameter shiyulong
@ 2022-06-06 9:05 ` Kito Cheng
0 siblings, 0 replies; 2+ messages in thread
From: Kito Cheng @ 2022-06-06 9:05 UTC (permalink / raw)
To: 史玉龙
Cc: GCC Patches, Andrew Waterman, jiawei, wuwei2016,
廖仕华
On Mon, Jun 6, 2022 at 3:29 PM <shiyulong@iscas.ac.cn> wrote:
>
> From: yulong <shiyulong@iscas.ac.cn>
>
> We changed the RTL mode and builtins format about zicbom and zicboz subextensions.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-cmo.def (RISCV_BUILTIN): changed "RISCV_SI(DI)_FTYPE" to "RISCV_SI(DI)_FTPYE_SI(DI)"
> * config/riscv/riscv-ftypes.def (0): deleted DEF_RISCV_FTYPE (0,(SI)) and DEF_RISCV_FTYPE (0,(DI))
> * config/riscv/riscv.md: added a immediate_operand about cbo.clean, cbo.flush, cbo.inval and cbo.zero instructions
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/cmo-zicbom-1.c: added a parameter
> * gcc.target/riscv/cmo-zicbom-2.c: added a parameter
> * gcc.target/riscv/cmo-zicboz-1.c: added a parameter
> * gcc.target/riscv/cmo-zicboz-2.c: added a parameter
>
> ---
> gcc/config/riscv/riscv-cmo.def | 16 ++++++++--------
> gcc/config/riscv/riscv-ftypes.def | 2 --
> gcc/config/riscv/riscv.md | 12 ++++++++----
> gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 6 +++---
> gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 6 +++---
> gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c | 2 +-
> gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c | 2 +-
> 7 files changed, 24 insertions(+), 22 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
> index b30ecf96ec1..d43cbf62954 100644
> --- a/gcc/config/riscv/riscv-cmo.def
> +++ b/gcc/config/riscv/riscv-cmo.def
> @@ -1,16 +1,16 @@
> // zicbom
> -RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, clean32),
> -RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, clean64),
> +RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, clean32),
> +RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, clean64),
That should be RISCV_VOID_FTYPE_SI and RISCV_VOID_FTYPE_DI, it takes
one argument but no return value.
>
> -RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, flush32),
> -RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, flush64),
> +RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, flush32),
> +RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, flush64),
>
> -RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, inval32),
> -RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, inval64),
> +RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, inval32),
> +RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, inval64),
>
> // zicboz
> -RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, zero32),
> -RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, zero64),
> +RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, zero32),
> +RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, zero64),
>
> // zicbop
> RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, prefetchi32),
> diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
> index 62421292ce7..445eb8ee05d 100644
> --- a/gcc/config/riscv/riscv-ftypes.def
> +++ b/gcc/config/riscv/riscv-ftypes.def
> @@ -28,7 +28,5 @@ along with GCC; see the file COPYING3. If not see
>
> DEF_RISCV_FTYPE (0, (USI))
> DEF_RISCV_FTYPE (1, (VOID, USI))
> -DEF_RISCV_FTYPE (0, (SI))
> -DEF_RISCV_FTYPE (0, (DI))
> DEF_RISCV_FTYPE (1, (SI, SI))
> DEF_RISCV_FTYPE (1, (DI, DI))
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index b8ab0cf169a..2d7d94eebd3 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -2893,28 +2893,32 @@
> [(set_attr "length" "12")])
>
> (define_insn "riscv_clean_<mode>"
> - [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
> + [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
> + (match_operand:X 1 "immediate_operand" "i")]
No need for a second input operand.
> UNSPECV_CLEAN)]
> "TARGET_ZICBOM"
> "cbo.clean\t%a0"
> )
>
> (define_insn "riscv_flush_<mode>"
> - [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
> + [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
> + (match_operand:X 1 "immediate_operand" "i")]
> UNSPECV_FLUSH)]
> "TARGET_ZICBOM"
> "cbo.flush\t%a0"
> )
>
> (define_insn "riscv_inval_<mode>"
> - [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
> + [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
> + (match_operand:X 1 "immediate_operand" "i")]
> UNSPECV_INVAL)]
> "TARGET_ZICBOM"
> "cbo.inval\t%a0"
> )
>
> (define_insn "riscv_zero_<mode>"
> - [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
> + [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
> + (match_operand:X 1 "immediate_operand" "i")]
> UNSPECV_ZERO)]
> "TARGET_ZICBOZ"
> "cbo.zero\t%a0"
> diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
> index e2ba2183511..eb68944418b 100644
> --- a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
> @@ -3,17 +3,17 @@
>
> int foo1()
> {
> - return __builtin_riscv_zicbom_cbo_clean();
> + return __builtin_riscv_zicbom_cbo_clean(0);
No return value for those cbo operations, and could you try to pass
some address other than 0 to the argument?
e.g.
int var;
void foo1()
{
__builtin_riscv_zicbom_cbo_clean(0);
__builtin_riscv_zicbom_cbo_clean(&var);
__builtin_riscv_zicbom_cbo_clean((void*)0x1234)
}
And also for cmo.flush, cmo.inval and cmo.zero.
> }
>
> int foo2()
> {
> - return __builtin_riscv_zicbom_cbo_flush();
> + return __builtin_riscv_zicbom_cbo_flush(0);
> }
>
> int foo3()
> {
> - return __builtin_riscv_zicbom_cbo_inval();
> + return __builtin_riscv_zicbom_cbo_inval(0);
> }
>
> /* { dg-final { scan-assembler-times "cbo.clean" 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
> index a605e8b1bdc..3dc0f6d3368 100644
> --- a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
> +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
> @@ -3,17 +3,17 @@
>
> int foo1()
> {
> - return __builtin_riscv_zicbom_cbo_clean();
> + return __builtin_riscv_zicbom_cbo_clean(0);
> }
>
> int foo2()
> {
> - return __builtin_riscv_zicbom_cbo_flush();
> + return __builtin_riscv_zicbom_cbo_flush(0);
> }
>
> int foo3()
> {
> - return __builtin_riscv_zicbom_cbo_inval();
> + return __builtin_riscv_zicbom_cbo_inval(0);
> }
>
> /* { dg-final { scan-assembler-times "cbo.clean" 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
> index 96c1674ef2d..4726577f119 100644
> --- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
> @@ -3,7 +3,7 @@
>
> int foo1()
> {
> - return __builtin_riscv_zicboz_cbo_zero();
> + return __builtin_riscv_zicboz_cbo_zero(0);
> }
>
> /* { dg-final { scan-assembler-times "cbo.zero" 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
> index 9d99839b1e7..18d66b88515 100644
> --- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
> +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
> @@ -3,7 +3,7 @@
>
> int foo1()
> {
> - return __builtin_riscv_zicboz_cbo_zero();
> + return __builtin_riscv_zicboz_cbo_zero(0);
> }
>
> /* { dg-final { scan-assembler-times "cbo.zero" 1 } } */
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2022-06-06 7:29 [PATCH] RISC-V:Fix a bug that is the CMO builtins are missing parameter shiyulong
2022-06-06 9:05 ` Kito Cheng
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