* [PATCH] aarch64: Update Ampere-1A (-mcpu=ampere1a) to include SM4
@ 2023-01-28 23:12 Philipp Tomsich
2023-01-30 14:18 ` Kyrylo Tkachov
0 siblings, 1 reply; 3+ messages in thread
From: Philipp Tomsich @ 2023-01-28 23:12 UTC (permalink / raw)
To: gcc-patches
Cc: Manolis Tsamis, Richard Sandiford, Tamar Christina, Philipp Tomsich
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Update
ampere1a to include SM4.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
gcc/config/aarch64/aarch64-cores.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index 2a0f52e1dd9..85fdfd8bf74 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -70,7 +70,7 @@ AARCH64_CORE("thunderxt83", thunderxt83, thunderx, V8A, (CRC, CRYPTO), thu
/* Ampere Computing ('\xC0') cores. */
AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (F16, RNG, AES, SHA3), ampere1, 0xC0, 0xac3, -1)
-AARCH64_CORE("ampere1a", ampere1a, cortexa57, V8_6A, (F16, RNG, AES, SHA3, MEMTAG), ampere1a, 0xC0, 0xac4, -1)
+AARCH64_CORE("ampere1a", ampere1a, cortexa57, V8_6A, (F16, RNG, AES, SHA3, SM4, MEMTAG), ampere1a, 0xC0, 0xac4, -1)
/* Do not swap around "emag" and "xgene1",
this order is required to handle variant correctly. */
AARCH64_CORE("emag", emag, xgene1, V8A, (CRC, CRYPTO), emag, 0x50, 0x000, 3)
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH] aarch64: Update Ampere-1A (-mcpu=ampere1a) to include SM4
2023-01-28 23:12 [PATCH] aarch64: Update Ampere-1A (-mcpu=ampere1a) to include SM4 Philipp Tomsich
@ 2023-01-30 14:18 ` Kyrylo Tkachov
2023-01-30 14:51 ` Philipp Tomsich
0 siblings, 1 reply; 3+ messages in thread
From: Kyrylo Tkachov @ 2023-01-30 14:18 UTC (permalink / raw)
To: Philipp Tomsich, gcc-patches
Cc: Manolis Tsamis, Richard Sandiford, Tamar Christina
> -----Original Message-----
> From: Gcc-patches <gcc-patches-
> bounces+kyrylo.tkachov=arm.com@gcc.gnu.org> On Behalf Of Philipp
> Tomsich
> Sent: Saturday, January 28, 2023 11:12 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Manolis Tsamis <manolis.tsamis@vrull.eu>; Richard Sandiford
> <Richard.Sandiford@arm.com>; Tamar Christina
> <Tamar.Christina@arm.com>; Philipp Tomsich <philipp.tomsich@vrull.eu>
> Subject: [PATCH] aarch64: Update Ampere-1A (-mcpu=ampere1a) to include
> SM4
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-cores.def (AARCH64_CORE): Update
> ampere1a to include SM4.
Ok, this looks consistent with what recently went in to LLVM.
Thanks,
Kyrill
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
>
> gcc/config/aarch64/aarch64-cores.def | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/aarch64/aarch64-cores.def
> b/gcc/config/aarch64/aarch64-cores.def
> index 2a0f52e1dd9..85fdfd8bf74 100644
> --- a/gcc/config/aarch64/aarch64-cores.def
> +++ b/gcc/config/aarch64/aarch64-cores.def
> @@ -70,7 +70,7 @@ AARCH64_CORE("thunderxt83", thunderxt83,
> thunderx, V8A, (CRC, CRYPTO), thu
>
> /* Ampere Computing ('\xC0') cores. */
> AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (F16, RNG, AES,
> SHA3), ampere1, 0xC0, 0xac3, -1)
> -AARCH64_CORE("ampere1a", ampere1a, cortexa57, V8_6A, (F16, RNG, AES,
> SHA3, MEMTAG), ampere1a, 0xC0, 0xac4, -1)
> +AARCH64_CORE("ampere1a", ampere1a, cortexa57, V8_6A, (F16, RNG, AES,
> SHA3, SM4, MEMTAG), ampere1a, 0xC0, 0xac4, -1)
> /* Do not swap around "emag" and "xgene1",
> this order is required to handle variant correctly. */
> AARCH64_CORE("emag", emag, xgene1, V8A, (CRC, CRYPTO), emag,
> 0x50, 0x000, 3)
> --
> 2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] aarch64: Update Ampere-1A (-mcpu=ampere1a) to include SM4
2023-01-30 14:18 ` Kyrylo Tkachov
@ 2023-01-30 14:51 ` Philipp Tomsich
0 siblings, 0 replies; 3+ messages in thread
From: Philipp Tomsich @ 2023-01-30 14:51 UTC (permalink / raw)
To: Kyrylo Tkachov
Cc: gcc-patches, Manolis Tsamis, Richard Sandiford, Tamar Christina
On Mon, 30 Jan 2023 at 15:18, Kyrylo Tkachov <Kyrylo.Tkachov@arm.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Gcc-patches <gcc-patches-
> > bounces+kyrylo.tkachov=arm.com@gcc.gnu.org> On Behalf Of Philipp
> > Tomsich
> > Sent: Saturday, January 28, 2023 11:12 PM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Manolis Tsamis <manolis.tsamis@vrull.eu>; Richard Sandiford
> > <Richard.Sandiford@arm.com>; Tamar Christina
> > <Tamar.Christina@arm.com>; Philipp Tomsich <philipp.tomsich@vrull.eu>
> > Subject: [PATCH] aarch64: Update Ampere-1A (-mcpu=ampere1a) to include
> > SM4
> >
> > gcc/ChangeLog:
> >
> > * config/aarch64/aarch64-cores.def (AARCH64_CORE): Update
> > ampere1a to include SM4.
>
> Ok, this looks consistent with what recently went in to LLVM.
> Thanks,
> Kyrill
Thanks, applied to master!
Philipp.
>
> >
> > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> > ---
> >
> > gcc/config/aarch64/aarch64-cores.def | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/gcc/config/aarch64/aarch64-cores.def
> > b/gcc/config/aarch64/aarch64-cores.def
> > index 2a0f52e1dd9..85fdfd8bf74 100644
> > --- a/gcc/config/aarch64/aarch64-cores.def
> > +++ b/gcc/config/aarch64/aarch64-cores.def
> > @@ -70,7 +70,7 @@ AARCH64_CORE("thunderxt83", thunderxt83,
> > thunderx, V8A, (CRC, CRYPTO), thu
> >
> > /* Ampere Computing ('\xC0') cores. */
> > AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (F16, RNG, AES,
> > SHA3), ampere1, 0xC0, 0xac3, -1)
> > -AARCH64_CORE("ampere1a", ampere1a, cortexa57, V8_6A, (F16, RNG, AES,
> > SHA3, MEMTAG), ampere1a, 0xC0, 0xac4, -1)
> > +AARCH64_CORE("ampere1a", ampere1a, cortexa57, V8_6A, (F16, RNG, AES,
> > SHA3, SM4, MEMTAG), ampere1a, 0xC0, 0xac4, -1)
> > /* Do not swap around "emag" and "xgene1",
> > this order is required to handle variant correctly. */
> > AARCH64_CORE("emag", emag, xgene1, V8A, (CRC, CRYPTO), emag,
> > 0x50, 0x000, 3)
> > --
> > 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-01-30 14:18 ` Kyrylo Tkachov
2023-01-30 14:51 ` Philipp Tomsich
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