Re: [PATCH v2 1/2] RISC-V: Add basic support for the Ventana-VT1 core

[Philipp Tomsich <philipp.tomsich@vrull.eu>]

Applied to master. Thanks!

Philipp.

On Mon, 14 Nov 2022 at 16:52, Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
> On 11/13/22 13:48, Philipp Tomsich wrote:
> > The Ventana-VT1 core is compatible with rv64gc, Zb[abcs], Zifenci and
> > XVentanaCondOps.
> > This introduces a placeholder -mcpu=ventana-vt1, so tooling and
> > scripts don't need to change once full support (pipeline, tuning,
> > etc.) will become public later.
> >
> > gcc/ChangeLog:
> >
> >       * config/riscv/riscv-cores.def (RISCV_TUNE): Add ventana-vt1.
> >       (RISCV_CORE): Ditto.
> >       * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Ditto.
> >       * config/riscv/riscv.cc: Add tune_info for ventana-vt1.
> >       * config/riscv/riscv.md: Add ventana-vt1.
> >       * doc/gcc/gcc-command-options/machine-dependent-options/risc-v-options.rst:
> >       Document -mcpu= and -mtune with ventana-vt1.
>
> OK.
>
>
> WRT the scheduler description.  I have one, but I think it's on the
> server at the vacation house which went offline a couple weeks ago and
> due to health reasons I haven't been up there to reset the internet
> connection.  Worst case I can just rebuild it from scratch, it's not
> that complex.
>
> Jeff