Re: [PATCH v2 2/2] RISC-V: Add instruction fusion (for ventana-vt1)

[Jakub Jelinek <jakub@redhat.com>]

On Mon, Nov 14, 2022 at 09:06:10AM -0700, Jeff Law via Gcc-patches wrote:
> 
> On 11/13/22 13:48, Philipp Tomsich wrote:
> > The Ventana VT1 core supports quad-issue and instruction fusion.
> > This implemented TARGET_SCHED_MACRO_FUSION_P to keep fusible sequences
> > together and adds idiom matcheing for the supported fusion cases.
> > 
> > gcc/ChangeLog:
> > 
> > 	* config/riscv/riscv.cc (enum riscv_fusion_pairs): Add symbolic
> > 	constants to identify supported fusion patterns.
> > 	(struct riscv_tune_param): Add fusible_op field.
> > 	(riscv_macro_fusion_p): Implement.
> > 	(riscv_fusion_enabled_p): Implement.
> > 	(riscv_macro_fusion_pair_p): Implement and recoginze fusible

s/recoginze/recognize/

> > 	idioms for Ventana VT1.
> > 	(TARGET_SCHED_MACRO_FUSION_P): Point to riscv_macro_fusion_p.
> > 	(TARGET_SCHED_MACRO_FUSION_PAIR_P): Point to riscv_macro_fusion_pair_p.
> 
> You know the fusion rules for VT1 better than I...  I'm happy to largely
> defer to you on this.
> 
> I do wonder if going forward hand matching RTL like this is going to be an
> unmaintainable mess and whether or not we would be better served using insn
> attributes to describe instruction fusion.

	Jakub