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From: "Christoph Müllner" <christoph.muellner@vrull.eu>
To: Hans-Peter Nilsson <hp@bitrange.com>
Cc: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@sifive.com>,
	 Jim Wilson <jim.wilson.gcc@gmail.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Andrew Waterman <andrew@sifive.com>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>,
	 Jeff Law <jeffreyalaw@gmail.com>,
	Cooper Qu <cooper.qu@linux.alibaba.com>,
	 Lifang Xia <lifang_xia@linux.alibaba.com>,
	Yunhai Shang <yunhai@linux.alibaba.com>,
	 Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH v3 04/11] riscv: thead: Add support for the XTheadBs ISA extension
Date: Tue, 28 Feb 2023 18:49:19 +0100	[thread overview]
Message-ID: <CAEg0e7hmSmOABX8nAbCV7Ca_QORG+4Oy1FRfC3h+YSX0VAB+Qw@mail.gmail.com> (raw)
In-Reply-To: <alpine.BSF.2.20.16.2302251827120.50502@arjuna.pair.com>

On Sun, Feb 26, 2023 at 12:42 AM Hans-Peter Nilsson <hp@bitrange.com> wrote:
>
> On Fri, 24 Feb 2023, Christoph Muellner wrote:
> > diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> > index 158e9124c3a..2c684885850 100644
> > --- a/gcc/config/riscv/thead.md
> > +++ b/gcc/config/riscv/thead.md
> > @@ -29,3 +29,14 @@ (define_insn "*th_addsl"
> >    "th.addsl\t%0,%3,%1,%2"
> >    [(set_attr "type" "bitmanip")
> >     (set_attr "mode" "<X:MODE>")])
> > +
> > +;; XTheadBs
> > +
> > +(define_insn "*th_tst"
> > +  [(set (match_operand:X 0 "register_operand" "=r")
> > +     (zero_extract:X (match_operand:X 1 "register_operand" "r")
> > +                     (const_int 1)
> > +                     (match_operand 2 "immediate_operand" "i")))]
>
> (Here and same elsewhere.)
>
> You're unlikely to get other constant operands in that pattern,
> but FWIW, the actual matching pair for just CONST_INT is
> "const_int_operand" for the predicate and "n" for the
> constraint.  Using the right predicate and constraint will also
> help the generated part of recog be a few nanoseconds faster. ;)

Thank you for that comment!
I think what you mean would look like this:

(define_insn "*th_tst"
  [(set (match_operand:X 0 "register_operand" "=r")
    (zero_extract:X (match_operand:X 1 "register_operand" "r")
            (match_operand 3 "const_int_operand" "n")
            (match_operand 2 "immediate_operand" "i")))]
  "TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)
   && UINTVAL (operands[3]) == 1"
  "th.tst\t%0,%1,%2"
  [(set_attr "type" "bitmanip")])

So while we have more generic form in the pattern, the condition needs
to check that the operand is equal to 1.

I can change this in the patch (I don't have strong opinions about
this and I do care about the nanosecond).
However, I think this goes beyond this patchset.
Because a single git grep shows many examples of "const_int " matches
in GCC's backends.
Examples can be found in gcc/config/riscv/bitmanip.md,
gcc/config/aarch64/aarch64.md,...
So it feels like changing the patch to use const_int_operand would go
against common practice.

@Kito: Any preferences about this?

Thanks,
Christoph

  reply	other threads:[~2023-02-28 17:49 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-24  5:51 [PATCH v3 00/11] RISC-V: Add XThead* extension support Christoph Muellner
2023-02-24  5:51 ` [PATCH v3 01/11] riscv: Add basic XThead* vendor " Christoph Muellner
2023-02-24  5:51 ` [PATCH v3 02/11] riscv: riscv-cores.def: Add T-Head XuanTie C906 Christoph Muellner
2023-02-24  5:51 ` [PATCH v3 03/11] riscv: thead: Add support for the XTheadBa ISA extension Christoph Muellner
2023-02-24  6:52   ` Andrew Pinski
2023-02-24  9:54     ` Kito Cheng
2023-02-24 10:05       ` Christoph Müllner
2023-02-24 10:47         ` Christoph Müllner
2023-02-24  5:51 ` [PATCH v3 04/11] riscv: thead: Add support for the XTheadBs " Christoph Muellner
2023-02-24  7:36   ` Kito Cheng
2023-02-24 10:21     ` Christoph Müllner
2023-02-25 23:42   ` Hans-Peter Nilsson
2023-02-28 17:49     ` Christoph Müllner [this message]
2023-03-01  0:19       ` Hans-Peter Nilsson
2023-03-01  7:49         ` Christoph Müllner
2023-02-24  5:51 ` [PATCH v3 05/11] riscv: thead: Add support for the XTheadBb " Christoph Muellner
2023-02-24  5:51 ` [PATCH v3 06/11] riscv: thead: Add support for the XTheadCondMov ISA extensions Christoph Muellner
2023-02-24  5:51 ` [PATCH v3 07/11] riscv: thead: Add support for the XTheadMac ISA extension Christoph Muellner
2023-02-24  5:51 ` [PATCH v3 08/11] riscv: thead: Add support for the XTheadFmv " Christoph Muellner
2023-02-24  5:51 ` [PATCH v3 09/11] riscv: thead: Add support for the XTheadMemPair " Christoph Muellner
2023-02-24  9:00   ` Kito Cheng
2023-02-24  9:33     ` Christoph Müllner
2023-02-24 15:48   ` Kito Cheng
2023-02-24  5:51 ` [PATCH v3 10/11] riscv: thead: Add support for the XTheadMemIdx " Christoph Muellner
2023-02-24  9:46   ` Kito Cheng
2023-02-24  5:51 ` [PATCH v3 11/11] riscv: thead: Add support for the XTheadFMemIdx " Christoph Muellner
2023-02-24  7:53   ` Kito Cheng
2023-02-24  9:46     ` Kito Cheng
2023-02-24  8:08 ` [PATCH v3 00/11] RISC-V: Add XThead* extension support Kito Cheng
2023-02-24 11:27   ` Christoph Müllner

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