From: "Christoph Müllner" <christoph.muellner@vrull.eu>
To: Kito Cheng <kito.cheng@gmail.com>
Cc: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Jeff Law <jeffreyalaw@gmail.com>,
Cooper Qu <cooper.qu@linux.alibaba.com>,
Lifang Xia <lifang_xia@linux.alibaba.com>,
Yunhai Shang <yunhai@linux.alibaba.com>,
Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH v3 00/11] RISC-V: Add XThead* extension support
Date: Fri, 24 Feb 2023 12:27:26 +0100 [thread overview]
Message-ID: <CAEg0e7j4LwDujgy6OPzH1-sJFyNVjtAapucvSZtKx1MQ0dTr7Q@mail.gmail.com> (raw)
In-Reply-To: <CA+yXCZBC-GLV2bV+fxXaoAsjHdUJ4OSqp9XWo8eTAtmLiFyCiw@mail.gmail.com>
On Fri, Feb 24, 2023 at 9:09 AM Kito Cheng <kito.cheng@gmail.com> wrote:
>
> Hi Christoph:
>
> OK for trunk for the 1~8, feel free to commit 1~8 after you address
> those minor comments, and could you also prepare release notes for
> those extensions?
I addressed the comment regarding XTheadBs.
But I have not done anything regarding XTheadB* and Zb*.
Release notes patch can be found here:
https://gcc.gnu.org/pipermail/gcc-patches/2023-February/612763.html
> And 9~11 needs to take a few more rounds of review and test.
I've seen the comments regarding patch 10 and 11.
We will try to clean this up asap.
In the patch for XTheadMemPair there was this nasty typo in one of the tests,
is there anything else that is needed?
I believe that patch should be in a better shape than the last two patches
and it is much less invasive.
Further similar code can be found in other backends.
Thanks,
Christoph
>
>
>
>
> On Fri, Feb 24, 2023 at 1:52 PM Christoph Muellner
> <christoph.muellner@vrull.eu> wrote:
> >
> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > This series introduces support for the T-Head specific RISC-V ISA extensions
> > which are available e.g. on the T-Head XuanTie C906.
> >
> > The ISA spec can be found here:
> > https://github.com/T-head-Semi/thead-extension-spec
> >
> > This series adds support for the following XThead* extensions:
> > * XTheadBa
> > * XTheadBb
> > * XTheadBs
> > * XTheadCmo
> > * XTheadCondMov
> > * XTheadFMemIdx
> > * XTheadFmv
> > * XTheadInt
> > * XTheadMac
> > * XTheadMemIdx
> > * XTheadMemPair
> > * XTheadSync
> >
> > All extensions are properly integrated and the included tests
> > demonstrate the improvements of the generated code.
> >
> > The series also introduces support for "-mcpu=thead-c906", which also
> > enables all available XThead* ISA extensions of the T-Head C906.
> >
> > All patches have been tested and don't introduce regressions for RV32 or RV64.
> > The patches have also been tested with SPEC CPU2017 on QEMU and real HW
> > (D1 board).
> >
> > Support patches for these extensions for Binutils, QEMU, and LLVM have
> > already been merged in the corresponding upstream projects.
> >
> > Changes in v3:
> > - Bugfix in XTheadBa
> > - Rewrite of XTheadMemPair
> > - Inclusion of XTheadMemIdx and XTheadFMemIdx
> >
> > Christoph Müllner (9):
> > riscv: Add basic XThead* vendor extension support
> > riscv: riscv-cores.def: Add T-Head XuanTie C906
> > riscv: thead: Add support for the XTheadBa ISA extension
> > riscv: thead: Add support for the XTheadBs ISA extension
> > riscv: thead: Add support for the XTheadBb ISA extension
> > riscv: thead: Add support for the XTheadCondMov ISA extensions
> > riscv: thead: Add support for the XTheadMac ISA extension
> > riscv: thead: Add support for the XTheadFmv ISA extension
> > riscv: thead: Add support for the XTheadMemPair ISA extension
> >
> > moiz.hussain (2):
> > riscv: thead: Add support for the XTheadMemIdx ISA extension
> > riscv: thead: Add support for the XTheadFMemIdx ISA extension
> >
> > gcc/common/config/riscv/riscv-common.cc | 26 +
> > gcc/config/riscv/bitmanip.md | 52 +-
> > gcc/config/riscv/constraints.md | 43 +
> > gcc/config/riscv/iterators.md | 4 +
> > gcc/config/riscv/peephole.md | 56 +
> > gcc/config/riscv/riscv-cores.def | 4 +
> > gcc/config/riscv/riscv-opts.h | 29 +
> > gcc/config/riscv/riscv-protos.h | 28 +-
> > gcc/config/riscv/riscv.cc | 1090 +++++++++++++++--
> > gcc/config/riscv/riscv.h | 8 +-
> > gcc/config/riscv/riscv.md | 169 ++-
> > gcc/config/riscv/riscv.opt | 3 +
> > gcc/config/riscv/thead.md | 351 ++++++
> > .../gcc.target/riscv/mcpu-thead-c906.c | 28 +
> > .../gcc.target/riscv/xtheadba-addsl.c | 55 +
> > gcc/testsuite/gcc.target/riscv/xtheadba.c | 14 +
> > gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c | 20 +
> > .../gcc.target/riscv/xtheadbb-extu-2.c | 22 +
> > .../gcc.target/riscv/xtheadbb-extu.c | 22 +
> > gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c | 18 +
> > gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c | 45 +
> > .../gcc.target/riscv/xtheadbb-srri.c | 21 +
> > gcc/testsuite/gcc.target/riscv/xtheadbb.c | 14 +
> > gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 13 +
> > gcc/testsuite/gcc.target/riscv/xtheadbs.c | 14 +
> > gcc/testsuite/gcc.target/riscv/xtheadcmo.c | 14 +
> > .../riscv/xtheadcondmov-mveqz-imm-eqz.c | 38 +
> > .../riscv/xtheadcondmov-mveqz-imm-not.c | 38 +
> > .../riscv/xtheadcondmov-mveqz-reg-eqz.c | 38 +
> > .../riscv/xtheadcondmov-mveqz-reg-not.c | 38 +
> > .../riscv/xtheadcondmov-mvnez-imm-cond.c | 38 +
> > .../riscv/xtheadcondmov-mvnez-imm-nez.c | 38 +
> > .../riscv/xtheadcondmov-mvnez-reg-cond.c | 38 +
> > .../riscv/xtheadcondmov-mvnez-reg-nez.c | 38 +
> > .../gcc.target/riscv/xtheadcondmov.c | 14 +
> > .../riscv/xtheadfmemidx-fldr-fstr.c | 58 +
> > .../gcc.target/riscv/xtheadfmemidx.c | 14 +
> > .../gcc.target/riscv/xtheadfmv-fmv.c | 24 +
> > gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 14 +
> > gcc/testsuite/gcc.target/riscv/xtheadint.c | 14 +
> > .../gcc.target/riscv/xtheadmac-mula-muls.c | 43 +
> > gcc/testsuite/gcc.target/riscv/xtheadmac.c | 14 +
> > .../gcc.target/riscv/xtheadmemidx-ldi-sdi.c | 72 ++
> > .../riscv/xtheadmemidx-ldr-str-32.c | 23 +
> > .../riscv/xtheadmemidx-ldr-str-64.c | 53 +
> > .../gcc.target/riscv/xtheadmemidx-macros.h | 110 ++
> > gcc/testsuite/gcc.target/riscv/xtheadmemidx.c | 14 +
> > .../gcc.target/riscv/xtheadmempair-1.c | 98 ++
> > .../gcc.target/riscv/xtheadmempair-2.c | 84 ++
> > .../gcc.target/riscv/xtheadmempair-3.c | 29 +
> > .../gcc.target/riscv/xtheadmempair.c | 13 +
> > gcc/testsuite/gcc.target/riscv/xtheadsync.c | 14 +
> > 52 files changed, 3048 insertions(+), 124 deletions(-)
> > create mode 100644 gcc/config/riscv/thead.md
> > create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-2.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcmo.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-fldr-fstr.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac-mula-muls.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-ldi-sdi.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-ldr-str-32.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-ldr-str-64.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-macros.h
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-1.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-2.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-3.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair.c
> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadsync.c
> >
> > --
> > 2.39.2
> >
prev parent reply other threads:[~2023-02-24 11:27 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-24 5:51 Christoph Muellner
2023-02-24 5:51 ` [PATCH v3 01/11] riscv: Add basic XThead* vendor " Christoph Muellner
2023-02-24 5:51 ` [PATCH v3 02/11] riscv: riscv-cores.def: Add T-Head XuanTie C906 Christoph Muellner
2023-02-24 5:51 ` [PATCH v3 03/11] riscv: thead: Add support for the XTheadBa ISA extension Christoph Muellner
2023-02-24 6:52 ` Andrew Pinski
2023-02-24 9:54 ` Kito Cheng
2023-02-24 10:05 ` Christoph Müllner
2023-02-24 10:47 ` Christoph Müllner
2023-02-24 5:51 ` [PATCH v3 04/11] riscv: thead: Add support for the XTheadBs " Christoph Muellner
2023-02-24 7:36 ` Kito Cheng
2023-02-24 10:21 ` Christoph Müllner
2023-02-25 23:42 ` Hans-Peter Nilsson
2023-02-28 17:49 ` Christoph Müllner
2023-03-01 0:19 ` Hans-Peter Nilsson
2023-03-01 7:49 ` Christoph Müllner
2023-02-24 5:51 ` [PATCH v3 05/11] riscv: thead: Add support for the XTheadBb " Christoph Muellner
2023-02-24 5:51 ` [PATCH v3 06/11] riscv: thead: Add support for the XTheadCondMov ISA extensions Christoph Muellner
2023-02-24 5:51 ` [PATCH v3 07/11] riscv: thead: Add support for the XTheadMac ISA extension Christoph Muellner
2023-02-24 5:51 ` [PATCH v3 08/11] riscv: thead: Add support for the XTheadFmv " Christoph Muellner
2023-02-24 5:51 ` [PATCH v3 09/11] riscv: thead: Add support for the XTheadMemPair " Christoph Muellner
2023-02-24 9:00 ` Kito Cheng
2023-02-24 9:33 ` Christoph Müllner
2023-02-24 15:48 ` Kito Cheng
2023-02-24 5:51 ` [PATCH v3 10/11] riscv: thead: Add support for the XTheadMemIdx " Christoph Muellner
2023-02-24 9:46 ` Kito Cheng
2023-02-24 5:51 ` [PATCH v3 11/11] riscv: thead: Add support for the XTheadFMemIdx " Christoph Muellner
2023-02-24 7:53 ` Kito Cheng
2023-02-24 9:46 ` Kito Cheng
2023-02-24 8:08 ` [PATCH v3 00/11] RISC-V: Add XThead* extension support Kito Cheng
2023-02-24 11:27 ` Christoph Müllner [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAEg0e7j4LwDujgy6OPzH1-sJFyNVjtAapucvSZtKx1MQ0dTr7Q@mail.gmail.com \
--to=christoph.muellner@vrull.eu \
--cc=andrew@sifive.com \
--cc=cooper.qu@linux.alibaba.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=jeffreyalaw@gmail.com \
--cc=jim.wilson.gcc@gmail.com \
--cc=kito.cheng@gmail.com \
--cc=kito.cheng@sifive.com \
--cc=lifang_xia@linux.alibaba.com \
--cc=palmer@dabbelt.com \
--cc=philipp.tomsich@vrull.eu \
--cc=yunhai@linux.alibaba.com \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).