* [PATCH] x86: Handle V16BF in ix86_avx256_split_vector_move_misalign
@ 2022-08-26 17:34 H.J. Lu
2022-08-26 17:34 ` H.J. Lu
2022-08-27 8:56 ` Uros Bizjak
0 siblings, 2 replies; 3+ messages in thread
From: H.J. Lu @ 2022-08-26 17:34 UTC (permalink / raw)
To: gcc-patches; +Cc: crazylht, Uros Bizjak, lingling.kong
Handle E_V16BFmode in ix86_avx256_split_vector_move_misalign and add
V16BF to V_256H iterator.
gcc/
PR target/106748
* config/i386/i386-expand.cc
(ix86_avx256_split_vector_move_misalign): Handle E_V16BFmode.
* config/i386/sse.md (V_256H): Add V16BF.
gcc/testsuite/
PR target/106748
* gcc.target/i386/pr106748.c: New test.
---
gcc/config/i386/i386-expand.cc | 4 ++++
gcc/config/i386/sse.md | 4 ++--
gcc/testsuite/gcc.target/i386/pr106748.c | 20 ++++++++++++++++++++
3 files changed, 26 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr106748.c
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 4b216308a18..836ebc82d67 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -745,6 +745,10 @@ ix86_avx256_split_vector_move_misalign (rtx op0, rtx op1)
extract = gen_avx_vextractf128v32qi;
mode = V16QImode;
break;
+ case E_V16BFmode:
+ extract = gen_avx_vextractf128v16bf;
+ mode = V8BFmode;
+ break;
case E_V16HFmode:
extract = gen_avx_vextractf128v16hf;
mode = V8HFmode;
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e6ab3c92dcf..259048481b6 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -297,9 +297,9 @@ (define_mode_iterator V_128
(define_mode_iterator V_256
[V32QI V16HI V8SI V4DI V8SF V4DF])
-;; All 256bit vector modes including HF vector mode
+;; All 256bit vector modes including HF/BF vector modes
(define_mode_iterator V_256H
- [V32QI V16HI V8SI V4DI V8SF V4DF V16HF])
+ [V32QI V16HI V8SI V4DI V8SF V4DF V16HF V16BF])
;; All 128bit and 256bit vector modes
(define_mode_iterator V_128_256
diff --git a/gcc/testsuite/gcc.target/i386/pr106748.c b/gcc/testsuite/gcc.target/i386/pr106748.c
new file mode 100644
index 00000000000..6388b1deb23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr106748.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx256-split-unaligned-store -mavx -fpack-struct" } */
+
+typedef __bf16 __m256bf16 __attribute__((__vector_size__(32)));
+typedef struct {
+ __m256bf16 _m256bf16[1];
+} YMM_T;
+
+struct {
+ YMM_T ymm0;
+} fregs;
+
+__m256bf16 do_test_u3b_0_0;
+int do_test_i;
+
+void
+do_test()
+{
+ (&fregs.ymm0)[do_test_i]._m256bf16[0] = do_test_u3b_0_0;
+}
--
2.37.2
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] x86: Handle V16BF in ix86_avx256_split_vector_move_misalign
2022-08-26 17:34 [PATCH] x86: Handle V16BF in ix86_avx256_split_vector_move_misalign H.J. Lu
@ 2022-08-26 17:34 ` H.J. Lu
2022-08-27 8:56 ` Uros Bizjak
1 sibling, 0 replies; 3+ messages in thread
From: H.J. Lu @ 2022-08-26 17:34 UTC (permalink / raw)
To: gcc-patches
Handle E_V16BFmode in ix86_avx256_split_vector_move_misalign and add
V16BF to V_256H iterator.
gcc/
PR target/106748
* config/i386/i386-expand.cc
(ix86_avx256_split_vector_move_misalign): Handle E_V16BFmode.
* config/i386/sse.md (V_256H): Add V16BF.
gcc/testsuite/
PR target/106748
* gcc.target/i386/pr106748.c: New test.
---
gcc/config/i386/i386-expand.cc | 4 ++++
gcc/config/i386/sse.md | 4 ++--
gcc/testsuite/gcc.target/i386/pr106748.c | 20 ++++++++++++++++++++
3 files changed, 26 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr106748.c
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 4b216308a18..836ebc82d67 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -745,6 +745,10 @@ ix86_avx256_split_vector_move_misalign (rtx op0, rtx op1)
extract = gen_avx_vextractf128v32qi;
mode = V16QImode;
break;
+ case E_V16BFmode:
+ extract = gen_avx_vextractf128v16bf;
+ mode = V8BFmode;
+ break;
case E_V16HFmode:
extract = gen_avx_vextractf128v16hf;
mode = V8HFmode;
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e6ab3c92dcf..259048481b6 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -297,9 +297,9 @@ (define_mode_iterator V_128
(define_mode_iterator V_256
[V32QI V16HI V8SI V4DI V8SF V4DF])
-;; All 256bit vector modes including HF vector mode
+;; All 256bit vector modes including HF/BF vector modes
(define_mode_iterator V_256H
- [V32QI V16HI V8SI V4DI V8SF V4DF V16HF])
+ [V32QI V16HI V8SI V4DI V8SF V4DF V16HF V16BF])
;; All 128bit and 256bit vector modes
(define_mode_iterator V_128_256
diff --git a/gcc/testsuite/gcc.target/i386/pr106748.c b/gcc/testsuite/gcc.target/i386/pr106748.c
new file mode 100644
index 00000000000..6388b1deb23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr106748.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx256-split-unaligned-store -mavx -fpack-struct" } */
+
+typedef __bf16 __m256bf16 __attribute__((__vector_size__(32)));
+typedef struct {
+ __m256bf16 _m256bf16[1];
+} YMM_T;
+
+struct {
+ YMM_T ymm0;
+} fregs;
+
+__m256bf16 do_test_u3b_0_0;
+int do_test_i;
+
+void
+do_test()
+{
+ (&fregs.ymm0)[do_test_i]._m256bf16[0] = do_test_u3b_0_0;
+}
--
2.37.2
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] x86: Handle V16BF in ix86_avx256_split_vector_move_misalign
2022-08-26 17:34 [PATCH] x86: Handle V16BF in ix86_avx256_split_vector_move_misalign H.J. Lu
2022-08-26 17:34 ` H.J. Lu
@ 2022-08-27 8:56 ` Uros Bizjak
1 sibling, 0 replies; 3+ messages in thread
From: Uros Bizjak @ 2022-08-27 8:56 UTC (permalink / raw)
To: H.J. Lu; +Cc: gcc-patches, crazylht, lingling.kong
On Fri, Aug 26, 2022 at 7:34 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> Handle E_V16BFmode in ix86_avx256_split_vector_move_misalign and add
> V16BF to V_256H iterator.
>
> gcc/
>
> PR target/106748
> * config/i386/i386-expand.cc
> (ix86_avx256_split_vector_move_misalign): Handle E_V16BFmode.
> * config/i386/sse.md (V_256H): Add V16BF.
>
> gcc/testsuite/
>
> PR target/106748
> * gcc.target/i386/pr106748.c: New test.
OK.
Thanks,
Uros.
>
> ---
> gcc/config/i386/i386-expand.cc | 4 ++++
> gcc/config/i386/sse.md | 4 ++--
> gcc/testsuite/gcc.target/i386/pr106748.c | 20 ++++++++++++++++++++
> 3 files changed, 26 insertions(+), 2 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr106748.c
>
> diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> index 4b216308a18..836ebc82d67 100644
> --- a/gcc/config/i386/i386-expand.cc
> +++ b/gcc/config/i386/i386-expand.cc
> @@ -745,6 +745,10 @@ ix86_avx256_split_vector_move_misalign (rtx op0, rtx op1)
> extract = gen_avx_vextractf128v32qi;
> mode = V16QImode;
> break;
> + case E_V16BFmode:
> + extract = gen_avx_vextractf128v16bf;
> + mode = V8BFmode;
> + break;
> case E_V16HFmode:
> extract = gen_avx_vextractf128v16hf;
> mode = V8HFmode;
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index e6ab3c92dcf..259048481b6 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -297,9 +297,9 @@ (define_mode_iterator V_128
> (define_mode_iterator V_256
> [V32QI V16HI V8SI V4DI V8SF V4DF])
>
> -;; All 256bit vector modes including HF vector mode
> +;; All 256bit vector modes including HF/BF vector modes
> (define_mode_iterator V_256H
> - [V32QI V16HI V8SI V4DI V8SF V4DF V16HF])
> + [V32QI V16HI V8SI V4DI V8SF V4DF V16HF V16BF])
>
> ;; All 128bit and 256bit vector modes
> (define_mode_iterator V_128_256
> diff --git a/gcc/testsuite/gcc.target/i386/pr106748.c b/gcc/testsuite/gcc.target/i386/pr106748.c
> new file mode 100644
> index 00000000000..6388b1deb23
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr106748.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O0 -mavx256-split-unaligned-store -mavx -fpack-struct" } */
> +
> +typedef __bf16 __m256bf16 __attribute__((__vector_size__(32)));
> +typedef struct {
> + __m256bf16 _m256bf16[1];
> +} YMM_T;
> +
> +struct {
> + YMM_T ymm0;
> +} fregs;
> +
> +__m256bf16 do_test_u3b_0_0;
> +int do_test_i;
> +
> +void
> +do_test()
> +{
> + (&fregs.ymm0)[do_test_i]._m256bf16[0] = do_test_u3b_0_0;
> +}
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-08-26 17:34 [PATCH] x86: Handle V16BF in ix86_avx256_split_vector_move_misalign H.J. Lu
2022-08-26 17:34 ` H.J. Lu
2022-08-27 8:56 ` Uros Bizjak
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