* [PATCH 1/2] Reimplement packuswb/packusdw with UNSPEC_US_TRUNCATE instead of original us_truncate. @ 2023-06-16 2:09 liuhongt 2023-06-16 2:09 ` [PATCH 2/2] Refined 256/512-bit vpacksswb/vpackssdw patterns liuhongt 2023-06-16 7:32 ` [PATCH 1/2] Reimplement packuswb/packusdw with UNSPEC_US_TRUNCATE instead of original us_truncate Uros Bizjak 0 siblings, 2 replies; 4+ messages in thread From: liuhongt @ 2023-06-16 2:09 UTC (permalink / raw) To: gcc-patches; +Cc: ubizjak packuswb/packusdw does unsigned saturation for signed source, but rtl us_truncate means does unsigned saturation for unsigned source. So for value -1, packuswb will produce 0, but us_truncate produces 255. The patch reimplement those related patterns and functions with UNSPEC_US_TRUNCATE instead of us_truncate. The patch will fix below testcase which failed after g:921b841350c4fc298d09f6c5674663e0f4208610 added constant-folding for US_TRUNCATE FAIL: gcc.target/i386/avx-vpackuswb-1.c execution test FAIL: gcc.target/i386/avx2-vpackusdw-2.c execution test FAIL: gcc.target/i386/avx2-vpackuswb-2.c execution test FAIL: gcc.target/i386/sse2-packuswb-1.c execution test Bootstrapped and regtested on x86_64-pc-linux-gnu. Ok for trunk? gcc/ChangeLog: PR target/110235 * config/i386/i386-expand.cc (ix86_split_mmx_pack): Use UNSPEC_US_TRUNCATE instead of original us_truncate for packusdw/packuswb. * config/i386/mmx.md (mmx_pack<s_trunsuffix>swb): Splitted to below 2 new patterns. (mmx_packsswb): New reload_completed define_insn_and_split. (mmx_packuswb): Ditto. (mmx_packusdw): Use UNSPEC_US_TRUNCATE instead of original us_truncate. (s_trunsuffix): Removed. (any_s_truncate): Removed. * config/i386/sse.md (<sse2_avx2>_packuswb<mask_name>): Use UNSPEC_US_TRUNCATE instead of original us_truncate. (<sse4_1_avx2>_packusdw<mask_name>): Ditto. * config/i386/i386.md (UNSPEC_US_TRUNCATE): New unspec_c_enum. --- gcc/config/i386/i386-expand.cc | 20 ++++++++++++---- gcc/config/i386/i386.md | 4 ++++ gcc/config/i386/mmx.md | 43 ++++++++++++++++++++++------------ gcc/config/i386/sse.md | 20 ++++++++-------- 4 files changed, 57 insertions(+), 30 deletions(-) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index def060ab562..35e2740f9b6 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -1019,6 +1019,7 @@ ix86_split_mmx_pack (rtx operands[], enum rtx_code code) rtx op0 = operands[0]; rtx op1 = operands[1]; rtx op2 = operands[2]; + rtx src; machine_mode dmode = GET_MODE (op0); machine_mode smode = GET_MODE (op1); @@ -1042,11 +1043,20 @@ ix86_split_mmx_pack (rtx operands[], enum rtx_code code) op1 = lowpart_subreg (sse_smode, op1, GET_MODE (op1)); op2 = lowpart_subreg (sse_smode, op2, GET_MODE (op2)); - op1 = gen_rtx_fmt_e (code, sse_half_dmode, op1); - op2 = gen_rtx_fmt_e (code, sse_half_dmode, op2); - rtx insn = gen_rtx_SET (dest, gen_rtx_VEC_CONCAT (sse_dmode, - op1, op2)); - emit_insn (insn); + /* For packusdw/packuswb, it does unsigned saturation for + signed source which is different for rtl US_TRUNCATE. */ + if (code == US_TRUNCATE) + src = gen_rtx_UNSPEC (sse_dmode, + gen_rtvec (2, op1, op2), + UNSPEC_US_TRUNCATE); + else + { + op1 = gen_rtx_fmt_e (code, sse_half_dmode, op1); + op2 = gen_rtx_fmt_e (code, sse_half_dmode, op2); + src = gen_rtx_VEC_CONCAT (sse_dmode, op1, op2); + } + + emit_move_insn (dest, src); ix86_move_vector_high_sse_to_mmx (op0); } diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 0929115ed4d..070a84d8af9 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -129,6 +129,10 @@ (define_c_enum "unspec" [ UNSPEC_RSQRT UNSPEC_PSADBW + ;; US_TRUNCATE this is different from rtl us_truncate, + ;; it does unsigned truncation for signed source. + UNSPEC_US_TRUNCATE + ;; For AVX/AVX512F support UNSPEC_SCALEF UNSPEC_PCMP diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 6fbe3909c8b..315eb4193c4 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -3337,27 +3337,41 @@ (define_split ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; Used in signed and unsigned truncations with saturation. -(define_code_iterator any_s_truncate [ss_truncate us_truncate]) -;; Instruction suffix for truncations with saturation. -(define_code_attr s_trunsuffix [(ss_truncate "s") (us_truncate "u")]) - -(define_insn_and_split "mmx_pack<s_trunsuffix>swb" +(define_insn_and_split "mmx_packsswb" [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw") (vec_concat:V8QI - (any_s_truncate:V4QI + (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0,0,Yw")) - (any_s_truncate:V4QI + (ss_truncate:V4QI (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))))] "TARGET_MMX || TARGET_MMX_WITH_SSE" "@ - pack<s_trunsuffix>swb\t{%2, %0|%0, %2} + packsswb\t{%2, %0|%0, %2} + # + #" + "&& reload_completed + && SSE_REGNO_P (REGNO (operands[0]))" + [(const_int 0)] + "ix86_split_mmx_pack (operands, SS_TRUNCATE); DONE;" + [(set_attr "mmx_isa" "native,sse_noavx,avx") + (set_attr "type" "mmxshft,sselog,sselog") + (set_attr "mode" "DI,TI,TI")]) + +(define_insn_and_split "mmx_packuswb" + [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw") + (unspec:V8QI + [(match_operand:V4HI 1 "register_operand" "0,0,Yw") + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")] + UNSPEC_US_TRUNCATE))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + packuswb\t{%2, %0|%0, %2} # #" "&& reload_completed && SSE_REGNO_P (REGNO (operands[0]))" [(const_int 0)] - "ix86_split_mmx_pack (operands, <any_s_truncate:CODE>); DONE;" + "ix86_split_mmx_pack (operands, US_TRUNCATE); DONE;" [(set_attr "mmx_isa" "native,sse_noavx,avx") (set_attr "type" "mmxshft,sselog,sselog") (set_attr "mode" "DI,TI,TI")]) @@ -3384,11 +3398,10 @@ (define_insn_and_split "mmx_packssdw" (define_insn_and_split "mmx_packusdw" [(set (match_operand:V4HI 0 "register_operand" "=Yr,*x,Yw") - (vec_concat:V4HI - (us_truncate:V2HI - (match_operand:V2SI 1 "register_operand" "0,0,Yw")) - (us_truncate:V2HI - (match_operand:V2SI 2 "register_operand" "Yr,*x,Yw"))))] + (unspec:V4HI + [(match_operand:V2SI 1 "register_operand" "0,0,Yw") + (match_operand:V2SI 2 "register_operand" "Yr,*x,Yw")] + UNSPEC_US_TRUNCATE))] "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE" "#" "&& reload_completed" diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 7d4b4ec8df5..83e3f534fd2 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -17796,13 +17796,14 @@ (define_insn "<sse2_avx2>_packssdw<mask_name>" (set_attr "prefix" "orig,<mask_prefix>") (set_attr "mode" "<sseinsnmode>")]) +;; This is different from rtl unsigned saturation, the instruction does +;; unsigned saturation for signed value. (define_insn "<sse2_avx2>_packuswb<mask_name>" [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,<v_Yw>") - (vec_concat:VI1_AVX512 - (us_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 1 "register_operand" "0,<v_Yw>")) - (us_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,<v_Yw>m"))))] + (unspec:VI1_AVX512 + [(match_operand:<sseunpackmode> 1 "register_operand" "0,<v_Yw>") + (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,<v_Yw>m")] + UNSPEC_US_TRUNCATE))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ packuswb\t{%2, %0|%0, %2} @@ -21889,11 +21890,10 @@ (define_insn "<sse4_1_avx2>_mpsadbw" (define_insn "<sse4_1_avx2>_packusdw<mask_name>" [(set (match_operand:VI2_AVX2 0 "register_operand" "=Yr,*x,<v_Yw>") - (vec_concat:VI2_AVX2 - (us_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 1 "register_operand" "0,0,<v_Yw>")) - (us_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 2 "vector_operand" "YrBm,*xBm,<v_Yw>m"))))] + (unspec:VI2_AVX2 + [(match_operand:<sseunpackmode> 1 "register_operand" "0,0,<v_Yw>") + (match_operand:<sseunpackmode> 2 "vector_operand" "YrBm,*xBm,<v_Yw>m")] + UNSPEC_US_TRUNCATE))] "TARGET_SSE4_1 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ packusdw\t{%2, %0|%0, %2} -- 2.39.1.388.g2fc9e9ca3c ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] Refined 256/512-bit vpacksswb/vpackssdw patterns. 2023-06-16 2:09 [PATCH 1/2] Reimplement packuswb/packusdw with UNSPEC_US_TRUNCATE instead of original us_truncate liuhongt @ 2023-06-16 2:09 ` liuhongt 2023-06-16 7:37 ` Uros Bizjak 2023-06-16 7:32 ` [PATCH 1/2] Reimplement packuswb/packusdw with UNSPEC_US_TRUNCATE instead of original us_truncate Uros Bizjak 1 sibling, 1 reply; 4+ messages in thread From: liuhongt @ 2023-06-16 2:09 UTC (permalink / raw) To: gcc-patches; +Cc: ubizjak The packing in vpacksswb/vpackssdw is not a simple concat, it's an interweave from src1 and src2 for every 128 bit(or 64-bit for the ss_truncate result). .i.e. dst[192-255] = ss_truncate (src2[128-255]) dst[128-191] = ss_truncate (src1[128-255]) dst[64-127] = ss_truncate (src2[0-127]) dst[0-63] = ss_truncate (src1[0-127] The patch refined those patterns with an extra vec_select for the interweave. The patch will fix below testcase which failed after g:921b841350c4fc298d09f6c5674663e0f4208610 added constant-folding for SS_TRUNCATE FAIL: gcc.target/i386/avx2-vpackssdw-2.c execution test. Bootstrapped and regtested on x86_64-pc-linux-gnu. Ok for trunk? gcc/ChangeLog: PR target/110235 * config/i386/sse.md (<sse2_avx2>_packsswb<mask_name>): Split to below 3 new define_insns. (sse2_packsswb<mask_name>): New define_insn. (avx2_packsswb<mask_name>): Ditto. (avx512bw_packsswb<mask_name>): Ditto. (<sse2_avx2>_packssdw<mask_name>): Split to below 3 new define_insns. (sse2_packssdw<mask_name>): New define_insn. (avx2_packssdw<mask_name>): Ditto. (avx512bw_packssdw<mask_name>): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512bw-vpackssdw-3.c: New test. * gcc.target/i386/avx512bw-vpacksswb-3.c: New test. --- gcc/config/i386/sse.md | 165 ++++++++++++++++-- .../gcc.target/i386/avx512bw-vpackssdw-3.c | 55 ++++++ .../gcc.target/i386/avx512bw-vpacksswb-3.c | 50 ++++++ 3 files changed, 252 insertions(+), 18 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 83e3f534fd2..cc4e4620257 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -17762,14 +17762,14 @@ (define_expand "vec_pack_sbool_trunc_qi" DONE; }) -(define_insn "<sse2_avx2>_packsswb<mask_name>" - [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,<v_Yw>") - (vec_concat:VI1_AVX512 - (ss_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 1 "register_operand" "0,<v_Yw>")) - (ss_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,<v_Yw>m"))))] - "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" +(define_insn "sse2_packsswb<mask_name>" + [(set (match_operand:V16QI 0 "register_operand" "=x,Yw") + (vec_concat:V16QI + (ss_truncate:V8QI + (match_operand:V8HI 1 "register_operand" "0,Yw")) + (ss_truncate:V8QI + (match_operand:V8HI 2 "vector_operand" "xBm,Ywm"))))] + "TARGET_SSE2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>" "@ packsswb\t{%2, %0|%0, %2} vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" @@ -17777,16 +17777,93 @@ (define_insn "<sse2_avx2>_packsswb<mask_name>" (set_attr "type" "sselog") (set_attr "prefix_data16" "1,*") (set_attr "prefix" "orig,<mask_prefix>") - (set_attr "mode" "<sseinsnmode>")]) + (set_attr "mode" "TI")]) -(define_insn "<sse2_avx2>_packssdw<mask_name>" - [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,<v_Yw>") - (vec_concat:VI2_AVX2 - (ss_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 1 "register_operand" "0,<v_Yw>")) - (ss_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,<v_Yw>m"))))] - "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" +(define_insn "avx2_packsswb<mask_name>" + [(set (match_operand:V32QI 0 "register_operand" "=Yw") + (vec_select:V32QI + (vec_concat:V32QI + (ss_truncate:V16QI + (match_operand:V16HI 1 "register_operand" "Yw")) + (ss_truncate:V16QI + (match_operand:V16HI 2 "vector_operand" "Ywm"))) + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 16) (const_int 17) + (const_int 18) (const_int 19) + (const_int 20) (const_int 21) + (const_int 22) (const_int 23) + (const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15) + (const_int 24) (const_int 25) + (const_int 26) (const_int 27) + (const_int 28) (const_int 29) + (const_int 30) (const_int 31)])))] + "TARGET_AVX2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>" + "vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" + [(set_attr "type" "sselog") + (set_attr "prefix" "<mask_prefix>") + (set_attr "mode" "OI")]) + +(define_insn "avx512bw_packsswb<mask_name>" + [(set (match_operand:V64QI 0 "register_operand" "=v") + (vec_select:V64QI + (vec_concat:V64QI + (ss_truncate:V32QI + (match_operand:V32HI 1 "register_operand" "v")) + (ss_truncate:V32QI + (match_operand:V32HI 2 "vector_operand" "vm"))) + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 32) (const_int 33) + (const_int 34) (const_int 35) + (const_int 36) (const_int 37) + (const_int 38) (const_int 39) + (const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15) + (const_int 40) (const_int 41) + (const_int 42) (const_int 43) + (const_int 44) (const_int 45) + (const_int 46) (const_int 47) + (const_int 16) (const_int 17) + (const_int 18) (const_int 19) + (const_int 20) (const_int 21) + (const_int 22) (const_int 23) + (const_int 48) (const_int 49) + (const_int 50) (const_int 51) + (const_int 52) (const_int 53) + (const_int 54) (const_int 55) + (const_int 24) (const_int 25) + (const_int 26) (const_int 27) + (const_int 28) (const_int 29) + (const_int 30) (const_int 31) + (const_int 56) (const_int 57) + (const_int 58) (const_int 59) + (const_int 60) (const_int 61) + (const_int 62) (const_int 63)])))] + + "TARGET_AVX512BW" + "vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" + [(set_attr "type" "sselog") + (set_attr "prefix" "<mask_prefix>") + (set_attr "mode" "XI")]) + +(define_insn "sse2_packssdw<mask_name>" + [(set (match_operand:V8HI 0 "register_operand" "=x,Yw") + (vec_concat:V8HI + (ss_truncate:V4HI + (match_operand:V4SI 1 "register_operand" "0,Yw")) + (ss_truncate:V4HI + (match_operand:V4SI 2 "vector_operand" "xBm,Ywm"))))] + "TARGET_SSE2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>" "@ packssdw\t{%2, %0|%0, %2} vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" @@ -17794,7 +17871,59 @@ (define_insn "<sse2_avx2>_packssdw<mask_name>" (set_attr "type" "sselog") (set_attr "prefix_data16" "1,*") (set_attr "prefix" "orig,<mask_prefix>") - (set_attr "mode" "<sseinsnmode>")]) + (set_attr "mode" "TI")]) + +(define_insn "avx2_packssdw<mask_name>" + [(set (match_operand:V16HI 0 "register_operand" "=Yw") + (vec_select:V16HI + (vec_concat:V16HI + (ss_truncate:V8HI + (match_operand:V8SI 1 "register_operand" "Yw")) + (ss_truncate:V8HI + (match_operand:V8SI 2 "vector_operand" "Ywm"))) + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15)])))] + "TARGET_AVX2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>" + "vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" + [(set_attr "type" "sselog") + (set_attr "prefix" "<mask_prefix>") + (set_attr "mode" "OI")]) + +(define_insn "avx512bw_packssdw<mask_name>" + [(set (match_operand:V32HI 0 "register_operand" "=v") + (vec_select:V32HI + (vec_concat:V32HI + (ss_truncate:V16HI + (match_operand:V16SI 1 "register_operand" "v")) + (ss_truncate:V16HI + (match_operand:V16SI 2 "vector_operand" "vm"))) + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 16) (const_int 17) + (const_int 18) (const_int 19) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 20) (const_int 21) + (const_int 22) (const_int 23) + (const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 24) (const_int 25) + (const_int 26) (const_int 27) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15) + (const_int 28) (const_int 29) + (const_int 30) (const_int 31)])))] + "TARGET_AVX512BW" + "vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" + [(set_attr "type" "sselog") + (set_attr "prefix" "<mask_prefix>") + (set_attr "mode" "XI")]) ;; This is different from rtl unsigned saturation, the instruction does ;; unsigned saturation for signed value. diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c b/gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c new file mode 100644 index 00000000000..ae839e8d2c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c @@ -0,0 +1,55 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512bw" } */ +/* { dg-require-effective-target avx512bw } */ + +#define AVX512BW +#include "avx512f-helper.h" + +#define DST_SIZE (AVX512F_LEN / 16) +#define SRC_SIZE (AVX512F_LEN / 32) + +#include "limits.h" + +#include "avx512f-mask-type.h" + +static short +int_to_short (int iVal) +{ + short sVal; + + if (iVal < -32768) + sVal = -32768; + else if (iVal > 32767) + sVal = 32767; + else + sVal = iVal; + + return sVal; +} + +void +TEST (void) +{ + union512i_d s1, s2; + union512i_w res1; + short dst_ref[32]; + int i; + + s1.x = _mm512_set_epi32 (1, 2, 3, 4, 65000, 20, 30, 90, 88, 44, 33, 22, 11, 98, 76, -65000); + s2.x = _mm512_set_epi32 (80, 40, 31, 21, 10, 99, 74, -65000, 2, 3, 4, 5, 65010, 21, 31, 91); + res1.x = _mm512_packs_epi32 (s1.x, s2.x); + for (int i = 0; i != 4; i++) + { + dst_ref[i] = int_to_short (s1.a[i]); + dst_ref[i + 4] = int_to_short (s2.a[i]); + dst_ref[i + 8] = int_to_short (s1.a[i + 4]); + dst_ref[i + 12] = int_to_short (s2.a[i + 4]); + dst_ref[i + 16] = int_to_short (s1.a[i + 8]); + dst_ref[i + 20] = int_to_short (s2.a[i + 8]); + dst_ref[i + 24] = int_to_short (s1.a[i + 12]); + dst_ref[i + 28] = int_to_short (s2.a[i + 12]); + } + + if (check_union512i_w (res1, dst_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c b/gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c new file mode 100644 index 00000000000..056c735ae0e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512bw" } */ +/* { dg-require-effective-target avx512bw } */ + +#define AVX512BW +#include "avx512f-helper.h" + +static char +short_to_byte (short iVal) +{ + short sVal; + + if (iVal < -128) + sVal = -128; + else if (iVal > 127) + sVal = 127; + else + sVal = iVal; + + return sVal; +} + +void +TEST (void) +{ + union512i_w s1, s2; + union512i_b res1; + char dst_ref[64]; + int i; + + s1.x = _mm512_set_epi16 (1, 2, 3, 4, 650, 20, 30, 90, 88, 44, 33, 22, 11, 98, 76, -650, + 128, 230, -112, -128, -3, -4, -7, 9, 10, 11, 12, 13, -223, 10, 8, 11); + s2.x = _mm512_set_epi16 (80, 40, 31, 21, 10, 99, 74, -650, 2, 3, 4, 5, 650, 21, 31, 91, + 280, -140, 310, 20, 9, 98, 73, -651, 3, 4, 5, 6, 651, 22, 32, 92); + res1.x = _mm512_packs_epi16 (s1.x, s2.x); + for (int i = 0; i != 8; i++) + { + dst_ref[i] = short_to_byte (s1.a[i]); + dst_ref[i + 8] = short_to_byte (s2.a[i]); + dst_ref[i + 16] = short_to_byte (s1.a[i + 8]); + dst_ref[i + 24] = short_to_byte (s2.a[i + 8]); + dst_ref[i + 32] = short_to_byte (s1.a[i + 16]); + dst_ref[i + 40] = short_to_byte (s2.a[i + 16]); + dst_ref[i + 48] = short_to_byte (s1.a[i + 24]); + dst_ref[i + 56] = short_to_byte (s2.a[i + 24]); + } + + if (check_union512i_b (res1, dst_ref)) + abort (); +} -- 2.39.1.388.g2fc9e9ca3c ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] Refined 256/512-bit vpacksswb/vpackssdw patterns. 2023-06-16 2:09 ` [PATCH 2/2] Refined 256/512-bit vpacksswb/vpackssdw patterns liuhongt @ 2023-06-16 7:37 ` Uros Bizjak 0 siblings, 0 replies; 4+ messages in thread From: Uros Bizjak @ 2023-06-16 7:37 UTC (permalink / raw) To: liuhongt; +Cc: gcc-patches On Fri, Jun 16, 2023 at 4:12 AM liuhongt <hongtao.liu@intel.com> wrote: > > The packing in vpacksswb/vpackssdw is not a simple concat, it's an > interweave from src1 and src2 for every 128 bit(or 64-bit for the > ss_truncate result). > > .i.e. > > dst[192-255] = ss_truncate (src2[128-255]) > dst[128-191] = ss_truncate (src1[128-255]) > dst[64-127] = ss_truncate (src2[0-127]) > dst[0-63] = ss_truncate (src1[0-127] > > The patch refined those patterns with an extra vec_select for the > interweave. > > The patch will fix below testcase which failed after > g:921b841350c4fc298d09f6c5674663e0f4208610 added constant-folding for SS_TRUNCATE > FAIL: gcc.target/i386/avx2-vpackssdw-2.c execution test. > > Bootstrapped and regtested on x86_64-pc-linux-gnu. > Ok for trunk? > > gcc/ChangeLog: > > PR target/110235 > * config/i386/sse.md (<sse2_avx2>_packsswb<mask_name>): Split > to below 3 new define_insns. > (sse2_packsswb<mask_name>): New define_insn. > (avx2_packsswb<mask_name>): Ditto. > (avx512bw_packsswb<mask_name>): Ditto. > (<sse2_avx2>_packssdw<mask_name>): Split to below 3 new define_insns. > (sse2_packssdw<mask_name>): New define_insn. > (avx2_packssdw<mask_name>): Ditto. > (avx512bw_packssdw<mask_name>): Ditto. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/avx512bw-vpackssdw-3.c: New test. > * gcc.target/i386/avx512bw-vpacksswb-3.c: New test. Please proofread and fix ChangeLog entry, in the same way as your previous patch. Otherwise LGTM. Thanks, Uros. > --- > gcc/config/i386/sse.md | 165 ++++++++++++++++-- > .../gcc.target/i386/avx512bw-vpackssdw-3.c | 55 ++++++ > .../gcc.target/i386/avx512bw-vpacksswb-3.c | 50 ++++++ > 3 files changed, 252 insertions(+), 18 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c > create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 83e3f534fd2..cc4e4620257 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -17762,14 +17762,14 @@ (define_expand "vec_pack_sbool_trunc_qi" > DONE; > }) > > -(define_insn "<sse2_avx2>_packsswb<mask_name>" > - [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,<v_Yw>") > - (vec_concat:VI1_AVX512 > - (ss_truncate:<ssehalfvecmode> > - (match_operand:<sseunpackmode> 1 "register_operand" "0,<v_Yw>")) > - (ss_truncate:<ssehalfvecmode> > - (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,<v_Yw>m"))))] > - "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" > +(define_insn "sse2_packsswb<mask_name>" > + [(set (match_operand:V16QI 0 "register_operand" "=x,Yw") > + (vec_concat:V16QI > + (ss_truncate:V8QI > + (match_operand:V8HI 1 "register_operand" "0,Yw")) > + (ss_truncate:V8QI > + (match_operand:V8HI 2 "vector_operand" "xBm,Ywm"))))] > + "TARGET_SSE2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>" > "@ > packsswb\t{%2, %0|%0, %2} > vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" > @@ -17777,16 +17777,93 @@ (define_insn "<sse2_avx2>_packsswb<mask_name>" > (set_attr "type" "sselog") > (set_attr "prefix_data16" "1,*") > (set_attr "prefix" "orig,<mask_prefix>") > - (set_attr "mode" "<sseinsnmode>")]) > + (set_attr "mode" "TI")]) > > -(define_insn "<sse2_avx2>_packssdw<mask_name>" > - [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,<v_Yw>") > - (vec_concat:VI2_AVX2 > - (ss_truncate:<ssehalfvecmode> > - (match_operand:<sseunpackmode> 1 "register_operand" "0,<v_Yw>")) > - (ss_truncate:<ssehalfvecmode> > - (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,<v_Yw>m"))))] > - "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" > +(define_insn "avx2_packsswb<mask_name>" > + [(set (match_operand:V32QI 0 "register_operand" "=Yw") > + (vec_select:V32QI > + (vec_concat:V32QI > + (ss_truncate:V16QI > + (match_operand:V16HI 1 "register_operand" "Yw")) > + (ss_truncate:V16QI > + (match_operand:V16HI 2 "vector_operand" "Ywm"))) > + (parallel [(const_int 0) (const_int 1) > + (const_int 2) (const_int 3) > + (const_int 4) (const_int 5) > + (const_int 6) (const_int 7) > + (const_int 16) (const_int 17) > + (const_int 18) (const_int 19) > + (const_int 20) (const_int 21) > + (const_int 22) (const_int 23) > + (const_int 8) (const_int 9) > + (const_int 10) (const_int 11) > + (const_int 12) (const_int 13) > + (const_int 14) (const_int 15) > + (const_int 24) (const_int 25) > + (const_int 26) (const_int 27) > + (const_int 28) (const_int 29) > + (const_int 30) (const_int 31)])))] > + "TARGET_AVX2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>" > + "vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" > + [(set_attr "type" "sselog") > + (set_attr "prefix" "<mask_prefix>") > + (set_attr "mode" "OI")]) > + > +(define_insn "avx512bw_packsswb<mask_name>" > + [(set (match_operand:V64QI 0 "register_operand" "=v") > + (vec_select:V64QI > + (vec_concat:V64QI > + (ss_truncate:V32QI > + (match_operand:V32HI 1 "register_operand" "v")) > + (ss_truncate:V32QI > + (match_operand:V32HI 2 "vector_operand" "vm"))) > + (parallel [(const_int 0) (const_int 1) > + (const_int 2) (const_int 3) > + (const_int 4) (const_int 5) > + (const_int 6) (const_int 7) > + (const_int 32) (const_int 33) > + (const_int 34) (const_int 35) > + (const_int 36) (const_int 37) > + (const_int 38) (const_int 39) > + (const_int 8) (const_int 9) > + (const_int 10) (const_int 11) > + (const_int 12) (const_int 13) > + (const_int 14) (const_int 15) > + (const_int 40) (const_int 41) > + (const_int 42) (const_int 43) > + (const_int 44) (const_int 45) > + (const_int 46) (const_int 47) > + (const_int 16) (const_int 17) > + (const_int 18) (const_int 19) > + (const_int 20) (const_int 21) > + (const_int 22) (const_int 23) > + (const_int 48) (const_int 49) > + (const_int 50) (const_int 51) > + (const_int 52) (const_int 53) > + (const_int 54) (const_int 55) > + (const_int 24) (const_int 25) > + (const_int 26) (const_int 27) > + (const_int 28) (const_int 29) > + (const_int 30) (const_int 31) > + (const_int 56) (const_int 57) > + (const_int 58) (const_int 59) > + (const_int 60) (const_int 61) > + (const_int 62) (const_int 63)])))] > + > + "TARGET_AVX512BW" > + "vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" > + [(set_attr "type" "sselog") > + (set_attr "prefix" "<mask_prefix>") > + (set_attr "mode" "XI")]) > + > +(define_insn "sse2_packssdw<mask_name>" > + [(set (match_operand:V8HI 0 "register_operand" "=x,Yw") > + (vec_concat:V8HI > + (ss_truncate:V4HI > + (match_operand:V4SI 1 "register_operand" "0,Yw")) > + (ss_truncate:V4HI > + (match_operand:V4SI 2 "vector_operand" "xBm,Ywm"))))] > + "TARGET_SSE2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>" > "@ > packssdw\t{%2, %0|%0, %2} > vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" > @@ -17794,7 +17871,59 @@ (define_insn "<sse2_avx2>_packssdw<mask_name>" > (set_attr "type" "sselog") > (set_attr "prefix_data16" "1,*") > (set_attr "prefix" "orig,<mask_prefix>") > - (set_attr "mode" "<sseinsnmode>")]) > + (set_attr "mode" "TI")]) > + > +(define_insn "avx2_packssdw<mask_name>" > + [(set (match_operand:V16HI 0 "register_operand" "=Yw") > + (vec_select:V16HI > + (vec_concat:V16HI > + (ss_truncate:V8HI > + (match_operand:V8SI 1 "register_operand" "Yw")) > + (ss_truncate:V8HI > + (match_operand:V8SI 2 "vector_operand" "Ywm"))) > + (parallel [(const_int 0) (const_int 1) > + (const_int 2) (const_int 3) > + (const_int 8) (const_int 9) > + (const_int 10) (const_int 11) > + (const_int 4) (const_int 5) > + (const_int 6) (const_int 7) > + (const_int 12) (const_int 13) > + (const_int 14) (const_int 15)])))] > + "TARGET_AVX2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>" > + "vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" > + [(set_attr "type" "sselog") > + (set_attr "prefix" "<mask_prefix>") > + (set_attr "mode" "OI")]) > + > +(define_insn "avx512bw_packssdw<mask_name>" > + [(set (match_operand:V32HI 0 "register_operand" "=v") > + (vec_select:V32HI > + (vec_concat:V32HI > + (ss_truncate:V16HI > + (match_operand:V16SI 1 "register_operand" "v")) > + (ss_truncate:V16HI > + (match_operand:V16SI 2 "vector_operand" "vm"))) > + (parallel [(const_int 0) (const_int 1) > + (const_int 2) (const_int 3) > + (const_int 16) (const_int 17) > + (const_int 18) (const_int 19) > + (const_int 4) (const_int 5) > + (const_int 6) (const_int 7) > + (const_int 20) (const_int 21) > + (const_int 22) (const_int 23) > + (const_int 8) (const_int 9) > + (const_int 10) (const_int 11) > + (const_int 24) (const_int 25) > + (const_int 26) (const_int 27) > + (const_int 12) (const_int 13) > + (const_int 14) (const_int 15) > + (const_int 28) (const_int 29) > + (const_int 30) (const_int 31)])))] > + "TARGET_AVX512BW" > + "vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" > + [(set_attr "type" "sselog") > + (set_attr "prefix" "<mask_prefix>") > + (set_attr "mode" "XI")]) > > ;; This is different from rtl unsigned saturation, the instruction does > ;; unsigned saturation for signed value. > diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c b/gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c > new file mode 100644 > index 00000000000..ae839e8d2c6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c > @@ -0,0 +1,55 @@ > +/* { dg-do run } */ > +/* { dg-options "-O2 -mavx512bw" } */ > +/* { dg-require-effective-target avx512bw } */ > + > +#define AVX512BW > +#include "avx512f-helper.h" > + > +#define DST_SIZE (AVX512F_LEN / 16) > +#define SRC_SIZE (AVX512F_LEN / 32) > + > +#include "limits.h" > + > +#include "avx512f-mask-type.h" > + > +static short > +int_to_short (int iVal) > +{ > + short sVal; > + > + if (iVal < -32768) > + sVal = -32768; > + else if (iVal > 32767) > + sVal = 32767; > + else > + sVal = iVal; > + > + return sVal; > +} > + > +void > +TEST (void) > +{ > + union512i_d s1, s2; > + union512i_w res1; > + short dst_ref[32]; > + int i; > + > + s1.x = _mm512_set_epi32 (1, 2, 3, 4, 65000, 20, 30, 90, 88, 44, 33, 22, 11, 98, 76, -65000); > + s2.x = _mm512_set_epi32 (80, 40, 31, 21, 10, 99, 74, -65000, 2, 3, 4, 5, 65010, 21, 31, 91); > + res1.x = _mm512_packs_epi32 (s1.x, s2.x); > + for (int i = 0; i != 4; i++) > + { > + dst_ref[i] = int_to_short (s1.a[i]); > + dst_ref[i + 4] = int_to_short (s2.a[i]); > + dst_ref[i + 8] = int_to_short (s1.a[i + 4]); > + dst_ref[i + 12] = int_to_short (s2.a[i + 4]); > + dst_ref[i + 16] = int_to_short (s1.a[i + 8]); > + dst_ref[i + 20] = int_to_short (s2.a[i + 8]); > + dst_ref[i + 24] = int_to_short (s1.a[i + 12]); > + dst_ref[i + 28] = int_to_short (s2.a[i + 12]); > + } > + > + if (check_union512i_w (res1, dst_ref)) > + abort (); > +} > diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c b/gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c > new file mode 100644 > index 00000000000..056c735ae0e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c > @@ -0,0 +1,50 @@ > +/* { dg-do run } */ > +/* { dg-options "-O2 -mavx512bw" } */ > +/* { dg-require-effective-target avx512bw } */ > + > +#define AVX512BW > +#include "avx512f-helper.h" > + > +static char > +short_to_byte (short iVal) > +{ > + short sVal; > + > + if (iVal < -128) > + sVal = -128; > + else if (iVal > 127) > + sVal = 127; > + else > + sVal = iVal; > + > + return sVal; > +} > + > +void > +TEST (void) > +{ > + union512i_w s1, s2; > + union512i_b res1; > + char dst_ref[64]; > + int i; > + > + s1.x = _mm512_set_epi16 (1, 2, 3, 4, 650, 20, 30, 90, 88, 44, 33, 22, 11, 98, 76, -650, > + 128, 230, -112, -128, -3, -4, -7, 9, 10, 11, 12, 13, -223, 10, 8, 11); > + s2.x = _mm512_set_epi16 (80, 40, 31, 21, 10, 99, 74, -650, 2, 3, 4, 5, 650, 21, 31, 91, > + 280, -140, 310, 20, 9, 98, 73, -651, 3, 4, 5, 6, 651, 22, 32, 92); > + res1.x = _mm512_packs_epi16 (s1.x, s2.x); > + for (int i = 0; i != 8; i++) > + { > + dst_ref[i] = short_to_byte (s1.a[i]); > + dst_ref[i + 8] = short_to_byte (s2.a[i]); > + dst_ref[i + 16] = short_to_byte (s1.a[i + 8]); > + dst_ref[i + 24] = short_to_byte (s2.a[i + 8]); > + dst_ref[i + 32] = short_to_byte (s1.a[i + 16]); > + dst_ref[i + 40] = short_to_byte (s2.a[i + 16]); > + dst_ref[i + 48] = short_to_byte (s1.a[i + 24]); > + dst_ref[i + 56] = short_to_byte (s2.a[i + 24]); > + } > + > + if (check_union512i_b (res1, dst_ref)) > + abort (); > +} > -- > 2.39.1.388.g2fc9e9ca3c > ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] Reimplement packuswb/packusdw with UNSPEC_US_TRUNCATE instead of original us_truncate. 2023-06-16 2:09 [PATCH 1/2] Reimplement packuswb/packusdw with UNSPEC_US_TRUNCATE instead of original us_truncate liuhongt 2023-06-16 2:09 ` [PATCH 2/2] Refined 256/512-bit vpacksswb/vpackssdw patterns liuhongt @ 2023-06-16 7:32 ` Uros Bizjak 1 sibling, 0 replies; 4+ messages in thread From: Uros Bizjak @ 2023-06-16 7:32 UTC (permalink / raw) To: liuhongt; +Cc: gcc-patches On Fri, Jun 16, 2023 at 4:12 AM liuhongt <hongtao.liu@intel.com> wrote: > > packuswb/packusdw does unsigned saturation for signed source, but rtl > us_truncate means does unsigned saturation for unsigned source. > So for value -1, packuswb will produce 0, but us_truncate produces > 255. The patch reimplement those related patterns and functions with > UNSPEC_US_TRUNCATE instead of us_truncate. > > The patch will fix below testcase which failed after > g:921b841350c4fc298d09f6c5674663e0f4208610 added constant-folding for US_TRUNCATE > > FAIL: gcc.target/i386/avx-vpackuswb-1.c execution test > FAIL: gcc.target/i386/avx2-vpackusdw-2.c execution test > FAIL: gcc.target/i386/avx2-vpackuswb-2.c execution test > FAIL: gcc.target/i386/sse2-packuswb-1.c execution test > > Bootstrapped and regtested on x86_64-pc-linux-gnu. > Ok for trunk? Please proofread the ChangeLog entries and comments and fix confusion with truncation / saturation in comments. OK with the above change. Thanks, Uros. > > gcc/ChangeLog: > > PR target/110235 > * config/i386/i386-expand.cc (ix86_split_mmx_pack): Use > UNSPEC_US_TRUNCATE instead of original us_truncate for > packusdw/packuswb. > * config/i386/mmx.md (mmx_pack<s_trunsuffix>swb): Splitted to > below 2 new patterns. Just say: ...: Substitute with ... > (mmx_packsswb): New reload_completed define_insn_and_split. ...: ... this and ... > (mmx_packuswb): Ditto. ...: ... this. > (mmx_packusdw): Use UNSPEC_US_TRUNCATE instead of original > us_truncate. > (s_trunsuffix): Removed. ...: Remove code iterator. > (any_s_truncate): Removed. ...: Ditto. > * config/i386/sse.md (<sse2_avx2>_packuswb<mask_name>): Use > UNSPEC_US_TRUNCATE instead of original us_truncate. > (<sse4_1_avx2>_packusdw<mask_name>): Ditto. > * config/i386/i386.md (UNSPEC_US_TRUNCATE): New unspec_c_enum. > --- > gcc/config/i386/i386-expand.cc | 20 ++++++++++++---- > gcc/config/i386/i386.md | 4 ++++ > gcc/config/i386/mmx.md | 43 ++++++++++++++++++++++------------ > gcc/config/i386/sse.md | 20 ++++++++-------- > 4 files changed, 57 insertions(+), 30 deletions(-) > > diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc > index def060ab562..35e2740f9b6 100644 > --- a/gcc/config/i386/i386-expand.cc > +++ b/gcc/config/i386/i386-expand.cc > @@ -1019,6 +1019,7 @@ ix86_split_mmx_pack (rtx operands[], enum rtx_code code) > rtx op0 = operands[0]; > rtx op1 = operands[1]; > rtx op2 = operands[2]; > + rtx src; > > machine_mode dmode = GET_MODE (op0); > machine_mode smode = GET_MODE (op1); > @@ -1042,11 +1043,20 @@ ix86_split_mmx_pack (rtx operands[], enum rtx_code code) > op1 = lowpart_subreg (sse_smode, op1, GET_MODE (op1)); > op2 = lowpart_subreg (sse_smode, op2, GET_MODE (op2)); > > - op1 = gen_rtx_fmt_e (code, sse_half_dmode, op1); > - op2 = gen_rtx_fmt_e (code, sse_half_dmode, op2); > - rtx insn = gen_rtx_SET (dest, gen_rtx_VEC_CONCAT (sse_dmode, > - op1, op2)); > - emit_insn (insn); > + /* For packusdw/packuswb, it does unsigned saturation for > + signed source which is different for rtl US_TRUNCATE. */ paskusdw/packuswb does unsigned saturation of a signed source which is different from generic us_truncate RTX. > + if (code == US_TRUNCATE) > + src = gen_rtx_UNSPEC (sse_dmode, > + gen_rtvec (2, op1, op2), > + UNSPEC_US_TRUNCATE); > + else > + { > + op1 = gen_rtx_fmt_e (code, sse_half_dmode, op1); > + op2 = gen_rtx_fmt_e (code, sse_half_dmode, op2); > + src = gen_rtx_VEC_CONCAT (sse_dmode, op1, op2); > + } > + > + emit_move_insn (dest, src); > > ix86_move_vector_high_sse_to_mmx (op0); > } > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md > index 0929115ed4d..070a84d8af9 100644 > --- a/gcc/config/i386/i386.md > +++ b/gcc/config/i386/i386.md > @@ -129,6 +129,10 @@ (define_c_enum "unspec" [ > UNSPEC_RSQRT > UNSPEC_PSADBW > > + ;; US_TRUNCATE this is different from rtl us_truncate, > + ;; it does unsigned truncation for signed source. Different from generic us_truncate RTX as it does unsigned saturation of signed source. > + UNSPEC_US_TRUNCATE > + > ;; For AVX/AVX512F support > UNSPEC_SCALEF > UNSPEC_PCMP > diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md > index 6fbe3909c8b..315eb4193c4 100644 > --- a/gcc/config/i386/mmx.md > +++ b/gcc/config/i386/mmx.md > @@ -3337,27 +3337,41 @@ (define_split > ;; > ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; > > -;; Used in signed and unsigned truncations with saturation. > -(define_code_iterator any_s_truncate [ss_truncate us_truncate]) > -;; Instruction suffix for truncations with saturation. > -(define_code_attr s_trunsuffix [(ss_truncate "s") (us_truncate "u")]) > - > -(define_insn_and_split "mmx_pack<s_trunsuffix>swb" > +(define_insn_and_split "mmx_packsswb" > [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw") > (vec_concat:V8QI > - (any_s_truncate:V4QI > + (ss_truncate:V4QI > (match_operand:V4HI 1 "register_operand" "0,0,Yw")) > - (any_s_truncate:V4QI > + (ss_truncate:V4QI > (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))))] > "TARGET_MMX || TARGET_MMX_WITH_SSE" > "@ > - pack<s_trunsuffix>swb\t{%2, %0|%0, %2} > + packsswb\t{%2, %0|%0, %2} > + # > + #" > + "&& reload_completed > + && SSE_REGNO_P (REGNO (operands[0]))" > + [(const_int 0)] > + "ix86_split_mmx_pack (operands, SS_TRUNCATE); DONE;" > + [(set_attr "mmx_isa" "native,sse_noavx,avx") > + (set_attr "type" "mmxshft,sselog,sselog") > + (set_attr "mode" "DI,TI,TI")]) > + This instruction does unsigned saturation of signed source and is different from generic us_truncate RTX. > +(define_insn_and_split "mmx_packuswb" > + [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw") > + (unspec:V8QI > + [(match_operand:V4HI 1 "register_operand" "0,0,Yw") > + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")] > + UNSPEC_US_TRUNCATE))] > + "TARGET_MMX || TARGET_MMX_WITH_SSE" > + "@ > + packuswb\t{%2, %0|%0, %2} > # > #" > "&& reload_completed > && SSE_REGNO_P (REGNO (operands[0]))" > [(const_int 0)] > - "ix86_split_mmx_pack (operands, <any_s_truncate:CODE>); DONE;" > + "ix86_split_mmx_pack (operands, US_TRUNCATE); DONE;" > [(set_attr "mmx_isa" "native,sse_noavx,avx") > (set_attr "type" "mmxshft,sselog,sselog") > (set_attr "mode" "DI,TI,TI")]) > @@ -3384,11 +3398,10 @@ (define_insn_and_split "mmx_packssdw" > > (define_insn_and_split "mmx_packusdw" > [(set (match_operand:V4HI 0 "register_operand" "=Yr,*x,Yw") > - (vec_concat:V4HI > - (us_truncate:V2HI > - (match_operand:V2SI 1 "register_operand" "0,0,Yw")) > - (us_truncate:V2HI > - (match_operand:V2SI 2 "register_operand" "Yr,*x,Yw"))))] > + (unspec:V4HI > + [(match_operand:V2SI 1 "register_operand" "0,0,Yw") > + (match_operand:V2SI 2 "register_operand" "Yr,*x,Yw")] > + UNSPEC_US_TRUNCATE))] > "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE" > "#" > "&& reload_completed" > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 7d4b4ec8df5..83e3f534fd2 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -17796,13 +17796,14 @@ (define_insn "<sse2_avx2>_packssdw<mask_name>" > (set_attr "prefix" "orig,<mask_prefix>") > (set_attr "mode" "<sseinsnmode>")]) > > +;; This is different from rtl unsigned saturation, the instruction does > +;; unsigned saturation for signed value. This instruction does unsigned saturation of signed source and is different from generic us_truncate RTX. > (define_insn "<sse2_avx2>_packuswb<mask_name>" > [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,<v_Yw>") > - (vec_concat:VI1_AVX512 > - (us_truncate:<ssehalfvecmode> > - (match_operand:<sseunpackmode> 1 "register_operand" "0,<v_Yw>")) > - (us_truncate:<ssehalfvecmode> > - (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,<v_Yw>m"))))] > + (unspec:VI1_AVX512 > + [(match_operand:<sseunpackmode> 1 "register_operand" "0,<v_Yw>") > + (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,<v_Yw>m")] > + UNSPEC_US_TRUNCATE))] > "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" > "@ > packuswb\t{%2, %0|%0, %2} > @@ -21889,11 +21890,10 @@ (define_insn "<sse4_1_avx2>_mpsadbw" > > (define_insn "<sse4_1_avx2>_packusdw<mask_name>" > [(set (match_operand:VI2_AVX2 0 "register_operand" "=Yr,*x,<v_Yw>") > - (vec_concat:VI2_AVX2 > - (us_truncate:<ssehalfvecmode> > - (match_operand:<sseunpackmode> 1 "register_operand" "0,0,<v_Yw>")) > - (us_truncate:<ssehalfvecmode> > - (match_operand:<sseunpackmode> 2 "vector_operand" "YrBm,*xBm,<v_Yw>m"))))] > + (unspec:VI2_AVX2 > + [(match_operand:<sseunpackmode> 1 "register_operand" "0,0,<v_Yw>") > + (match_operand:<sseunpackmode> 2 "vector_operand" "YrBm,*xBm,<v_Yw>m")] > + UNSPEC_US_TRUNCATE))] > "TARGET_SSE4_1 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" > "@ > packusdw\t{%2, %0|%0, %2} > -- > 2.39.1.388.g2fc9e9ca3c > ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-06-16 7:37 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-06-16 2:09 [PATCH 1/2] Reimplement packuswb/packusdw with UNSPEC_US_TRUNCATE instead of original us_truncate liuhongt 2023-06-16 2:09 ` [PATCH 2/2] Refined 256/512-bit vpacksswb/vpackssdw patterns liuhongt 2023-06-16 7:37 ` Uros Bizjak 2023-06-16 7:32 ` [PATCH 1/2] Reimplement packuswb/packusdw with UNSPEC_US_TRUNCATE instead of original us_truncate Uros Bizjak
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).